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ZYL (17")
a
PCB 6L STACK UP
Intel Bay Trail-M Platform Block Diagram
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LAYER 1 : TOP
D LAYER 2 : SVCC D
t
LAYER 3 : IN1(High)
LAYER 4 : IN2(Low)
LAYER 5 : SGND
LAYER 6 : BOT
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GPU
PCIE Gen 2 x 2 Lane 27 Mhz
DDR3L SO-DIMM 0 Port0 & Port1
N15V-GM (GeForce 820M) PAGE 15
DDR3L 1066MT/s PCIE0 & PCIE1
e
Maximum 8GB
PAGE 13~18
PAGE 11
DDI 1
Intel Bay Trail-M eDP
d
PAGE 20
SATA - HDD
SATA0 3GB/s
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Package : 9.5 (mm)
Power : PAGE 23 DDI 0 HDMI Conn PAGE 20
f
C Power : 7.5 Watt C
SATA - ODD 32.768KHz

SATA1 3GB/s Package : FCBGA 1170 PAGE 6
Package : 9.5 (mm)
Power : PAGE 22 Size : 25 x 27 (mm)
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25 Mhz
PAGE 6
o
USB3.0 Port0
1.8V BIOS+TXE USB3.0 Conn PAGE 25
SPI ROM(64Mb) SPI Interface
C
PAGE 6 Port0
PAGE 2~10 USB 2.0 Interface
Port3 Port2 Port1
Azalia USB Hub
Camera
B GL850G-OHY31 12 Mhz B
TPM
a
PAGE 28 PAGE 20 Package : QFN-28 PAGE 24
LPC Interface PCIE Gen 2 x 1 Lane
Size : 5 x 5 (mm) PAGE 24
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Port3 Port2
Embedded Controller Audio Codec LAN Half Mini Card Card Reader USB2.0 Port x 2
3.3V EC code
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NPCE985LB1 ALC283 RTL8111 GS-CG USB Hub -4 USB Hub -2
SPI ROM(1Mb) GL834L USB Hub -3
PAGE 23 25 Mhz
Power : Power : Power : Power :
PAGE 27 WLAN / BT Combo PAGE 24
a
KB Package : LQPF128 Package : QFN-48 Package : QFN-32 Package : QFN-32
Keyboard
PAGE 21
Size : 14 x 14 (mm) Size : 6 x 6 (mm) Size : 4 x 4 (mm) Size : 4 x 4 (mm)
PS2
Touch Pad PAGE 19 PAGE 26 PAGE 27 PAGE 28 PAGE 25
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PAGE 21
I/O board (card reader+LED)
I2C FAN Speaker
PAGE 22
A PAGE 26 A
I2C from CPU
PAGE 21 Universal Jack
Q
Headphone + MIC
PAGE 26
Quanta Computer Inc.
Analog MIC PROJECT : ZYL/ZYLA
Size Document Number Rev
PAGE 26 Intel Block Diagram 1A
Date: Thursday, July 10, 2014 Sheet 1 of 44

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[11] M_A_A[15:0]
M_A_A0
M_A_A1
M_A_A2
K45
H47
L41
U29A
DRAM0_MA_00
DRAM0_MA_11
DRAM0_DQ_00
DRAM0_DQ_11
M36
J36
P40
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ[63:0] [11]
a
M_A_A3 H44 DRAM0_MA_22 DRAM0_DQ_22 M40 M_A_DQ3
M_A_A4 H50 DRAM0_MA_33 DRAM0_DQ_33 P36 M_A_DQ4
M_A_A5 G53 DRAM0_MA_44 DRAM0_DQ_44 N36 M_A_DQ5
M_A_A6 DRAM0_MA_55 DRAM0_DQ_55 M_A_DQ6
i
H49 K40
M_A_A7 D50 DRAM0_MA_66 DRAM0_DQ_66 K42 M_A_DQ7
M_A_A8 G52 DRAM0_MA_77 DRAM0_DQ_77 B32 M_A_DQ8
D M_A_A9 E52 DRAM0_MA_88 DRAM0_DQ_88 C32 M_A_DQ9 D
DRAM0_MA_99 DRAM0_DQ09_C32
t
M_A_A10 K48 C36 M_A_DQ10
M_A_A11 E51 DRAM0_MA_1010 DRAM0_DQ_1010 A37 M_A_DQ11
M_A_A12 F47 DRAM0_MA_1111 DRAM0_DQ_1111 C33 M_A_DQ12
M_A_A13 J51 DRAM0_MA_1212 DRAM0_DQ_1212 A33 M_A_DQ13
M_A_A14 B49 DRAM0_MA_1313 DRAM0_DQ_1313 C37 M_A_DQ14
M_A_A15 B50 DRAM0_MA_1414 DRAM0_DQ_1414 B38 M_A_DQ15
DRAM0_MA_1515 DRAM0_DQ_1515 F36 M_A_DQ16
n
M_A_DM0 G36 DRAM0_DQ_1616 G38 M_A_DQ17
[11] M_A_DM0 M_A_DM1 DRAM0_DM_00 DRAM0_DQ_1717 M_A_DQ18
B36 F42
F38 J42
B42 G40
P51 C38
V42 G44
e
Y50 D42
Y52 A41
[11] M_A_DM7 DRAM0_DM_77 DRAM0_DQ_2424 M_A_DQ25
C41
M_A_RAS# M45 DRAM0_DQ_2525 A45 M_A_DQ26
[11] M_A_RAS# DRAM0_RAS DRAM0_DQ_2626
M_A_CAS# M44 B46 M_A_DQ27
[11] M_A_CAS# DRAM0_CAS DRAM0_DQ_2727
M_A_WE# H51 C40 M_A_DQ28
[11] M_A_WE# DRAM0_WE DRAM0_DQ_2828 B40 M_A_DQ29
d
M_A_BS#0 K47 DRAM0_DQ_2929 B48 M_A_DQ30
[11] M_A_BS#0 DRAM0_BS_00 DRAM0_DQ_3030
M_A_BS#1 K44 B47 M_A_DQ31
[11] M_A_BS#1 DRAM0_BS_11 DRAM0_DQ_3131
M_A_BS#2 D52 K52 M_A_DQ32
[11] M_A_BS#2 DRAM0_BS_22 DRAM0_DQ_3232 M_A_DQ33
i
K51
M_A_CS#0 P44 DRAM0_DQ_3333 T52 M_A_DQ34
[11] M_A_CS#0 DRAM0_CS_0 DRAM0_DQ_3434 T51 M_A_DQ35
M_A_CS#1 P45 DRAM0_DQ_3535 L51 M_A_DQ36
[11] M_A_CS#1 DRAM0_CS_2 DRAM0_DQ_3636 L53 M_A_DQ37
f
DRAM0_DQ_3737 R51 M_A_DQ38
C M_A_CKE0 C47 DRAM0_DQ_3838 R53 M_A_DQ39 C
[11] M_A_CKE0 DRAM0_CKE_00 DRAM0_DQ_3939
D48 T47 M_A_DQ40
M_A_CKE1 F44 RESERVED_D48 DRAM0_DQ_4040 T45 M_A_DQ41
[11] M_A_CKE1 DRAM0_CKE_22 DRAM0_DQ_4141
E46 Y40 M_A_DQ42
RESERVED_E46 DRAM0_DQ_4242 V41 M_A_DQ43
T41 DRAM0_DQ_4343 T48 M_A_DQ44
n
[11] M_A_ODT0 DRAM0_ODT_0 DRAM0_DQ_4444 T50 M_A_DQ45
P42 DRAM0_DQ_4545 Y42 M_A_DQ46
[11] M_A_ODT1 DRAM0_ODT_2 DRAM0_DQ_4646 AB40 M_A_DQ47
DRAM0_DQ_4747 V45 M_A_DQ48
M_A_CLK0 M50 DRAM0_DQ_4848 V47 M_A_DQ49
+1.35VSUS [11] M_A_CLK0 DRAM0_CKP_0 DRAM0_DQ_4949
M_A_CLK0# M48 AD48 M_A_DQ50
[11] M_A_CLK0# DRAM0_CKN_0 DRAM0_DQ_5050 AD50 M_A_DQ51
o
M_A_CLK1 P50 DRAM0_DQ_5252 V50 M_A_DQ53
[11] M_A_CLK1 DRAM0_CKP_2 DRAM0_DQ_5353
R431 M_A_CLK1# P48 AB44 M_A_DQ54
[11] M_A_CLK1# DRAM0_CKN_2 DRAM0_DQ_5454
4.7K_4 Y45 M_A_DQ55
DRAM0_DQ_5656 W51 M_A_DQ57
CPU_VREF M_A_DRAMRST# P41 DRAM0_DQ_5757 AC53 M_A_DQ58
[11] M_A_DRAMRST# DRAM0_DRAMRST DRAM0_DQ_5858 AC51 M_A_DQ59
DRAM0_DQ_5959 W53 M_A_DQ60
C
R430 C435 DRAM0_DQ_6060 Y51 M_A_DQ61
4.7K_4 CPU_VREF AF44 DRAM0_DQ_6161 AD52 M_A_DQ62
0.1U/10V_4 DRAM_VREF DRAM0_DQ_6262 AD51 M_A_DQ63
DRAM0_DQ_6363
J38 M_A_DQS0
ICLK_DRAM_TERMN_0 DRAM0_DQSP_00 M_A_DQS#0 M_A_DQS0 [11]
GND R434 100K/F_4 AH42 K38
ICLK_DRAM_TERMN_1 ICLK_DRAM_TERMN DRAM0_DQSN_00 M_A_DQS1 M_A_DQS#0 [11]
GND GND R435 100K/F_4 AF42 C35
ICLK_DRAM_TERMN_AF42 DRAM0_DQSP_11 M_A_DQS#1 M_A_DQS1 [11]
B34
B DRAM0_DQSN_11 M_A_DQS2 M_A_DQS#1 [11] B
D40
a
SOC_DRAM_PWROK DRAM0_DQSP_22 M_A_DQS#2 M_A_DQS2 [11]
AD42 F40
SOC_VCCA_PWROK DRAM_VDD_S4_PWROK DRAM0_DQSN_22 M_A_DQS3 M_A_DQS#2 [11]
AB42 B44
DRAM_CORE_PWROK DRAM0_DQSP_33 M_A_DQS#3 M_A_DQS3 [11]
C43
DRAM0_DQSN_33 M_A_DQS4 M_A_DQS#3 [11]
N53
t
DRAM_RCOMP0 DRAM0_DQSP_44 M_A_DQS#4 M_A_DQS4 [11]
R432 23.2/F_4 AD44 M52
DRAM_RCOMP1 DRAM_RCOMP_00 DRAM0_DQSN_44 M_A_DQS5 M_A_DQS#4 [11]
GND R436 29.4/F_4 AF45 T42
DRAM_RCOMP2 DRAM_RCOMP_11 DRAM0_DQSP_55 M_A_DQS#5 M_A_DQS5 [11]
R433 162/F_4 AD45 T44
DRAM_RCOMP_22 DRAM0_DQSN_55 M_A_DQS6 M_A_DQS#5 [11]
Y47
+1.35VSUS [8,11,36,37] DRAM0_DQSP_66 M_A_DQS#6 M_A_DQS6 [11]
Y48
+3V_S5 [9,12,19,21,24,27,28,34,35,37,39,40] DRAM0_DQSN_66 M_A_DQS7 M_A_DQS#6 [11]
AF40 AB52
RESERVED_AF40 DRAM0_DQSP_77 M_A_DQS#7 M_A_DQS7 [11]
AF41 AA51
n
RESERVED_AF41 DRAM0_DQSN_77 M_A_DQS#7 [11]
AD40
AD41 RESERVED_AD40
RESERVED_AD41
1 OF 13
VLV_M_D/BGA
a
REV = 1.15
+1.35VSUS
+3V_S5
+1.35VSUS
+3V_S5
R389
u
R382 10K_4
4.7K_4 R390
R383 10K_4
4.7K_4
HWPG_1.35V R388 SOC_DRAM_PWROK
DRM_PWOK_C1 *short_0/J_4
A SOC_VCCA_PWROK A
3
C417 DRM_PWOK_C2
SLP_S4# 5 2
[6,12] SLP_S4#
6
*0.1U/10V_4 C416
Q
3
Q43A Q43B EC_PWROK 2

[12,19] EC_PWROK
4
PJ4N3KDW PJ4N3KDW 5 *0.1U/10V_4

Q44B
GND Q44A 1 PJ4N3KDW Quanta Computer Inc.
4
PJ4N3KDW
GND HWPG_1.35V [36]

GND
PROJECT : ZYL/ZYLA
GND Valley 1/9 (DDRA) 1A

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U29B
3
a
AY45 BG38
BB47 DRAM1_MA_00 DRAM1_DQ_00 BC40
DRAM1_MA_11 DRAM1_DQ_11
i
AW41 BA42
BB44 DRAM1_MA_22 DRAM1_DQ_22 BD42
BB50 DRAM1_MA_33 DRAM1_DQ_33 BC38
D BC53 DRAM1_MA_44 DRAM1_DQ_44 BD36 D
DRAM1_MA_55 DRAM1_DQ_55
t
BB49 BF42
BF50 DRAM1_MA_66 DRAM1_DQ_66 BC44
BC52 DRAM1_MA_77 DRAM1_DQ_77 BH32
BE52 DRAM1_MA_88 DRAM1_DQ_88 BG32
AY48 DRAM1_MA_99 DRAM1_DQ_99 BG36
BE51 DRAM1_MA_1010 DRAM1_DQ_1010 BJ37
BD47 DRAM1_MA_1111 DRAM1_DQ_1111 BG33
n
BA51 DRAM1_MA_1212 DRAM1_DQ_1212 BJ33
BH49 DRAM1_MA_1313 DRAM1_DQ_1313 BG37
BH50 DRAM1_MA_1414 DRAM1_DQ_1414 BH38
DRAM1_MA_1515 DRAM1_DQ_1515 AU36
BD38 DRAM1_DQ_1616 AT36
BH36 DRAM1_DM_00 DRAM1_DQ_1717 AV40
e
BC36 DRAM1_DM_11 DRAM1_DQ_1818 AT40
BH42 DRAM1_DM_22 DRAM1_DQ_1919 BA36
AT51 DRAM1_DM_33 DRAM1_DQ_2020 AV36
AM42 DRAM1_DM_44 DRAM1_DQ_2121 AY42
AK50 DRAM1_DM_55 DRAM1_DQ_2222 AY40
AK52 DRAM1_DM_66 DRAM1_DQ_2323 BJ41
DRAM1_DM_77 DRAM1_DQ_2424 BG41
d
AV45 DRAM1_DQ_2525 BJ45
AV44 DRAM1_RAS DRAM1_DQ_2626 BH46
BB51 DRAM1_CAS DRAM1_DQ_2727 BG40
DRAM1_WE DRAM1_DQ_2828
i
BH40
AY47 DRAM1_DQ_2929 BH48
AY44 DRAM1_BS_00 DRAM1_DQ_3030 BH47
BF52 DRAM1_BS_11 DRAM1_DQ_3131 AY52
DRAM1_BS_22 DRAM1_DQ_3232 AY51
f
AT44 DRAM1_DQ_3333 AP52
C DRAM1_CS_0 DRAM1_DQ_3434 AP51 C
AT45 DRAM1_DQ_3535 AW51
DRAM1_CS_2 DRAM1_DQ_3636 AW53
DRAM1_DQ_3737 AR51
BG47 DRAM1_DQ_3838 AR53
BE46 DRAM1_CKE_00 DRAM1_DQ_3939 AP47
n
BD44 RESERVED_BE46 DRAM1_DQ_4040 AP45
BF48 DRAM1_CKE_22 DRAM1_DQ_4141 AK40
RESERVED_BF48 DRAM1_DQ_4242 AM41
AP41 DRAM1_DQ_4343 AP48
DRAM1_ODT_0 DRAM1_DQ_4444 AP50
AT42 DRAM1_DQ_4545 AK42
DRAM1_ODT_2 DRAM1_DQ_4646 AH40
o
DRAM1_DQ_4747 AM45
AV50 DRAM1_DQ_4848 AM47
AV48 DRAM1_CKP_0 DRAM1_DQ_4949 AF48
DRAM1_CKN_0 DRAM1_DQ_5050 AF50
DRAM1_DQ_5151 AM48
DRAM1_DQ_5252 AM50
AT50 DRAM1_DQ_5353 AH44
AT48 DRAM1_CKP_2 DRAM1_DQ_5454 AK45
DRAM1_CKN_2 DRAM1_DQ_5555 AM52
C
DRAM1_DQ_5656 AL51
DRAM1_DQ_5757 AG53
AT41 DRAM1_DQ_5858 AG51
DRAM1_DRAMRST DRAM1_DQ_5959 AL53
DRAM1_DQ_6060 AK51
DRAM1_DQ_6161 AF52
DRAM1_DQ_6262 AF51
DRAM1_DQ_6363
B BF40 B
a
DRAM1_DQSP_00 BD40
DRAM1_DQSN_00 BG35
DRAM1_DQSP_11 BH34
DRAM1_DQSN_11 BA38
t
DRAM1_DQSP_22 AY38
DRAM1_DQSN_22 BH44
DRAM1_DQSP_33 BG43
DRAM1_DQSN_33 AU53
DRAM1_DQSP_44 AV52
DRAM1_DQSN_44 AP42
DRAM1_DQSP_55 AP44
n
DRAM1_DQSN_55 AK47
DRAM1_DQSP_66 AK48
DRAM1_DQSN_66 AH52
DRAM1_DQSP_77 AJ51
DRAM1_DQSN_77
a
2 OF 13
VLV_M_D/BGA
REV = 1.15
u
A A
Q
PROJECT : ZYL/ZYLA
Valley 2/9 (DDRB) 1A

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U29C
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AV3 AG3
D [20] IN_D2 DDI0_TXP_0 DDI1_TXP_0 INT_eDP_TXP0 [20] D
AV2 AG1
t
[20] IN_D2# AT2 DDI0_TXN_0 DDI1_TXN_0 AF3 INT_eDP_TXN0 [20]
[20] IN_D1 AT3 DDI0_TXP_1 DDI1_TXP_1 AF2 INT_eDP_TXP1 [20]
[20] IN_D1# DDI0_TXN_1 DDI1_TXN_1 INT_eDP_TXN1 [20]
AR3 AD3
[20] IN_D0 AR1 DDI0_TXP_2 DDI1_TXP_2 AD2
[20] IN_D0# DDI0_TXN_2 DDI1_TXN_2
AP3 AC3
n
[20] IN_CLK AP2 DDI0_TXP_3 DDI1_TXP_3 AC1
[20] IN_CLK# DDI0_TXN_3 DDI1_TXN_3
AL3 AK3 INT_eDP_AUXP [20]
AL1 DDI0_AUXP DDI1_AUXP AK2
DDI0_AUXN DDI1_AUXN INT_eDP_AUXN [20]
e
D27 K30
[20] HDMI_HPD_CON DDI0_HPD DDI1_HPD DDI1_EDP_HPD_R [20]
C26 P30 DDI1_DDCDATA R266 2.2K_4
[20] SDVO_DATA C28 DDI0_DDCDATA DDI1_DDCDATA G30 DDI1_DDCCLK R265 *2.2K_4
+1.8V
[20] SDVO_CLK DDI0_DDCCLK DDI1_DDCCLK DDI1_DDCCLK in eDP/DP Mode : Unused
d
1.8V Pull High on p.13 HDMI B28 N30 PCH_DISP_ON_C
C27 DDI0_VDDEN DDI1_VDDEN J30 PCH_EDP_BLON_C
B26 DDI0_BKLTEN DDI1_BKLTEN M30 PCH_DPST_PWM_C
i
DDI0_BKLTCTL DDI1_BKLTCTL
R174
402/F_4 SOC_DDIO_RCOMP AK13 AH14 Q47A
SOC_DDIO_RCOMP_P AK12 DDI0_RCOMP RESERVED_AH14 AH13 PJ4N3KDW
f
AM14 DDI0_RCOMP_P RESERVED_AH13 AF14
C RESERVED_AM14 RESERVED_AF14 C
AM13 AF13 PCH_DISP_ON_C 4 3
RESERVED_AM13 RESERVED_AF13 PCH_DISP_ON [20]
AM3 AH3
AM2 VSS_AM3 VSS_AH3 AH2
VSS_AM2 VSS_AH2
5
BA3 R551 200K/F_4
VGA_RED AY2 GND
VGA_BLUE +1.8V +3V
GND BA1 R553 200K/F_4
VGA_GREEN AW1
VGA_IREF
2
AY3
VGA_IRTN
o
BD2 PCH_EDP_BLON_C 1 6
+1.8V [5,6,7,9,12,19,20,21,27,28,37] VGA_HSYNC PCH_EDP_BLON [19,22]
BF2
+3V [5,7,9,11,12,13,17,19,20,22,24,25,26,27,28,35,37,39,40] VGA_VSYNC
BC1 VGA/CRT No Used
VGA_DDCCLK BC2 Q47B
VGA_DDCDATA VGA DDCCLK/DDCDATA need link GND. PJ4N3KDW
C
T2 T7
T3 RESERVED_T2 RESERVED_T7 T9 GND
AB3 RESERVED_T3 RESERVED_T9 AB13 +3V
AB2 RESERVED_AB3 RESERVED_AB13 AB12 +1.8V
Y3 RESERVED_AB2 RESERVED_AB12 Y12
Y2 RESERVED_Y3 RESERVED_Y12 Y13
W3 RESERVED_Y2 RESERVED_Y13 V10 R290
W1 RESERVED_W3 RESERVED_V10 V9 4.7K/J_4
a
B B
V2 RESERVED_W1 RESERVED_V9 T12
RESERVED_V2 RESERVED_T12
2
V3 T10
R3 RESERVED_V3 RESERVED_T10 V14
t
R1 RESERVED_R3 RESERVED_V14 V13 PCH_DPST_PWM_C 1 3 PCH_DPST_PWM
RESERVED_R1 RESERVED_V13 PCH_DPST_PWM [20]
+1.8V AD6 T14
AD4 RESERVED_AD6 RESERVED_T14 T13 Q37
AB9 RESERVED_AD4 RESERVED_T13 T6 PJA138K
AB7 RESERVED_AB9 RESERVED_T6 T4
RESERVED_AB7 RESERVED_T4
n
R513 Y4 P14
*10K_4 Y6 RESERVED_Y4 RESERVED_P14
V4 RESERVED_Y6
RESERVED_V4
Bay Trail-M Hardware Straps:
V6 K34
GPIO_NC13 A29 RESERVED_V6 RESERVED_K34 D32
a
GPIO_NC14 C29 GPIO_S0_NC13 GPIO_S0_NC26 N32
TP48 GPIO_S0_NC14_C29 GPIO_S0_NC25
AB14 J34
R512 INTD_DSI_TE B30 RESERVED_AB14 GPIO_S0_NC24 K28
TP47 GPIO_S0_NC12 GPIO_S0_NC23
10K_4 C30 F28
RESERVED_C30 GPIO_S0_NC22 F32
GPIO_S0_NC21
u
D34
GPIO_S0_NC20 J28
GPIO_S0_NC18 D28
GND GPIO_S0_NC17 M32
3 OF 13 GPIO_S0_NC16 F34
A GPIO_S0_NC15 A
VLV_M_D/BGA
Q
REV = 1.15
PROJECT : ZYL/ZYLA
1A
Valley 3/9 (Display)
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U29D
a
BF6 AY7 C_PEG_TX0 EV@0.22u/10V_4 C422
[23] SATA_TXP0 SATA_TXP_0 PCIE_TXP_0 PEG_TX0 [13]
BG7 AY6 C_PEG_TX#0 EV@0.22u/10V_4 C426 PEG_TX#0 [13]
[23] SATA_TXN0 SATA_TXN_0 PCIE_TXN_0
SATA HDD
i
AU16 AT14 PEG_RX0 [13]
[23] SATA_RXP0 SATA_RXP_0 PCIE_RXP_0
AV16 AT13 PEG_RX#0 [13]
[23] SATA_RXN0 SATA_RXN_0 PCIE_RXN_0
D BD10 AV6 C_PEG_TX1 EV@0.22u/10V_4 C427 PEG_TX1 [13]
GPU x2 D
[22] SATA_TXP1 SATA_TXP1 PCIE_TXP_1
t
BF10 AV4 C_PEG_TX#1 EV@0.22u/10V_4 C431 PEG_TX#1 [13]
[22] SATA_TXN1 SATA_TXN_1 PCIE_TXN_1
SATA ODD AY16 AT10 PEG_RX1 [13]
[22] SATA_RXP1 SATA_RXP_1 PCIE_RXP_1
BA16 AT9 PEG_RX#1 [13]
[22] SATA_RXN1 SATA_RXN_1 PCIE_RXN_1
GND R144 *short_0/J_4 ICLK_SATA_TERMP BB10 AT7 PCIE_TXP2_WLAN_C C433 0.1U/10V_4

ICLK_SATA_TERMP PCIE_TXP_2 PCIE_TXP2_WLAN [28]
R128 *short_0/J_4 ICLK_SATA_TERMN BC10 AT6 PCIE_TXN2_WLAN_C C439 0.1U/10V_4
n
ICLK_SATA_TERMN PCIE_TXN_2 PCIE_TXN2_WLAN [28]
[12] SOC_KBC_SCI R133 *short_0/J_4 SATA_GP0 BA12 AP12 WLAN x1

SATA_GP1 SATA_GP0 PCIE_RXP_2 PCIE_RXP2_WLAN [28]
+1.8V R125 *10K_4 AY14 AP10
SATA_LED_R_N SATA_GP1 PCIE_RXN_2 PCIE_RXN2_WLAN [28]
R116 *10K_4 AY12
SATA_LED AP6 PCIE_TXP3_LAN_C C446 0.1U/10V_4
SATA_RCOMP_DP PCIE_TXP_3 PCIE_TXN3_LAN_C PCIE_TXP3_LAN [27]
AU18 AP4 C445 0.1U/10V_4
e
SATA_RCOMP_DN SATA_RCOMP_P_AU18 PCIE_TXN_3 PCIE_TXN3_LAN [27]
AT18
SATA_RCOMP_N_AT18 AP9 LAN x1
PCIE_RXP_3 PCIE_RXP3_LAN [27]
AP7
PCIE_RXN_3 PCIE_RXN3_LAN [27]
R173 AT22
MMC1_CLK BB7 VSS_BB7 R141 *short_0/J_4 +1.8V
402/F_4 AV20 VSS_BB7 BB5 VSS_BB5 R136 *short_0/J_4
MMC1_D0 VSS_BB5 GND
AU22
d
AV22 MMC1_D1 BG3 CLK_PEGA_REQ# CLK_PEGA_REQ# R127 10K_4
MMC1_D2 PCIE_CLKREQ_0 CLK_PEGA_REQ# [13]
AT20 BD7 PCIE_CLKREQ1# PCIE_CLKREQ1# R119 10K_4
AY24 MMC1_D3 PCIE_CLKREQ_1 BG5 PCIE_CLKREQ2_WLAN# PCIE_CLKREQ2_WLAN# R123 10K_4
MMC1_D4 PCIE_CLKREQ_2 PCIE_CLKREQ3_LAN# PCIE_CLKREQ2_WLAN# [28] PCIE_CLKREQ3_LAN#
i
AU26 BE3 R132 10K_4
MMC1_D5 PCIE_CLKREQ_3 PCIE_CLKREQ3_LAN# [27]
AT26 BD5
AU20 MMC1_D6 SD3_WP_BD5
+1.8V [4,6,7,9,12,19,20,21,27,28,37] MMC1_D7 SOC_PCIE_COMP
AP14 R171
AV26 PCIE_RCOMP_P_AP14_AP14 AP13 SOC_PCIE_COMN 402/F_4
f
BA24 MMC1_CMD PCIE_RCOMP_N_AP13_AP13
C MMC1_RST BB4 C
R121 49.9/F_4 MMC1_RCOMP AY18 RESERVED_BB4 BB3
GND MMC1_RCOMP RESERVED_BB3 AV10
RESERVED_AV10 AV9
BA18 RESERVED_AV9
AY20 SD2_CLK
n
BD20 SD2_D0 BF20 HDA_RCOMP R117 49.9/F_4
SD2_D1 HDA_LPE_RCOMP GND
BA20 BG22 ACZ_RST# R419 33_4
SD2_D2 HDA_RST PCH_AZ_CODEC_RST# [26]
BD18 BH20 ACZ_SYNC R418 33_4
SD2_D3_CD HDA_SYNC PCH_AZ_CODEC_SYNC [26]
BC18 BJ21 ACZ_BCLK R402 33_4
SD2_CMD HDA_CLK PCH_AZ_CODEC_BITCLK [26]
BG20 ACZ_SDOUT R401 33_4
HDA_SDO PCH_AZ_CODEC_SDOUT [26]
BG19 ACZ_SDIN0
201/04/18 : Add GPU Power Control Siganls HDA_SDI0 BG21
PCH_AZ_CODEC_SDIN0 [26]
o
AY26 HDA_SDI1 BH18
VGPU_EN AT28 SD3_CLK HDA_DOCKRST BG18
[39] VGPU_EN SD3_D0 HDA_DOCKEN
DGPU_HOLD_RST#_Q BD26
[12] DGPU_HOLD_RST#_Q SD3_D1
DGPU_PWR_EN_Q AU28 BF28
[12] DGPU_PWR_EN_Q SD3_D2 LPE_I2S2_CLK
DGPU_PWROK_Q BA26 BA30 BIOS_STRAP
[12] DGPU_PWROK_Q SD3_D3 LPE_I2S2_FRM
BC24 BC30 SOC_Override
DGPU_PW_CTRL# AV28 SD3_CD# LPE_I2S2_DATAOUT BD28
R567 100K/F_4 BF22 SD3_CMD LPE_I2S2_DATAIN
GND SD3_1P8EN
BD22 P34
C
SD3_PWREN RESERVED_P34 N34
R112 49.9/F_4 SD3_RCOMP BF26 RESERVED_N34
GND SD3_RCOMP AK9
RESERVED_AK9 AK7
201/04/18 : Add GPU Power Control Siganls RESERVED_AK7
C24 SOC_PROCHOT# R507 *short_0/J_4
PROCHOT H_PROCHOT# [19,35]
4 OF 13
B R496 71.5/F_4 B
+1.05V
a
VLV_M_D/BGA
REV = 1.15
t
High UMA Only Security Flash Descriptors
GPU power is control by PCH
0 = Override +1.8V
Low GPIO (Discrete, SG or Optimize)
R85 UMA@10K_4 1 = Normal Operation
+3V DGPU_PW_CTRL# R82 EV@10K_4 GND
SOC_Override
n
R88 *10K_4 R87
+1.8V
10K_4
Default NC No Pull High / Low
3
R86 *10K_4 BIOS_STRAP
+3V VGPU_EN R83 *10K_4 R386 *short_0/J_4 SOC_Override_NM 5 PJ4N3KDW
GND [19] EN_OVERRIDE Q45A
0 = LPC
a
R89 *10K_4
+1.8V R84
1 = SPI
4
*10K_4
R98 EV@10K_4
Default Pull High 10K(+3V)
+3V DGPU_HOLD_RST#_Q R109 *10K_4 GND
GND
R93 *10K_4
+1.8V
u
GND
R100 *10K_4
Default NC No Pull High / Low
+3V DGPU_PWR_EN_Q R97 *10K_4 GND
R91 *10K_4
A
+1.8V AC_PRESENT [6]
A
6
Default Pull Low 10K(GND) AC_PRESENT_NM

+3V R111 *10K_4
[19] AC_PRESENT_EC
R391 *short_0/J_4 2 Q45B AC Present: This input pin indicates when the
Q
DGPU_PWROK_Q R108 EV@10K_4
R118 *10K_4
GND PJ4N3KDW
platform is plugged into AC power.
+1.8V
1

GND
PROJECT : ZYL/ZYLA
Valley 4/9 (SD/PCIE/SATA) 1A

5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
6
+1.8V_S5 [7,9,12,21,37]
l
+1.8V [4,5,7,9,12,19,20,21,27,28,37]
C458 12P/50V_4
XTAL25_OUT
a
2
1
GND
Y12 R456 U29E
XTAL25_IN
i
25MHZ +-10PPM 1M_4 AH12 AU34
4 XTAL25_OUT AH10 ICLK_OSCIN SIO_UART1_RXD AV34
3 XTAL25_IN ICLK_OSCOUT SIO_UART1_TXD BA34
AD9 SIO_UART1_RTS AY34
RESERVED_AD9 SIO_UART1_CTS
t
GND
D D
C453 12P/50V_4 R463 4.02K/F_4 ICLK_ICOMP AD14 BF34
R462 47.5/F_4 ICLK_RCOMP AD13 ICLK_ICOMP SIO_UART2_RXD BD34
ICLK_RCOMP SIO_UART2_TXD BD32
AD10 SIO_UART2_RTS BF32 +1.8V_S5
GND AD12 RESERVED_AD10 SIO_UART2_CTS
RESERVED_AD12 PMU_BATLOW#_R R242 10K_4
n
[13] CLK_PCIE_VGAN AF6
AF4 PCIE_CLKN_00 D26 SUS_PWRDOWNACK R264 *short_0_4 SUS_PWRDOWNACK R263 10K_4
GPU [13] CLK_PCIE_VGAP PCIE_CLKP_00 PMC_SUSPWRDNACK G24
SUSWARN#_EC [19]
AF9 PMC_SUSCLK0_G24 F18 SOC_PMC_WAKE R243 10K_4
PCIE_CLKN_11 PMC_SLP_S0IX SLP_S0IX# [12]
AF7 F22
PCIE_CLKP_11 PMC_SLP_S4 SLP_S4# [2,12] AC_PRESENT
D22 R262 10K_4
e
PMC_SLP_S3 SLP_S3# [12]
J20
AK4 GPIO_S514_J20 D20 AC_PRESENT
[28] CLK_PCIE_WLANN PCIE_CLKN_22 PMC_ACPRESENT AC_PRESENT [5] +1.8V
AK6 F26 SOC_PMC_WAKE
WLAN [28] CLK_PCIE_WLANP PCIE_CLKP_22 PMC_WAKE_PCIE_0 K26 PMU_BATLOW#_R
SOC_PMC_WAKE [12]
AM4 PMC_BATLOW J26 SOC_REST_BTN R409 10K_4
[27] CLK_PCIE_LANN PCIE_CLKN_33 PMC_PWRBTN SOC_PWRBTN# [12]
AM6 BG9 SOC_REST_BTN
LAN [27] CLK_PCIE_LANP PCIE_CLKP_33 PMC_RSTBTN F20
d
PMC_PLTRST SOC_PLTRST# [12]
AM10 J24
AM9 RESERVED_AM10 GPIO_S517_J24 G18
RESERVED_AM9 PMC_SUS_STAT PCH_SLP_S0# [12]
i
C11 SOC_RTEST#
BH7 ILB_RTC_TEST
BH5 PMC_PLT_CLK_00
f
BH4 PMC_PLT_CLK_11
BH8 PMC_PLT_CLK_22 B10
PMC_PLT_CLK_33 PMC_RSMRST SOC_RSMRST# [12] +1.0V
BH6 B7 CORE_PWROK [12]
+1.8V_S5 BJ9 PMC_PLT_CLK_44 PMC_CORE_PWROK
SRT_CRST# C12 PMC_PLT_CLK_55
R248 51/F_4 XDP_H_TDO ILB_RTC_RST C9 RTC_X1
C R260 51/F_4 XDP_H_TMS XDP_H_TCK D14 ILB_RTC_X1 A9 RTC_X2 C
n
R228 51/F_4 XDP_H_TDI XDP_H_TRST# G12 TAP_TCK ILB_RTC_X2 B8 BRTC_EXTPAD C482 0.1U/10V_4 C293
TAP_TRST ILB_RTC_EXTPAD GND
R247 200/F_4 XDP_H_PREQ# XDP_H_TMS F14 *0.1u/10V_4 R526 R525 R527
XDP_H_TDI F12 TAP_TMS *71.5/F_4 71.5/F_4 *71.5/F_4
R229 51/F_4 XDP_H_TRST# XDP_H_TDO G16 TAP_TDI
R246 51/F_4 XDP_H_TCK XDP_H_PRDY# D18 TAP_TDO GND
TP28 TAP_PRDY
XDP_H_PREQ# F16 B24 SVID_ALERT#_SOC R517 20/F_4 VR_SVID_ALERT# VR_SVID_DATA
TAP_PREQ SVID_ALERT SVID_DATA_SOC VR_SVID_DATA VR_SVID_ALERT# [35] VR_SVID_ALERT#
AT34 A25 R518 16.9R_4
o
RESERVED SVID_DATA SVID_CLK_SOC VR_SVID_CLK VR_SVID_DATA [35] VR_SVID_CLK
C25 R519 *0/short_4
SOC_SPI_CS# SVID_CLK VR_SVID_CLK [35]
GND C23
C21 PCU_SPI_CS_00 intel check list 2.0: 70 Ω ±5% pull-up to V1P0S,
SOC_SPI_MISO B22 PCU_SPI_CS_11 AU32 TOUCHPANEL_INTR#_SOC R90 *10K_4 PLM does not have it, so use 71.5 Ω ±1% to replace.
SOC_SPI_MOSI A21 PCU_SPI_MISO SIO_PWM_00 AT32 SOC_SENS_HUB_RST# R96 *10K_4
+1.8V
SOC_SPI_CLK C22 PCU_SPI_MOSI SIO_PWM_11
PCU_SPI_CLK
+1.8V_S5 TP_INT# B18
C
Touch pad [21] TP_INT#
SOC_JTAG2_TCK B16 GPIO_S5_0 K24
SOC_JTAG2_TMS C18 GPIO_S5_1 GPIO_S5_22 N24
R505 10K_4 TP_INT# SOC_JTAG2_TDI A17 GPIO_S5_2 GPIO_S5_23 M20
R493 *10K_4 SOC_JTAG2_TCK SOC_JTAG2_TDO C17 GPIO_S5_3 GPIO_S5_24 J18
R494 *10K_4 SOC_JTAG2_TMS BOARD_ID4 C16 GPIO_S5_4 GPIO_S5_25 M18
R514 *10K_4 SOC_JTAG2_TDI BOARD_ID5 B14 GPIO_S5_5 GPIO_S5_26 K18
R504 *10K_4 SOC_JTAG2_TDO R492 *short_0/J_4 SOC_GPOI7 C15 GPIO_S5_6 GPIO_S5_27 K20
[12] SOC_KCB_SMI GPIO_S5_7 GPIO_S5_28 M22
GPIO_S5_29 M24 RTC Clock 32.768KHz
a
GPIO_S5_30
BOARD_ID1 C13
BOARD_ID2 A13 GPIO_S5_8 RTC_X1 15P/50V_4 C477
GPIO_S5_9
1
BOARD_ID3 C19 AV32
t
GPIO_S5_10 SIO_SPI_CS BA28
SIO_SPI_MISO AY28
R529 49.9/F_4 SOC_GPIO_RCOMP N26 SIO_SPI_MOSI AY30 R487 Y13
B GPIO_RCOMP 5 OF 13 SIO_SPI_CLK 10M_4 32.768KHZ B
RTC_X2 15P/50V_4 C476

VLV_M_D/BGA
2
n
GND REV = 1.15
2013/07/25 GND
change package , P/N change
from BG332768224 to
BG332768453
a
+1.8V_S5
SPI NOR FLASH +3V_RTC

BOARD ID RTC Circuitry(RTC)
u
+1.8V_S5
C513
R542 20K/J_4 SOC_RTEST#
U33 BOARD_ID1
0.1U/10V_4 R502 UMA@10K_4 R490 EV@10K_4 20mils
1
8 5 SOC_SPI_MOSI_R R563 *short_0/J_4 SOC_SPI_MOSI R503 *10K_4 BOARD_ID2 R491 10K_4 +3V_RTC_0 G10
+1.8V_S5 VCC SPI_SI 2 SOC_SPI_MISO_R R558 *short_0/J_4 SOC_SPI_MISO R506 *TPM@10K_4 BOARD_ID3 R495 10K_4 C503
SPI_SO SOC_SPI_CS#_R SOC_SPI_CS# BOARD_ID4 +3VPCU
GND 1 R554 *short_0/J_4 R537 *10K_4 R543 10K_4 D32 1u/6.3V_4
SPI_3P 3 CS# 6 SOC_SPI_CLK_R SOC_SPI_CLK BOARD_ID5
R561 3.3K/F_4 R560 *short_0/J_4 R535 *10K_4 R534 10K_4 30mils *SHORT_ PAD1
2
WP# SPI_SCK
BOARD_ID1 : UMA or DIS HIGH= UMA, LOW= DIS +3V_RTC_0 R520 1K/J_4 VCCRTC_1
Q
R557 3.3K/F_4 SPI_7P 7 4 R536 20K/J_4 SRT_CRST#
SPI_HOLD GND BOARD_ID2 : None BAT54C
20MIL
BOARD_ID3 : TPM HIGH=TPM, LOW=W/O TPM
1
SPI_FLASH R556 EC18@0/J_4 SOC_SPI_CLK_R1 [19] G9
1
soic8-7_9-1_27 GND R555 EC18@0/J_4 SOC_SPI_CS#_R1 [19] BOARD_ID4 : Reserve for UMA and GPU C504 C498
R559 EC18@0/J_4 SOC_SPI_MISO_R1 [19] BOARD_ID5 : Reserve for UMA and GPU CN17 1u/6.3V_4 1u/6.3V_4
AKE5EZN0N00 R564 EC18@0/J_4 BAT_CONN *SHORT_ PAD1
SOC_SPI_MOSI_R1 [19]
2
IC FLASH (8P) W25Q64FWSSIG (SOIC)
2
+1.8V_S5
A
20MIL 20MIL A
6/25 Change G9、G10 footprint from

R552 3.3K/F_4 SOC_SPI_CS# GND "SOLDERJUMPER-2" to "RC0603-C" for
SMT request

PROJECT : ZYL/ZYLA
Valley 5/9 (SPI/GPIO/CLK) 1A
www.vinafix.vn
5 4 3 2 1
5 4 3 2 1
l
7
+1.8V_S5 [6,9,12,21,37]
+1.8V [4,5,6,9,12,19,20,21,27,28,37]
U29F
+3V [4,5,9,11,12,13,17,19,20,22,24,25,26,27,28,35,37,39,40]
G2 M10
GPIO_S5_31 RESERVED_M10 M9
a
RESERVED_M9
M3 P7
L1 GPIO_S5_32 RESERVED_P7 P6
+1.8V_S5 GPIO_S5_33 RESERVED_P6
i
K2
K3 GPIO_S5_34
M2 GPIO_S5_35 M7
D R475 *10K_4 SOC_PWR_BUT N3 GPIO_S5_36 RESERVED_M7 M12 USB3_P0_REXT R477 1.24K/F_4 D
GPIO_S5_37 USB3_REXT0
t
P2
L3 GPIO_S5_38 P10
GPIO_S5_39 RESERVED_P10 P12
RESERVED_P12 GND
M4
J3 RESERVED_M4 M6
P3 GPIO_S5_40 RESERVED_M6
n
H3 GPIO_S5_41 D4
GPIO_S5_42 USB3_RXP0 USB30_RX1+ [25]
B12 E3
GPIO_S5_43 USB3_RXN0 USB30_RX1- [25]
Port 1 is debug port K6

USB3_TXP0 USB30_TX1+ [25]
[25] USBP0+ M16 K7
USB_DP0 USB3_TXN0 USB30_TX1- [25]
USB3.0 [25] USBP0- K16
e
USB_DN0
J14
[24] USB_H1_P USB_DP1
USB 2.0 HUB G14
[24] USB_H1_N USB_DN1
[28] USBP2+ K12
J12 USB_DP2
Bluetooth [28] USBP2- USB_DN2
d
[20] USBP3+ K10 H8
H10 USB_DP3 RESERVED_H8 H7
CAMERA [20] USBP3- USB_DN3 RESERVED_H7
i
R244 1K_4 ICLK_USB_TERMN_0 D10 H5
R245 1K_4 ICLK_USB_TERMN_1 F10 ICLK_USB_TERMN_D10 RESERVED_H5 H4
ICLK_USB_TERMN RESERVED_H4 +1.8V
f
[24] SOC_USB_OC0
GND R515 10K_4 C20
USB_OC_00
C
+1.8V_S5 R516 10K_4 B20
USB_OC_11 Top Swap (A16 Override) C
R120
[25] SOC_USB_OC1 0 = Top address bit is unchanged
*10K_4
1 = Top address bit is inverted
D6 BD12
R219 45.3/F_4 USB_RCOMP C7 USB_RCOMPO GPIO_S0_SC_55 BC12 GPIO_S0_SC_56
n
USB_RCOMPI GPIO_S0_SC_56 BD14 SOC_UART_TX
GPIO_S0_SC_57 BC14
GND R478 *0/J_4 USB_PLL_MON M13 GPIO_S0_SC_58 BF14 R113
USB_PLL_MON GPIO_S0_SC_59 BD16
GPIO_S0_SC_60 *10K_4
BC16 SOC_UART_RX
GND GPIO_S0_SC_61
B4 SOC_UART_TX R126 *0/J_4SOC_UART_RX
o
B5 USB_HSIC0_DATA BH12
USB_HSIC0_STROBE ILB_8254_SPKR SPKR [26]
GND
E2
D2 USB_HSIC1_DATA Un-Stuff for Test Only
USB_HSIC1_STROBE BH22 I2C_0_SDA_R R420 22/J_4
SIO_I2C0_DATA I2C_0_SCL_R I2C_0_SDA [21]
BG23 R421 22/J_4 Touch pad
USB_HSIC_RCOMP SIO_I2C0_CLK I2C_0_SCL [21]
GND R489 45.3/F_4 A7
USB_HSIC_RCOMP
C
R124 49.9/F_4 BG24 I2C_1_SDA
SIO_I2C1_DATA BH24 I2C_1_SCL
LPC_RCOMP BF18 SIO_I2C1_CLK
LAD0 BH16 LPC_RCOMP
[19,28] LAD0 ILB_LPC_AD_00
LAD1 BJ17 BG25 I2C_2_SDA_R
[19,28] LAD1 ILB_LPC_AD_11 SIO_I2C2_DATA
[19,28] LAD2 LAD2 BJ13 BJ25 I2C_2_SCL_R +1.8V
LAD3 BG14 ILB_LPC_AD_22 SIO_I2C2_CLK
[19,28] LAD3 ILB_LPC_AD_33
[19,28] LFRAME# LFRAME# BG17
B R428 22_4 SOC_CLKOUT_0 BG15 ILB_LPC_FRAME BG26 I2C_3_SDA I2C_0_SDA R403 560_4 B
[19] CLK_24M_KBC
a
R427 *22_4 SOC_CLKOUT_1 BH14 ILB_LPC_CLK_00 SIO_I2C3_DATA BH26 I2C_3_SCL I2C_0_SCL R404 560_4
[28] CLK_24M_DEBUG ILB_LPC_CLK_11 SIO_I2C3_CLK
R411 *22_4 R429 22_4 SOC_CLKRUN# BG16
[28] CLK_TPM [19,28] CLKRUN# ILB_LPC_CLKRUN
SOC_SERIRQ BG13 I2C_1_SDA R422 *560_4
[12,28] SOC_SERIRQ ILB_LPC_SERIRQ BF27 I2C_4_SDA I2C_1_SCL R405 *560_4
t
For TPM SIO_I2C4_DATA BG27 I2C_4_SCL
SIO_I2C4_CLK I2C_2_SDA_R R423 *560_4
I2C_2_SCL_R R399 *560_4
+1.8V BH28 I2C_5_SDA
R394 2.2K_4 SMB_SOC_DATA BG12 SIO_I2C5_DATA BG28 I2C_5_SCL I2C_3_SDA R395 *560_4
R410 2.2K_4 SMB_SOC_CLK BH10 PCU_SMB_DATA SIO_I2C5_CLK I2C_3_SCL R416 *560_4
SMB_SOC_ALERTB BG11 PCU_SMB_CLK
n
R426 2.2K_4
PCU_SMB_ALERT BJ29 I2C_6_SDA
SIO_I2C6_DATA BG29 I2C_6_SCL I2C_4_SDA R406 *560_4
SIO_I2C6_CLK I2C_4_SCL R396 *560_4
BH30 I2C_NFC_SOC_SDA I2C_5_SDA R417 *560_4

+1.8V GPIO_S0_SC_092 I2C_NFC_SOC_SCL T10 I2C_5_SCL
BG30
a
R400 *560_4
GPIO_S0_SC_093 T9
6 OF 13
Q46 I2C_6_SDA R397 *560_4
5 4.7K_4 R392 I2C_6_SCL R407 *560_4
+3V VLV_M_D/BGA
SMB_SOC_DATA 4 3 SMB_RUN_DAT REV = 1.15 I2C_NFC_SOC_SDA R424 *560_4
SMB_RUN_DAT [11,28]
I2C_NFC_SOC_SCL R425 *560_4
u
2 4.7K_4 R387 +3V
SMB_SOC_CLK 1 6 SMB_RUN_CLK
SMB_RUN_CLK [11,28] I2C pull up:
Standard/ Fast Mode --> 560 ohm
A
PJ4N3KDW Hight speed mode --> CLK- 560 ohm; A
DATA- 910 ohm
Q
PROJECT : ZYL/ZYLA
Valley 6/9 (USB/LPC/I2C) 1A

5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
al
+VCC_CORE R271 100/F_4
+VCC_GFX R143 100/F_4
i
GND R270 100/F_4
D +1.35VSUS D
U29G
t
VCC_SENSE P28 BD49
[35] VCC_SENSE VCC_AXG_SENSE CORE_VCC_SENSE_P28 DRAM_VDD_S4_BD49
BB8 BD52
[35] VCC_AXG_SENSE VSS_SENSE UNCORE_VNN_SENSE DRAM_VDD_S4_BD52
N28 BD53
[35] VSS_SENSE CORE_VSS_SENSE_N28 DRAM_VDD_S4_BD53
R269 *0/short_4 BF44 C175 C174 C261 C222 C234 C266
[35] VSS_AXG_SENSE DRAM_VDD_S4_BF44 BG51 2.2U/6.3V_6 2.2U/6.3V_6 2.2U/6.3V_6 2.2U/6.3V_6 1u/6.3V_4 0.1U/10V_4
DRAM_VDD_S4_BG51 BJ48
C432 4.7U/6.3V_6 +1.35VSUS AD38 DRAM_VDD_S4_BJ48 C51
n
C436 1u/6.3V_4 AF38 DRAM_VDD_S4_AD38 DRAM_VDD_S4_C51 D44
GND DRAM_VDD_S4_AF38 DRAM_VDD_S4_D44
C213 0.1U/10V_4 A48 F49 GND
AK38 DRAM_VDD_S4 DRAM_VDD_S4_F49 F52
AM38 DRAM_VDD_S4_AK38 DRAM_VDD_S4_F52 F53
AV41 DRAM_VDD_S4_AM38 DRAM_VDD_S4_F53 H46
+1.35VSUS DRAM_VDD_S4_AV41 DRAM_VDD_S4_H46
AV42 M41
e
BB46 DRAM_VDD_S4_AV42 DRAM_VDD_S4_M41 M42
DRAM_VDD_S4_BB46 DRAM_VDD_S4_M42 V38
+VCC_CORE DRAM_VDD_S4_V38 Y38
DRAM_VDD_S4_Y38
AA27
AA29 CORE_VCC_S0IX_AA27 +VCC_GFX
AA30 CORE_VCC_S0IX_AA29
d
AC27 CORE_VCC_S0IX_AA30
AC29 CORE_VCC_S0IX_AC27 AA24
C221 10U/6.3V_6 AC30 CORE_VCC_S0IX_AC29 UNCORE_VNN_S3_AA24 AC22
CORE_VCC_S0IX_AC30 UNCORE_VNN_S3_AC22
i
C207 4.7U/6.3V_6 AD27 AC24
C235 4.7U/6.3V_6 AD29 CORE_VCC_S0IX_AD27 UNCORE_VNN_S3_AC24 AD22 C470 C471 C189 C220 C199 C196 C195 C192 C197
C255 2.2U/6.3V_6 AD30 CORE_VCC_S0IX_AD29 UNCORE_VNN_S3_AD22 AD24 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
C C
C489 2.2U/6.3V_6 AF27 CORE_VCC_S0IX_AD30 UNCORE_VNN_S3_AD24 AF22
C488 22U/6.3V_6 AF29 CORE_VCC_S0IX_AF27 UNCORE_VNN_S3_AF22 AF24
f
C487 22U/6.3V_6 AG27 CORE_VCC_S0IX_AF29 UNCORE_VNN_S3_AF24 AG22
C486 22U/6.3V_6 AG29 CORE_VCC_S0IX_AG27 UNCORE_VNN_S3_AG22 AG24 GND
CORE_VCC_S0IX_AG29 UNCORE_VNN_S3_AG24
AG30
CORE_VCC_S0IX_AG30 UNCORE_VNN_S3_AJ22
AJ22 Near CPU
P26 AJ24
CORE_VCC_S0IX_P26 UNCORE_VNN_S3_AJ24
Near CPU GND P27
CORE_VCC_S0IX_P27 UNCORE_VNN_S3_AK22
AK22
U27 AK24
U29 CORE_VCC_S0IX_U27 UNCORE_VNN_S3_AK24 AK25 C273
n
V27 CORE_VCC_S0IX_U29 UNCORE_VNN_S3_AK25 AK27 C473 C474 C475 C472 +
C283 V29 CORE_VCC_S0IX_V27 UNCORE_VNN_S3_AK27 AK29
+ C499 C500 C501 C502 V30 CORE_VCC_S0IX_V29 UNCORE_VNN_S3_AK29 AK30 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 *330u/2V_7343
Y27 CORE_VCC_S0IX_V30 UNCORE_VNN_S3_AK30 AK32
*330u/2V_7343 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 22U/6.3V_6 Y29 CORE_VCC_S0IX_Y27 UNCORE_VNN_S3_AK32 AM22
Y30 CORE_VCC_S0IX_Y29 UNCORE_VNN_S3_AM22
CORE_VCC_S0IX_Y30
o
SOC_CORE_PINAF30 AF30 AA22 SOC_CORE_PIN_AA22
TP43 TP_CORE_V1P05_S4 TP2_CORE_VCC_S0IX TP46
7 OF 13
VLV_M_D/BGA
REV = 1.15
C
B B
+VCC_CORE [29,35]
+VCC_GFX [9,29,35]
+1.35VSUS [2,11,36,37]
+3VPCU [6,19,21,22,25,26,30,31,32,37,39,40] IO Thrm Protect
+3VPCU
ta
R142
*10K_4
default 25 degree for detect temperature
n
THRM_MOINTOR [19]
2
a
R152 C159
*0/J_4 *0.1U/10V_4
1
A THER_CPU A
R488
u
*10K_6_NTC

PROJECT : ZYL/ZYLA
Valley 7/9 (Power 1) 1A
Q
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
l
For layout move
a
GND C246 1u/6.3V_4 U29H C190 1u/6.3V_4 GND
1u/6.3V_4 C200 GND C434 1u/6.3V_4 C218 1u/6.3V_4
+1.0V V32 AD36
SVID_V1P0_S3_V32 DRAM_V1P35_S0IX_F1_AD36 +1.35V
BJ6 AM32
i
D VIS_V1P0_SIOX_PW VGA_V1P0_S3_BJ6 HDA_LPE_V1P5V1P8_S3_AM32 UNCORE_V1P8_AN32_PWR +1.5V D
+1.0V R176 *0/short_4 AD35 AM30 R150 *0/short_4 +1.8V
C225 1u/6.3V_4 AF35 DRAM_V1P0_S0IX_AD35 UNCORE_V1P8_S3_AM30 AN32 C138 1u/6.3V_4 C239 1uF/6.3_4
GND DRAM_V1P0_S0IX_AF35 UNCORE_V1P8_S3_AN32 LPC_V3P3_PWR GND
AF36 AM27 R79 *0/short_4 +3V C186 1u/6.3V_4
DRAM_V1P0_S0IX_AF36 LPC_V1P8V3P3_S3_AM27 GND
t
AA36 U24 V1P8_S5_PWR C187 1u/6.3V_4
AJ36 DRAM_V1P0_S0IX_AA36 UNCORE_V1P8_G3_U24 N18 C492 1uF/6.3_4 C252 1uF/6.3_4
DRAM_V1P0_S0IX_AJ36 USB_V3P3_G3_N18 PCU_V3P3_G3_PWR GND
C204 1u/6.3V_4 AK35 P18 C247 0.1U/10V_4 C256 1uF/6.3_4
GND DRAM_V1P0_S0IX_AK35 USB_V3P3_G3_P18 UNCORE_V1P8_AN32_PWR
C210 1u/6.3V_4 AK36 U38 C242 1uF/6.3_4
DRAM_V1P0_S0IX_AK36 UNCORE_V1P8_S3_U38 VGA_V3P3_PWR GND
+1.0V Y35 AN24 R77 *0/short_4 C254 0.01U/25V_4
DRAM_V1P0_S0IX_Y35 VGA_V3P3_S3_AN24 V1P8_S5_PWR +3V
Y36 V25 C136 1u/6.3V_4
DRAM_V1P0_S0IX_Y36 PCU_V1P8_G3_V25 GND
VIS_V1P0_SIOX_PW AK19 N22 PCU_V3P3_G3_PWR
n
+1.0V R181 *0/short_4 R528 *0/short_4 +3V_S5
C198 1u/6.3V_4 AK21 DDI_V1P0_S0IX_AK19 PCU_V3P3_G3_N22 AN27 +VSDIO R78 *0/short_4
DDI_V1P0_S0IX_AK21 SD3_V1P8V3P3_S3_AN27 +3V
C202 1u/6.3V_4 AJ18 AD16 C462 *1U/6.3V_4 C137 1u/6.3V_4
GND DDI_V1P0_S0IX_AJ18 VSS_AD16 VSS_AD18_AD16_PWR GND
C240 1u/6.3V_4 AM16 AD18 R466 *0/short_4
USB3_V1P0_G3 DDI_V1P0_S0IX_AM16 VSS_AD18 USB_HSIC_V1P2_G3 GND
C226 1u/6.3V_4 U22 V18 R472 *0/short_4
GND UNCORE_V1P0_G3_U22 USB_HSIC_V1P2_G3_V18 +1.0V_S5
C231 0.01U/25V_4 V22 AA18 V1P8_AA18_PEW R469 *0/short_4 +1.8V_S5
e
C179 22U/6.3V_6 VIS_V1P0_SIOX_PW AN29 UNCORE_V1P0_G3_V22 UNCORE_V1P8_G3_AA18 P22 RTC_VCC_P22_PWR R215 *0/short_4 C465 1u/6.3V_4
GND VIS_V1P0_S0IX_AN29 RTC_VCC_P22 +3V_RTC GND
AN30 N20 C248 1uF/6.3_4
VIS_V1P0_S0IX_AN30 USB_V1P8_G3_N20 V1P8_S5_PWR GND
+1.0V AF16 U25 R261 *0/short_4
UNCORE_V1P0_S3_AF16 PMU_V1P8_G3_U25 +1.8V_S5
C215 1u/6.3V_4 AF18 AF33
C229 0.1U/10V_4 USB3_V1P0_G3 C237 1u/6.3V_4 Y18 UNCORE_V1P0_S3_AF18 CORE_V1P05_S3_AF33 AG33
+VCC_GFX GND UNCORE_V1P0_S3_Y18 CORE_V1P05_S3_AG33
C216 0.01U/25V_4 G1 AG35
UNCORE_V1P0_S3_G1 CORE_V1P05_S3_AG35
d
+1.0V AM21 U33
C185 1u/6.3V_4 AN21 PCIE_V1P0_S3_AM21 CORE_V1P05_S3_U33 U35 CORE_V1P05_S3_PW R209 *0/short_6
PCIE_V1P0_S3_AN21 CORE_V1P05_S3_U35 +1.05V
C181 1u/6.3V_4 V33
C GND CORE_V1P05_S3_V33 C
C177 0.01U/25V_4 AN18 A3
i
AN19 PCIE_GBE_SATA_V1P0_S3_AN18 VSS_A3_A3 A49
CORE_V1P05_S3_PW AA33 SATA_V1P0_S3_AN19 VSS_A49_A49 A5 C217 C232 C251 C257
R188 *0/short_4 VIS_V1P0_SIOX_PW AF21 CORE_V1P05_S3_AA33 VSS_A5_A5 A51 0.47uF/6.3V_4 1uF/6.3_4 1uF/6.3_4 0.01U/25V_4
+1.0V UNCORE_V1P0_S0IX_AF21 VSS_A51_A51
AG21 A52
UNCORE_V1P0_S0IX_AG21 VSS_A52_A52
f
C163 22U/6.3V_6 V24 A6
C165 22U/6.3V_6 Y22 VIS_V1P0_S0IX_V24 VSS_A6_A6 B2
C169 22U/6.3V_6 Y24 VIS_V1P0_S0IX_Y22 VSS_B2_B2 B52
C203 1u/6.3V_4 M14 VIS_V1P0_S0IX_Y24 VSS_B52_B52 B53
GND +1.0V USB_V1P0_S3_M14 VSS_B53_B53
C243 1u/6.3V_4 C193 1u/6.3V_4 U18 BE1
C214 1uF/6.3_4 U19 USB_V1P0_S3_U18 VSS_BE1_BE1 BE53
GND USB_V1P0_S3_U19 VSS_BE53_BE53
C238 1u/6.3V_4 AN25 BG1
n
R216 *0/short_4 USB3_V1P0_G3 Y19 GPIO_V1P0_S3_AN25 VSS_BG1_BG1 BG53 GND
+1.0V_S5 USB3_V1P0_G3_Y19 VSS_BG53_BG53
C277 1uF/6.3_4 C3 BH1
GND USB3_V1P0_G3_C3 VSS_BH1_BH1
C276 1uF/6.3_4 C5 BH2
B6 UNCORE_V1P0_G3_C5 VSS_BH2_BH2 BH52
R272 *0/short_4 CORE_V1P05 AC32 UNCORE_V1P0_G3_B6 VSS_BH52_BH52 BH53
+1.05V CORE_V1P0_S3_AC32 VSS_BH53_BH53
Y32 BJ2
o
U36 CORE_V1P0_S3_Y32 VSS_BJ2_BJ2 BJ3
+1.35V UNCORE_V1P35_S0IX_F4_U36 VSS_BJ3_BJ3
C228 1u/6.3V_4 AA25 BJ5
C245 1u/6.3V_4 AG32 UNCORE_V1P35_S0IX_F5_AA25 VSS_BJ5_BJ5 BJ49
GND UNCORE_V1P35_S0IX_F2_AG32 VSS_BJ49_BJ49
V36 BJ51
20140421: BD1 UNCORE_V1P35_S0IX_F3_V36 VSS_BJ51_BJ51 BJ52
Delete L14 +1.35V VGA_V1P35_S3_F1_BD1 VSS_BJ52_BJ52
B AF19 C1 B
C440 *22uF/6.3V_6 AG19 UNCORE_V1P35_S0IX_F6 VSS_C1_C1 C53
GND
C441 1u/6.3V_4
+1.35V C209 1u/6.3V_4 AJ19 UNCORE_V1P35_S0IX_F1_AG19 VSS_C53_C53 E1
ICLK_V1P35_S3_F1_AJ19 VSS_E1_E1
C
C442 1u/6.3V_4 E53
GND VSS_E53_E53 F1
AG18 RESERVED_F1 AK18
AN16 ICLK_V1P35_S3_F2 PCIE_V1P0_S3_AK18 AM18
+1.0V
U16 VSSA_AN16 8 OF 13 PCIE_V1P0_S3_AM18 C183 1u/6.3V_4
USB_VSSA_U16 C170 1u/6.3V_4
+1.35V VLV_M_D/BGA C188 1u/6.3V_4
GND
C206 C211 REV = 1.15
a
1u/6.3V_4 1u/6.3V_4
GND
t
GND
+1.0V [6,35,37]
+VCC_GFX [8,29,35]
+1.0V 20140418: +1.0V_S5 [33,37]
Add CAPs for +1.0V +1.05V [5,34]
+1.35V [37]
n
+1.5V [22,23,26,34]
+1.8V [4,5,6,7,12,19,20,21,27,28,37]
A A
+3V [4,5,7,11,12,13,17,19,20,22,24,25,26,27,28,35,37,39,40]
C151 C145 C144 C152
+3V_RTC [6]
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 0.01U/25V_4 +1.8V_S5 [6,7,12,21,37]
a
GND
Near CPU Side
PROJECT : ZYL/ZYLA
Valley 8/9 (Power 2) 1A
u
5 4 3 2 1
Q www.vinafix.vn
5 4 3 2 1
l
10
ia
D D
t
U29I U29J U29K U29L U29M
A11 AC36 AG38 AH47 AT24 AY36 BF30 E8 K9 U3

A15 VSS1 VSS36 AC38 AH4 VSS71 VSS106 AH48 AT27 VSS141 VSS176 AY4 BF36 VSS211 VSS246 F19 L13 VSS281 VSS316 U30
A19 VSS2 VSS37 AD19 AH41 VSS72 VSS107 AH50 AT30 VSS142 VSS177 AY50 BF4 VSS212 VSS247 F2 L19 VSS282 VSS317 U32
n
A23 VSS3 VSS38 AD21 AH45 VSS73 VSS108 AH51 AT35 VSS143 VSS178 AY9 BG31 VSS213 VSS248 F24 L27 VSS283 VSS318 U40
A27 VSS4 VSS39 AD25 AH7 VSS74 VSS109 AH6 AT38 VSS144 VSS179 BA14 BG34 VSS214 VSS249 F27 L35 VSS284 VSS319 U42
A31 VSS5 VSS40 AD32 AH9 VSS75 VSS110 AM44 AT4 VSS145 VSS180 BA19 BG39 VSS215 VSS250 F30 M19 VSS285 VSS320 U43
A35 VSS6 VSS41 AD33 AJ1 VSS76 VSS111 AM51 AT47 VSS146 VSS181 BA22 BG42 VSS216 VSS251 F35 M26 VSS286 VSS321 U45
A39 VSS7 VSS42 AD47 AJ16 VSS77 VSS112 AM7 AT52 VSS147 VSS182 BA27 BG45 VSS217 VSS252 F5 M27 VSS287 VSS322 U46
A43 VSS8 VSS43 AD7 AJ21 VSS78 VSS113 AN1 AU1 VSS148 VSS183 BA32 BG49 VSS218 VSS253 F7 M34 VSS288 VSS323 U48
e
A47 VSS9 VSS44 AE1 AJ25 VSS79 VSS114 AN11 AU24 VSS149 VSS184 BA35 BJ11 VSS219 VSS254 G10 M35 VSS289 VSS324 U49
AA1 VSS10 VSS45 AE11 AJ27 VSS80 VSS115 AN12 AU3 VSS150 VSS185 BA40 BJ15 VSS220 VSS255 G20 M38 VSS290 VSS325 U5
AA16 VSS11 VSS46 AE12 AJ29 VSS81 VSS116 AN14 AU30 VSS151 VSS186 BA53 BJ19 VSS221 VSS256 G22 M47 VSS291 VSS326 U51
AA19 VSS12 VSS47 AE14 AJ3 VSS82 VSS117 AN22 AU38 VSS152 VSS187 BB19 BJ23 VSS222 VSS257 G26 M51 VSS292 VSS327 U53
AA21 VSS13 VSS48 AE3 AJ30 VSS83 VSS118 AN3 AU51 VSS153 VSS188 BB27 BJ27 VSS223 VSS258 G28 N1 VSS293 VSS328 U6
AA3 VSS14 VSS49 AE4 AJ32 VSS84 VSS119 AN33 AV12 VSS154 VSS189 BB35 BJ31 VSS224 VSS259 G32 N16 VSS294 VSS329 U8
AA32 VSS15 VSS50 AE40 AJ33 VSS85 VSS120 AN35 AV13 VSS155 VSS190 BC20 BJ35 VSS225 VSS260 G34 N38 VSS295 VSS330 U9
d
AA35 VSS16 VSS51 AE42 AJ35 VSS86 VSS121 AN36 AV14 VSS156 VSS191 BC22 BJ39 VSS226 VSS261 G42 N51 VSS296 VSS331 V12
AA38 VSS17 VSS52 AE43 AJ38 VSS87 VSS122 AN38 AV18 VSS157 VSS192 BC26 BJ43 VSS227 VSS262 H19 P13 VSS297 VSS332 V16
AA53 VSS18 VSS53 AE45 AJ53 VSS88 VSS123 AN40 AV19 VSS158 VSS193 BC28 BJ47 VSS228 VSS263 H27 P16 VSS298 VSS333 V19
VSS19 VSS54 VSS89 VSS124 VSS159 VSS194 VSS229 VSS264 VSS299 VSS334
i
AB10 AE46 AK10 AN42 AV24 BC32 BJ7 H35 P19 V21
AB4 VSS20 VSS55 AE48 AK14 VSS90 VSS125 AN43 AV27 VSS160 VSS195 BC34 C14 VSS230 VSS265 J1 P20 VSS300 VSS335 V35
AB41 VSS21 VSS56 AE50 AK16 VSS91 VSS126 AN45 AV30 VSS161 VSS196 BC42 C31 VSS231 VSS266 J16 P24 VSS301 VSS336 V40
AB45 VSS22 VSS57 AE51 AK33 VSS92 VSS127 AN46 AV35 VSS162 VSS197 BD19 C34 VSS232 VSS267 J19 P32 VSS302 VSS337 V44
f
C AB50 VSS25 VSS60 AE8 AM12 VSS95 VSS130 AN5 AV51 VSS165 VSS200 BD30 C45 VSS235 VSS270 J32 P4 VSS305 VSS340 Y10 C
AB51 VSS26 VSS61 AE9 AM19 VSS96 VSS131 AN51 AV7 VSS166 VSS201 BD35 C49 VSS236 VSS271 J35 P47 VSS306 VSS341 Y14
AB6 VSS27 VSS62 AF10 AM24 VSS97 VSS132 AN53 AW13 VSS167 VSS202 BE19 D12 VSS237 VSS272 J40 P52 VSS307 VSS342 Y16
AC16 VSS28 VSS63 AF12 AM25 VSS98 VSS133 AN6 AW19 VSS168 VSS203 BE2 D16 VSS238 VSS273 J53 P9 VSS308 VSS343 Y21
AC18 VSS29 VSS64 AF25 AM29 VSS99 VSS134 AN8 AW27 VSS169 VSS204 BE35 D24 VSS239 VSS274 K14 T40 VSS309 VSS344 Y25
AC19 VSS30 VSS65 AF32 AM33 VSS100 VSS135 AN9 AW3 VSS170 VSS205 BE8 D30 VSS240 VSS275 K22 U1 VSS310 VSS345 Y33
n
AC21 VSS31 VSS66 AF47 AM35 VSS101 VSS136 AP40 AW35 VSS171 VSS206 BF12 D36 VSS241 VSS276 K32 U11 VSS311 VSS346 Y41
AC25 VSS32 VSS67 AG16 AM36 VSS102 VSS137 AT12 AY10 VSS172 VSS207 BF16 D38 VSS242 VSS277 K36 U12 VSS312 VSS347 Y44
AC33 VSS33 VSS68 AG25 AM40 VSS103 VSS138 AT16 AY22 VSS173 VSS208 BF24 E19 VSS243 VSS278 K4 U14 VSS313 VSS348 Y7
AC35 VSS34 VSS69 AG36 M28 VSS104 VSS139 AT19 AY32 VSS174 VSS209 BF38 E35 VSS244 VSS279 K50 U21 VSS314 VSS349 Y9
VSS35 9 OF 13 VSS70 VSS105 10 OF 13 VSS140 VSS175 11 OF 13 VSS210 VSS245 12 OF 13 VSS280 VSS315 13 OF 13 VSS350
VLV_M_D/BGA VLV_M_D/BGA VLV_M_D/BGA VLV_M_D/BGA VLV_M_D/BGA
o
REV = 1.15 REV = 1.15 REV = 1.15 REV = 1.15 REV = 1.15
GND GND GND GND GND GND GND GND GND GND
a C B
n t
A
ua A
Q
PROJECT : ZYL/ZYLA
Valley 9/9 (GND) 1A

5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
Address A0H
11
l
[2] M_A_A[15:0] M_A_DQ[63:0] [2]
JDIM9A +1.35VSUS
M_A_A0 98 5 M_A_DQ5 2.48A JDIM9B
M_A_A1 97 A0 DQ0 7 M_A_DQ4 75 44
M_A_A2 96 A1 DQ1 15 M_A_DQ6 76 VDD1 VSS16 48
a
i
A9 DQ9 33 VDD9 VSS24
t
D M_A_A10 107 M_A_DQ15 100 71 D
M_A_A11 84 A10/AP DQ10 35 M_A_DQ14 105 VDD10 VSS25 72
PC2100 DDR3 SDRAM SO-DIMM

M_A_A13 119 A12/BC# DQ12 24 M_A_DQ8 111 VDD12 VSS27 128
+1.35VSUS [2,8,36,37] M_A_A14 A13 DQ13 34 M_A_DQ10 VDD13 VSS28
80 112 133
+VDDQ_VTT [36] M_A_A15 78 A14 DQ14 36 M_A_DQ11 117 VDD14 VSS29 134
+3V [4,5,7,9,12,13,17,19,20,22,24,25,26,27,28,35,37,39,40] A15 DQ15 39 M_A_DQ25 118 VDD15 VSS30 138
n
PC2100 DDR3 SDRAM SO-DIMM
109 DQ16 41 M_A_DQ24 123 VDD16 VSS31 139
[2] M_A_BS#0 BA0 DQ17 51 VDD17 VSS32
108 M_A_DQ30 124 144
[2] M_A_BS#1 BA1 DQ18 53 M_A_DQ31 VDD18 VSS33
79 145
[2] M_A_BS#2 BA2 DQ19 40 M_A_DQ29 VSS34
114 199 150
[2] M_A_CS#0 S0# DQ20 42 +3V VDDSPD VSS35
121 M_A_DQ28 151
[2] M_A_CS#1
e
101 S1# DQ21 50 M_A_DQ27 77 VSS36 155
[2] M_A_CLK0 CK0 DQ22 52 NC1 VSS37
103 M_A_DQ26 122 156
[2] M_A_CLK0# CK0# DQ23 57 M_A_DQ21 NC2 VSS38
102 R122 10K/F_4 125 161
[2] M_A_CLK1 CK1 DQ24 59 M_A_DQ20 +3V NCTEST VSS39
104 162
[2] M_A_CLK1# CK1# DQ25 67 VSS40
73 M_A_DQ18 PM_EXTTS#0 198 167
[2] M_A_CKE0 CKE0 DQ26 69 M_A_DQ23 TP16 EVENT# VSS41
74 30 168
[2] M_A_CKE1 CKE1 DQ27 56 M_A_DQ17 [2] M_A_DRAMRST# RESET# VSS42
d
115 172
[2] M_A_CAS# CAS# DQ28 58 M_A_DQ16 VSS43
110 C289 *0.1U/10V_4 173
[2] M_A_RAS# RAS# DQ29 68 M_A_DQ22 +SMDDR_VREF_DQ VSS44
113 1 178
[2] M_A_WE# DIMM0_SA0 W E# DQ30 70 M_A_DQ19 +SMDDR_VREF_DIMM VREF_DQ VSS45
R115 10K/F_4 197 126 179
i
R114 10K/F_4 DIMM0_SA1 201 SA0 DQ31 129 M_A_DQ33 VREF_CA VSS46 184
202 SA1 DQ32 131 M_A_DQ32 VSS47 185
[7,28] SMB_RUN_CLK SCL DQ33 141 M_A_DQ39 VSS48
200 2 189
[7,28] SMB_RUN_DAT SDA DQ34 143 M_A_DQ38 3 VSS1 VSS49 190
DQ35 130 VSS2 VSS50
f
116 M_A_DQ36 8 195
[2] M_A_ODT0
(204P)
120 ODT0 DQ36 132 M_A_DQ37 9 VSS3 VSS51 196
[2] M_A_ODT1 ODT1 DQ37 140 VSS4 VSS52
M_A_DQ35 13
11 DQ38 142 M_A_DQ34 14 VSS5
C [2] M_A_DM0 28 DM0 DQ39 147 M_A_DQ61 19 VSS6 C
[2] M_A_DM1 DM1 DQ40 149 M_A_DQ60 VSS7
46 20
(204P)
[2] M_A_DM3 63 DM2 DQ41 157 M_A_DQ59 25 VSS8
n
[2] M_A_DM2 DM3 DQ42 159 M_A_DQ58 VSS9
136 26 203
[2] M_A_DM4 DM4 DQ43 146 M_A_DQ56 VSS10 VTT1 +VDDQ_VTT
153 31 204
[2] M_A_DM7 170 DM5 DQ44 148 M_A_DQ57 32 VSS11 VTT2
[2] M_A_DM5 187 DM6 DQ45 158 M_A_DQ62 37 VSS12 205
[2] M_A_DM6 DM7 DQ46 160 M_A_DQ63 38 VSS13 GND 206
M_A_DQS0 12 DQ47 163 M_A_DQ45 43 VSS14 GND
o
M_A_DQS1 29 DQS0 DQ48 165 M_A_DQ44 VSS15
M_A_DQS3 47 DQS1 DQ49 175 M_A_DQ46
M_A_DQS2 64 DQS2 DQ50 177 M_A_DQ43 DDR3-DIMM0_H=5.2_STD
M_A_DQS4 137 DQS3 DQ51 164 M_A_DQ40 ddr-ddrsk-20401-tp4b-204p-smt
M_A_DQS7 154 DQS4 DQ52 166 M_A_DQ41 DGMK4000433
M_A_DQS5 171 DQS5 DQ53 174 M_A_DQ42 IC SOCKET DDR3 STD SO-DIMM(204P,H5.2)
M_A_DQS6 188 DQS6 DQ54 176 M_A_DQ47
[2] M_A_DQS[7:0] DQS7 DQ55 181 Other one: DGMK4000109
M_A_DQS#0 10 M_A_DQ52
M_A_DQS#1 DQS#0 DQ56 183 M_A_DQ53
C
27
M_A_DQS#3 45 DQS#1 DQ57 191 M_A_DQ54
M_A_DQS#2 62 DQS#2 DQ58 193 M_A_DQ50
M_A_DQS#4 135 DQS#3 DQ59 180 M_A_DQ49
M_A_DQS#7 152 DQS#4 DQ60 182 M_A_DQ48
M_A_DQS#5 169 DQS#5 DQ61 192 M_A_DQ51
M_A_DQS#6 186 DQS#6 DQ62 194 M_A_DQ55
[2] M_A_DQS#[7:0] DQS#7 DQ63
EZIW
a
DDR3-DIMM0_H=5.2_STD
ddr-ddrsk-20401-tp4b-204p-smt
DGMK4000433
IC SOCKET DDR3 STD SO-DIMM(204P,H5.2)
t
B B
Other one: DGMK4000109
+1.35VSUS
Place these Caps near So-Dimm0.
n
For EMI RESERVE 0.1uF/10uF 4pcs on each side of connector VREF DQ0 M1 Solution
+1.35VSUS +1.35VSUS +VDDQ_VTT
R295
+1.35VSUS C223 0.1U/10V_4 C149 1u/6.3V_4 4.7K/F_4
+1.35VSUS
a
C227 C233 0.1U/10V_4 C150 1u/6.3V_4 +VDDQ R294 *0_6 +SMDDR_VREF_DQ
EC14 *120P/50V_4 EC13 *120P/50V_4 + [36] +VDDQ
C244 0.1U/10V_4 C147 1u/6.3V_4
EC12 *120P/50V_4 EC22 *120P/50V_4 *330u/2V_7343
C253 0.1U/10V_4 C148 1u/6.3V_4 R296
EC11 *120P/50V_4 EC17 *120P/50V_4 4.7K/F_4
u
C260 0.1U/10V_4 C146 10U/6.3V_6
EC15 *120P/50V_4 EC20 *0.1U/10V_4
Near SO-DIMM C265 0.1U/10V_4
EC18 *120P/50V_4 EC21 *0.1U/10V_4
C268 0.1U/10V_4 +1.35VSUS
EC16 *120P/50V_4 EC23 *0.1U/10V_4 +SMDDR_VREF_DIMM
C269 0.1U/10V_4
EC19 *120P/50V_4 EC24 *0.1U/10V_4 C208 0.1U/10V_4
Q
C219 10U/6.3V_6 C201 *2.2U/6.3V_6 R179
4.7K/F_4
+VDDQ_VTT C230 10U/6.3V_6
A +SMDDR_VREF_DQ +VDDQ R170 *0_6 +SMDDR_VREF_DIMM A
EC9 *120P/50V_4 C241 10U/6.3V_6
C313 0.1U/10V_4
EC10 *120P/50V_4 C250 10U/6.3V_6
C314 *2.2U/6.3V_6 R168
C259 10U/6.3V_6 4.7K/F_4
C264 10U/6.3V_6 +3V Quanta Computer Inc.

C267 10U/6.3V_6 C153 0.1U/10V_4
PROJECT : ZYL/ZYLA
C272 10U/6.3V_6 C154 0.1U/10V_4 Size Document Number Rev
Follow CHK list

DDR3 DIMM0-STD(5.2H) 1A

5 4 3 2 1
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5 4 3 2 1
l
12
EC_PWROK 0_4 R199
[2,19] EC_PWROK
R230 0_4
+1.8V *0/J_4 R212
[19] DPWROK_EC CORE_PWROK [6]
+1.8V_S5 +3V_S5
a
R206
R249
10K_4 U16 100K/F_4
i
1 6
VCCA VCCB
D 3 4 GND D
[7,28] SOC_SERIRQ A B SERIRQ [19]
t
2 5 R220 +1.8V_S5
GND OE *10K_4
0_4 R200
[19] RSMRST# SOC_RSMRST# [6]
GND *G2129TL1U
n
R207
use 985LB1, SERIRQ just bypass. 100K/F_4
e
GND
+1.8V [4,5,6,7,9,19,20,21,27,28,37]
+3V_S5 [2,9,19,21,24,27,28,34,35,37,39,40]
+3V [4,5,7,9,11,13,17,19,20,22,24,25,26,27,28,35,37,39,40]
+1.8V_S5 [6,7,9,21,37]
+1.8VPCU [19,32,37]
+1.8V_S5 +3V_S5
d
R223 *10K_4
Reserve For EC GPIO input.
+3V_S5
*0_4 R227 R236 *10K_4 GND
2
i
PJ4N3KDW
1 3 Q31A R250
[6] PCH_SLP_S0# PCH_SLP_S0_N [19]
PJ4N3KDW 10K_4
Q29A
f
4 3
C Q33 [6] SLP_S3# SUSB# [19] C
*PJA138K R218 *0/J_4 4 3
[6] SLP_S0IX# SLP_SUS#_EC [19]
5
R258 10K_4 +1.8V_S5 R253 *10K_4
[19] DNBSWON#
+1.8V_S5 +1.8VPCU
5
U17 SOC_PWRBTN# R222 *10K_4
n
SOC_PWRBTN# [6]
1 6 +1.8V_S5
A1 Y1
2
GND 2 5 +1.8V_S5
3 GND VCC 4
A2 Y2
2
SOC_KBC_SCI [5] 1 6
[2,6] SLP_S4# SUSC# [19]
74LVC2G07GW
R256 10K_4 1 6
[19] SIO_EXT_SCI# +1.8V [6] SOC_PLTRST# PLTRST# [13,19,24,25,27,28]
o
Q31B
PJ4N3KDW R217 10K_4
Q29B +3V
*0_4 R235 R226 *10K_4 PJ4N3KDW
GND
+3V_S5 R240
10K_4 Reserve For EC GPIO input.
U15 SOC_PMC_WAKE
[19,27,28] WAKE_SRC_1 SOC_PMC_WAKE [6]
1 6
C
2 A1 Y1 5
GND GND VCC +3V_S5
3 4
A2 Y2
[19] SIO_EXT_SMI# SOC_KCB_SMI [6]
74LVC2G07GW
R238 *10K_4 +1.8V_S5
B B
ta
+3V +1.8V
+1.8V *10K_4 R251 R224 *10K_4 +3V

2
2
n
[17] DGPU_PWROK 1 3 DGPU_PWROK_Q [5] [5] DGPU_PWR_EN_Q 1 3 DGPU_PWR_EN [40]
*2N7002K
Q30
a
Q32
*PJA138K
0_4
R221
Check Q51 / Q52 Gate Power to +3V Power rail. 0_4
R231
Check which GPIO(+1.8V_S0) +1.8V
u
R385 *10K_4 +3V
2
[5] DGPU_HOLD_RST#_Q 1 3 DGPU_HOLD_RST# [13]

A A
Q41
Q
*PJA138K
0_4
R384
PROJECT : ZYL/ZYLA
Level Shfiter 1A

5 4 3 2 1
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5 4 3 2 1
13
<VGA> +3V_GFX +3V_GFX
l
+VGPU_CORE PLACE UNDER GPU BALLS
U25A R55 Follow Z09 to isolate CLK_REQ# U25E
+1.05V_GFX
1000mA EV@10K/F_4 11/14 NVVDD
2
1/14 PCI_EXPRESS K10
VDD
K12
a
VDD
PEX_WAKE AB6 PEX_CLKREQ# 1 3 VDD K14
CLK_PEGA_REQ# [5]
To be placed no further from the GPUC125 EV@22u/6.3V_8 VDD K16 C65 C375 C374 C82 C379 C373 C55 C56
than bewteen BGA and Power supply C123 EV@22u/6.3V_8 AA22 PEX_IOVDD Q15 PU at page 9 VDD K18
C102 EV@10u/6.3V_6 AB23 AC7 PEGX_RST# EV@2N7002K L11
i
PEX_IOVDD PEX_RST VDD
C94 EV@10u/6.3V_6 AC24 PEX_IOVDD VDD L13 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6
place near balls C105 EV@4.7u/6.3V_6 AD25 PEX_IOVDD PEX_CLKREQ AC6 PEX_CLKREQ# R52 *EV@0_4 VDD L15 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6 EV@4.7u/6.3V_6
D C92 EV@1u/6.3V_4 AE26 PEX_IOVDD VDD L17 D
place under BGA C109 EV@1u/6.3V_4 AE27 AE8 M10
t
PEX_IOVDD PEX_REFCLK CLK_PCIE_VGAP [6] VDD
PEX_REFCLK AD8 CLK_PCIE_VGAN [6] VDD M12
VDD M14
PEX_TX0 AC9 C_PEG_RX0 C120 EV@0.22u/10V_4 VDD M16
C_PEG_RX#0 C119 PEG_RX0 [5]
PEX_TX0 AB9 EV@0.22u/10V_4 VDD M18 4.7uF x 15 population x10
PEG_RX#0 [5]
PLACE CLOSE TO BGA VDD N11
AG6 PEG_TX0 +3V_GFX J8/K8 N13
PEX_RX0 PEG_TX0 [5] VDD
AA10 PEX_IOVDDQ PEX_RX0 AG7 PEG_TX#0 VDD N15
+1.05V_GFX PEG_TX#0 [5]
n
C131 EV@22u/6.3V_8 AA12 PEX_IOVDDQ C39 EV@4.7u/6.3V_6 VDD N17 C49 C50 C378 C80 C67 C64 C68
To be placed no further from the GPUC130 EV@22u/6.3V_8 AA13 PEX_IOVDDQ PEX_TX1 AB10 C_PEG_RX1 C117 EV@0.22u/10V_4 VDD P10
C_PEG_RX#1 C118 PEG_RX1 [5]
than bewteen BGA and Power supply C93 EV@10u/6.3V_6 AA16 PEX_IOVDDQ PEX_TX1 AC10 EV@0.22u/10V_4 PEG_RX#1 [5] C43 EV@1u/6.3V_4 VDD P12
C103 EV@10u/6.3V_6 AA18 PEX_IOVDDQ VDD P14 EV@4.7u/6.3V_6 *EV@4.7u/6.3V_6 *EV@4.7u/6.3V_6 *EV@4.7u/6.3V_6
place near balls C107 EV@4.7u/6.3V_6 AA19 PEX_IOVDDQ PEX_RX1 AF7 PEG_TX1 VDD P16 EV@4.7u/6.3V_6 *EV@4.7u/6.3V_6 *EV@4.7u/6.3V_6
PEG_TX#1 PEG_TX1 [5]
C108 EV@1u/6.3V_4 AA20 PEX_IOVDDQ PEX_RX1 AE7 PEG_TX#1 [5] C33 EV@0.1u/10V_4 VDD P18
place under BGA C101 EV@1u/6.3V_4 AA21 R11
e
PEX_IOVDDQ VDD
AB22 PEX_IOVDDQ PEX_TX2 AD11 VDD R13
AC23 PEX_IOVDDQ PEX_TX2 AC11 PLACE CLOSE TO GPU BALLS L8/M8 VDD R15
AD24 R17
2500mA AE25
PEX_IOVDDQ
PEX_IOVDDQ PEX_RX2 AE9
VDD
VDD T10 PLACE NEAR GPU
AF26 PEX_IOVDDQ PEX_RX2 AF9 VDD T12
AF27 not GC6 2.0 unstuff resistor T14 +VGPU_CORE 47u x1 22u x7 4.7u x6 330u x1
PEX_IOVDDQ VDD
PEX_TX3 AC12 VDD T16 stuff x 1 stuff x 5 RSVD by DG
d
PEX_TX3 AB12 VDD T18
VDD U11
PEX_RX3 AG9 PLACE CLOSE TO BGA VDD U13
AG10 +3V_MAIN L8/M8 U15 + C376 C86 C377 C52 C51 C73 C54
PEX_RX3 VDD
i
VDD U17
PEX_TX4 AB13 C40 EV@4.7u/6.3V_6 VDD V10 C380 EV@47u/6.3V_8 EV@4.7u/25V_8 EV@4.7u/25V_8 EV@4.7u/25V_8
PEX_TX4 AC13 VDD V12 EV@330u/2V_7343 EV@22u/6.3V_8 EV@4.7u/25V_8 EV@4.7u/25V_8
C31 EV@1u/6.3V_4 VDD V14
PEX_RX4 AF10 VDD V16
f
PEX_RX4 AE10 VDD V18 0817 RSVD more NVVDD caps by NV DG
C 210mA of +3V_GFX C32 EV@0.1u/10V_4 C
PEX_TX5 AD14 C44 EV@0.1u/10V_4
+3V_GFX
PLACE NEAR BGA AA8 PEX_PLL_HVDD PEX_TX5 AC14 bga595-nvidia-n13p-gv2-s-a2
EV@0.1u/10V_4 C98 AA9 PEX_PLL_HVDD PLACE CLOSE TO GPU BALLS L8/M8 COMMON C74 C71 C88 C53 C72 C85 C87
EV@4.7u/6.3V_6 C99 PEX_RX5 AE12 U25C
EV@4.7u/6.3V_6 C100 PEX_RX5 AF12 14/14 XVDD/VDD33 *EV@22u/6.3V_8 *EV@22u/6.3V_8 *EV@22u/6.3V_8 *EV@22u/6.3V_8
n
AB8 PEX_SVDD_3V3 0.4MM = 16mils *EV@22u/6.3V_8 *EV@22u/6.3V_8 *EV@4.7u/25V_8
PEX_TX6 AC15 AD10 NC VDD33 G10
AB15 AD7 G12
PEX_TX6
B19
NC
NC
VDD33
VDD33 G8
+3V_GFX for meet Power down sequence
PEX_RX6 AG12
AG13
VDD33 G9
+3V_MAIN for +3V_GFX +VGPU_CORE
PEX_RX6 0.1uF x 8 population x 4
F11 3V3AUX_NC 0.4MM = 16mils D11 *EV@RB500V-40
+VGPU_CORE
AB16
o
+1.05V_GFX [14,15,40] PEX_TX7
PEX_TX7 AC16 V5 FERMI_RSVD1_NC C83 EV@0.1u/10V_4
+3V_GFX [16,17,40] +3V_GFX
V6 FERMI_RSVD2_NC C69 EV@0.1u/10V_4
+VGPU_CORE [39] AF13
PEX_RX7 +1.5V_GFX D10 *EV@820@RB500V-40 C75 EV@0.1u/10V_4
+3V_MAIN [16,17] AE13
PEX_RX7 C59 EV@0.1u/10V_4
+3V [4,5,7,9,11,12,17,19,20,22,24,25,26,27,28,35,37,39,40]
C81 *EV@0.1u/10V_4
NC PEX_TX8 AD17 No stuff D8 when GC6 support. C79 *EV@0.1u/10V_4
PEX_TX8 AC17 CONFIGURABLE C76 *EV@0.1u/10V_4
NC
POWER CHANNELS C66 *EV@0.1u/10V_4
PEX_RX8 AE15 * nc on substrate
NC
AF15
C
NC PEX_RX8
G1 XPWR_G1
F2 VDD_SENSE PEX_TX9 AC18 G2 XPWR_G2
[39] VGA_VCCSENSE NC
AB18 G3
NC PEX_TX9 XPWR_G3
G4 XPWR_G4
[39] VGA_VSSSENSE
F1 GND_SENSE NC PEX_RX9 AG15 G5 XPWR_G5 VDD33
AG16 G6
NC PEX_RX9
G7
XPWR_G6 +3V_GFX/
XPWR_G7
PEX_TX10 AB19 +3V_MAIN
NC
B NC PEX_TX10 AC19 t>0 B
V1 XPWR_V1 NVDD
a
AF16 V2
8mils width NC PEX_RX10
PEX_RX10 AE16
XPWR_V2 +VGPU_CORE
NC
(0.2MM)
PEX_TX11 AD20 PXE_VDD
t
NC
AC20
NC PEX_TX11 +1.05V_GFX
W1 XPWR_W1 t>0
NC PEX_RX11 AE18 W2 XPWR_W2 FBVDDQ
AF18 W3
NC PEX_RX11
W4
XPWR_W3 +1.35_GFX
XPWR_W4
NC PEX_TX12 AC21 N15x Power on sequance
PEX_TX12 AB21
NC
n
bga595-nvidia-n13p-gv2-s-a2 COMMON
*EV@200/F_4 R372 PEX_TSTCLK AF22 AG18 +3V

PEX_TSTCLK_OUT NC PEX_RX12
PEX_TSTCLK# AE22 PEX_TSTCLK_OUT PEX_RX12 AG19
NC
PEX_PLLVDD : 0.3MM = 12mils (150mA)
RSVD R1 and C1 for GV2 co-layout sDDR3 R1 PEX_TX13 AD23 C392
PEX_PLLVDD NC
PEX_RST timing
*short_6 R51 PEX_TX13 AE23 EV@0.1u/10V_4
+1.05V_GFX NC
a
EV@4.7u/6.3V_6 C104 AA14 PEX_PLLVDD PEX_RX13 AF19
NC
C1 C91 AA15 PEX_PLLVDD NC PEX_RX13 AE19
5
EV@1u/6.3V_4 C89
EV@1u/6.3V_4 place near BGA PEX_TX14 AF24 2
NC [12,19,24,25,27,28] PLTRST#
EV@0.1u/10V_4 C90
NC PEX_TX14 AE24 4
PEGX_RST# [16] I/O 3.3V
place near ball 1
[12] DGPU_HOLD_RST#
PEX_RX14 AE21
NC
u
NC PEX_RX14 AF21 U26 PEX_RST
3
EV@10K/F_4 R56 TESTMODE AD9 EV@TC7SH08FU
TESTMODE
PEX_TX15 AG24
NC
NC PEX_TX15 AG25
R375
PEX_RX15 AG21 *EV@0_4 Trise >= 1uS Tfail <=500nS
NC
PEX_RX15 AG22
A NC A
EV@2.49K/F_4 R59 PEX_TERMP AF25 PEX_TERMP

GF117 GF119 PCH control PEGX_RST#
Q

PROJECT : ZYL/ZYLA
1A
DGPU 1/5 (PEG)
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
14
l
<VGA>
U25B
a
2/14 FBA
EV@10K_4 R359 FB_CLAMP F3 FBA_D0 E18 VMA_DQ0
NC GF119
FBA_D1 F18 VMA_DQ1
FB_CLAMP FBA_D2 E16 VMA_DQ2
GF117
i
F17 VMA_DQ3 VMA_DQ[63:0]
N15V-GM no support GC6 function. FBA_D3
D20 VMA_DQ4
VMA_DQ[63:0] [18]
FBA_D4
FBA_D5 D21 VMA_DQ5
FBA_D6 F20 VMA_DQ6 U25F
t
D FBA_D7 E21 VMA_DQ7 13/14 GND D
FBA_D8 E15 VMA_DQ8 M13 GND GND A2
FBA_D9 D15 VMA_DQ9 M15 GND GND AB17
F15 VMA_DQ10 U25D M17 AB20
FBA_D10
FBA_D11 F13 VMA_DQ11
C13 VMA_DQ12
For Fermi 12/14 FBVDDQ N10
N12
GND
GND
GND
GND AB24
AC2
FBA_D12 GND GND
B13 VMA_DQ13 B26 N14 AC22
n
+1.05V_GFX [13,15,40] FBA_D13 FBA_CMD2 R36 EV@10K/F_4 FBVDDQ +1.5V_GFX GND GND
FBA_D14 E13 VMA_DQ14 FBVDDQ C25 N16 GND GND AC26
+1.5V_GFX [13,18,40]
FBA_D15 D13 VMA_DQ15 FBA_CMD3 FBVDDQ E23 N18 GND GND AC5
R32 EV@10K/F_4
FBA_D16 B15 VMA_DQ16 FBVDDQ E26 P11 GND GND AC8
FBA_D17 C16 VMA_DQ17 FBA_CMD5 FBVDDQ F14 P13 GND GND AD12
R41 EV@10K/F_4
FBA_D18 A13 VMA_DQ18 FBVDDQ F21 P15 GND GND AD13
A15 VMA_DQ19
e
FBA_D19 FBA_CMD18 FBVDDQ G13 P17 GND GND A26
R368 EV@10K/F_4
FBA_D20 B18 VMA_DQ20 FBVDDQ G14 P2 GND GND AD15
FBA_D21 A18 VMA_DQ21 FBA_CMD19 FBVDDQ G15 P23 GND GND AD16
R53 EV@10K/F_4
FBA_D22 A19 VMA_DQ22 FBVDDQ G16 P26 GND GND AD18
FBA_D23 C19 VMA_DQ23 FBVDDQ G18 P5 GND GND AD19
FBA_D24 B24 VMA_DQ24 FBVDDQ G19 R10 GND GND AD21
FBA_D25 C23 VMA_DQ25 FBVDDQ G20 R12 GND GND AD22
d
FBA_D26 A25 VMA_DQ26 FBVDDQ G21 R14 GND GND AE11
FBA_D27 A24 VMA_DQ27 FBVDDQ H24 R16 GND GND AE14
FBA_D28 A21 VMA_DQ28 FBVDDQ H26 R18 GND GND AE17
B21 VMA_DQ29 J21 T11 AE20
i
FBA_D29 FBVDDQ GND GND
FBA_D30 C20 VMA_DQ30 FBVDDQ K21 T13 GND GND AB11
FBA_D31 C21 VMA_DQ31 FBVDDQ L22 T15 GND GND AF1
FBA_D32 R22 VMA_DQ32 FBVDDQ L24 T17 GND GND AF11
FBA_CMD0 C27 FBA_CMD0 FBA_D33 R24 VMA_DQ33 FBVDDQ L26 U10 GND GND AF14
[18] FBA_CMD[30:0]
f
FBA_CMD1 C26 FBA_CMD1 FBA_D34 T22 VMA_DQ34 FBVDDQ M21 U12 GND GND AF17
FBA_CMD2 E24 FBA_CMD2 FBA_D35 R23 VMA_DQ35 FBVDDQ N21 U14 GND GND AF20
FBA_CMD3 F24 FBA_CMD3 FBA_D36 N25 VMA_DQ36 FBVDDQ R21 U16 GND GND AF23
FBA_CMD4 D27 FBA_CMD4 FBA_D37 N26 VMA_DQ37 FBVDDQ T21 U18 GND GND AF5
FBA_CMD5 D26 FBA_CMD5 FBA_D38 N23 VMA_DQ38 FBVDDQ V21 U2 GND GND AF8
FBA_CMD6 F25 FBA_CMD6 FBA_D39 N24 VMA_DQ39 FBVDDQ W21 U23 GND GND AG2
C FBA_CMD7 F26 FBA_CMD7 FBA_D40 V23 VMA_DQ40 U26 GND GND AG26 C
n
FBA_CMD8 F23 FBA_CMD8 FBA_D41 V22 VMA_DQ41 U5 GND GND AB14
FBA_CMD9 G22 FBA_CMD9 FBA_D42 T23 VMA_DQ42 V11 GND GND B1
FBA_CMD10 G23 FBA_CMD10 FBA_D43 U22 VMA_DQ43 V13 GND GND B11
FBA_CMD11 G24 FBA_CMD11 FBA_D44 Y24 VMA_DQ44 V15 GND GND B14
FBA_CMD12 F27 FBA_CMD12 FBA_D45 AA24 VMA_DQ45 V17 GND GND B17
FBA_CMD13 G25 FBA_CMD13 FBA_D46 Y22 VMA_DQ46 Y2 GND GND B20
+1.5V_GFX
FBA_CMD14 G27 AA23 VMA_DQ47 Y23 B23
o
FBA_CMD14 FBA_D47 GND GND
FBA_CMD15 G26 FBA_CMD15 FBA_D48 AD27 VMA_DQ48 Y26 GND GND B27
FBA_CMD16 M24 FBA_CMD16 FBA_D49 AB25 VMA_DQ49 Y5 GND GND B5
FBA_CMD17 M23 FBA_CMD17 FBA_D50 AD26 VMA_DQ50 PLACE CLOSE TO GPU BALLS GND B8
FBA_CMD18 K24 FBA_CMD18 FBA_D51 AC25 VMA_DQ51 GND E11
FBA_CMD19 K23 FBA_CMD19 FBA_D52 AA27 VMA_DQ52 C38 EV@0.1u/10V_4 GND E14
FBA_CMD20 M27 FBA_CMD20 FBA_D53 AA26 VMA_DQ53 C35 EV@0.1u/10V_4 GND E17
FBA_CMD21 M26 FBA_CMD21 FBA_D54 W26 VMA_DQ54 C57 *EV@0.1u/10V_4 GND E2
FBA_CMD22 M25 FBA_CMD22 FBA_D55 Y25 VMA_DQ55 C36 *EV@0.1u/10V_4 GND E20
FBA_CMD23 R26 VMA_DQ56
C
K26 FBA_CMD23 FBA_D56 GND E22
FBA_CMD24 K22 FBA_CMD24 FBA_D57 T25 VMA_DQ57 GND E25
FBA_CMD25 J23 FBA_CMD25 FBA_D58 N27 VMA_DQ58 GND E5
FBA_CMD26 J25 FBA_CMD26 FBA_D59 R27 VMA_DQ59 C30 EV@1u/6.3V_4 GND E8
FBA_CMD27 J24 FBA_CMD27 FBA_D60 V26 VMA_DQ60 GND H2
FBA_CMD28 K27 FBA_CMD28 FBA_D61 V27 VMA_DQ61 C27 EV@1u/6.3V_4 GND H23
FBA_CMD29 K25 FBA_CMD29 FBA_D62 W27 VMA_DQ62 GND H25
FBA_CMD30 J27 FBA_CMD30 FBA_D63 W25 VMA_DQ63 C28 *EV@1u/6.3V_4 GND H5
TP36 J26 FBA_CMD31 GND K11
+1.5V_GFX EV@40.2/F_4 R35 FB_CAL_PD_VDDQ D22 C77 *EV@1u/6.3V_4 K13
a
FB_CAL_PD_VDDQ GND
FBA_DQM0 D19 VMA_DM0 GND K15
VMA_DM[7..0] [18]
FBA_DQM1 D14 VMA_DM1 GND K17
FBA_DQM2 C17 VMA_DM2 EV@42.2/F_4 R29 FB_CAL_PU_GND C24 FB_CAL_PU_GND GND L10
VMA_DM3
t
FBA_DQM3 C22 GND L12
FBA_DQM4 P24 VMA_DM4 GND L14
FBA_DQM5 W24 VMA_DM5 EV@51.1/F_4 R27 FB_CAL_TERM_GND B25 FB_CALTERM_GND GND L16
FBA_DQM6 AA25 VMA_DM6 C45 EV@4.7u/6.3V_6 GND L18
B *EV@60.4/F_4 R39 FBA_DEBUG0 F22 U25 VMA_DM7 PLACE CLOSE TO GPU BALLS C133 EV@4.7u/6.3V_6 L2 B
+1.5V_GFX FBA_DEBUG0 FBA_DQM7 GND
*EV@60.4/F_4 R42 FBA_DEBUG1 J22 FBA_DEBUG1
bga595-nvidia-n13p-gv2-s-a2 C97 *EV@4.7u/6.3V_6 GND L23
sDDR3 COMMON C14 *EV@4.7u/6.3V_6 GND L25
n
FBA_DQS_WP0 E19 VMA_WDQS0 R47=42.2/F AA7 GND GND L5
VMA_WDQS[7..0] [18]
FBA_DQS_WP1 C15 VMA_WDQS1 R50=51.1/F AB7 GND GND M11
D24 FBA_CLK0 FBA_DQS_WP2 B16 VMA_WDQS2
[18] VMA_CLK0
D25 FBA_CLK0 FBA_DQS_WP3 B22 VMA_WDQS3 C46 EV@10u/6.3V_6
[18] VMA_CLK0#
N22 FBA_CLK1 FBA_DQS_WP4 R25 VMA_WDQS4 C84 *EV@10u/6.3V_6
[18] VMA_CLK1
M22 FBA_CLK1 FBA_DQS_WP5 W23 VMA_WDQS5 C21 *EV@10u/6.3V_6 COMMON bga595-nvidia-n13p-gv2-s-a2
[18] VMA_CLK1#
a
FBA_DQS_WP6 AB26 VMA_WDQS6 C11 *EV@10u/6.3V_6
FBA_DQS_WP7 T26 VMA_WDQS7
D18 FBA_WCK01 FBA_DQS_RN0 F19 VMA_RDQS0 C15 EV@22u/6.3V_8

VMA_RDQS[7..0] [18]
C18 FBA_WCK01 FBA_DQS_RN1 C14 VMA_RDQS1
D17 A16 VMA_RDQS2 C13 EV@22u/6.3V_8
u
FBA_WCK23 FBA_DQS_RN2
D16 FBA_WCK23 FBA_DQS_RN3 A22 VMA_RDQS3
T24 FBA_WCK45 FBA_DQS_RN4 P25 VMA_RDQS4 C12 *EV@22u/6.3V_8
U24 FBA_WCK45 FBA_DQS_RN5 W22 VMA_RDQS5
V24 FBA_WCK67 FBA_DQS_RN6 AB27 VMA_RDQS6 C16 EV@22u/6.3V_8
V25 FBA_WCK67 FBA_DQS_RN7 T27 VMA_RDQS7
EV@HCB1608KF/1A/30ohm_6 PLACE CLOSE TO BGA
+1.05V_GFX L11
EV@22u/6.3V_8 C63
F16 FB_PLLAVDD
Q
+
EV@0.1u/10V_4 C62 *EV@330u/2V_7343 C10
EV@0.1u/10V_4 C70 +FB_PLLAVDD P22 FB_PLLAVDD
+
EV@330u/2V_7343 C350
EV@0.1u/10V_4 C41 +FB_PLLAVDD H22 FB_DLLAVDD GF119
C87 close ball H22 35mA FB_PLLAVDD GF117
A A
FB_VREF_PROBE D23

PROJECT : ZYL/ZYLA
1A
DGPU 2/5 (Memory)
www.vinafix.vn
5 4 3 2 1
5 4 3 2 1
15
<VGA> <HDM> <CRT>
l
U25K
U25G 3/14 DACA
4/14 IFPAB
GF119 GF117
GF117 GF119
GF117 GF119 W5 B7 EV_CRTDCLK R339 EV@2.2K_4
DACA_VDD NC NC I2CA_SCL
AC4 A7 EV_CRTDDAT
a
NC IFPA_TXC I2CA_SDA R344 EV@2.2K_4
NC
IFPA_TXC AC3 AE2 DACA_VREF
GF119 GF117 NC TSEN_VREF
AA6 IFPAB_RSET AF2 DACA_RSET DACA_HSYNC AE3
NC NC NC
i
IFPA_TXD0 Y3 DACA_VSYNC AE4
NC NC
IFPA_TXD0 Y4
NC
V7 IFPAB_PLLVDD DACA_RED AG3
t
NC NC
D IFPA_TXD1 AA2 D
NC
W7 IFPAB_PLLVDD IFPA_TXD1 AA3 DACA_GREEN AF4
NC NC NC
DACA_BLUE AF3
NC
NC IFPA_TXD2 AA1
IFPA_TXD2 AB1
NC
n
AA5 bga595-nvidia-n13p-gv2-s-a2 COMMON
NC IFPA_TXD3
NC IFPA_TXD3 AA4
U25I
6/14 IFPD
e
IFPB_TXC AB4
NC GF119 GF117
IFPB_TXC AB5
NC GF117 GF119
U6 IFPD_RSET NC
GF119 GF117
W6 AB2 DVI/HDMI DP
IFPA_IOVDD NC NC IFPB_TXD4
IFPB_TXD4 AB3
NC
Y6 IFPB_IOVDD T7 IFPD_PLLVDD I2CX_SDA IFPD_AUX P4
NC NC NC
d
NC I2CX_SCL IFPD_AUX P3
IFPB_TXD5 AD2 R7 IFPD_PLLVDD
NC NC
IFPB_TXD5 AD3
NC
R5
i
NC TXC IFPD_L3
IFPD_L3 R4
NC TXC
NC IFPB_TXD6 AD1
IFPB_TXD6 AE1 IFPD_L2 T5
NC NC TXD0
IFPD_L2 T4
NC TXD0
f
IFPB_TXD7 AD5 TXD1 IFPD_L1 U4
NC NC
NC IFPB_TXD7 AD4 IFPD NC TXD1 IFPD_L1 U3
IFPD_L0 V4
NC TXD2
IFPD_L0 V3
NC TXD2
C C
n
NC GPIO14 B3
IFPAB R6 IFPD_IOVDD GF119 NC GPIO17 D4
NC GF117
o
U25H
5/14 IFPC
IFPC
GF119 GF117 U25J
T6 IFPC_RSET GF117 GF119
NC 7/14 IFPEF
C
DVI/HDMI DP GF119
GF117
M7 N5 DVI-DL DVI-SL/HDMI DP
IFPC_PLLVDD NC NC I2CW_SDA IFPC_AUX
N7 IFPC_PLLVDD NC I2CW_SCL IFPC_AUX N4 NC I2CY_SDA I2CY_SDA IFPE_AUX J3
NC GF119 GF117
NC I2CY_SCL I2CY_SCL IFPE_AUX J2
J7 IFPEF_PLLVDD NC
IFPC_L3 N3
NC TXC
NC IFPC_L3 N2 IFPE_L3 J1
TXC NC TXC TXC
K1
a
NC TXC TXC IFPE_L3
IFPC_L2 R3 K7 IFPEF_PLLVDD NC
NC TXD0
IFPC_L2 R2 IFPE_L2 K3
NC TXD0 NC TXD0 TXD0
IFPE_L2 K2
NC TXD0 TXD0
t
TXD1 IFPC_L1 R1
NC
NC TXD1 IFPC_L1 T1 K6 IFPEF_RSET IFPE_L1 M3
NC NC TXD1 TXD1
IFPE_L1 M2
NC TXD1 TXD1
IFPC_L0 T3
B NC TXD2 B
IFPC_L0 T2 IFPE_L0 M1
NC TXD2 NC TXD2 TXD2
IFPE_L0 N1
NC TXD2 TXD2
n
P6 IFPC_IOVDD NC NC GPIO15 C3 IFPE
bga595-nvidia-n13p-gv2-s-a2 COMMON GPIO18 C2

NC HPD_E HPD_E
a
GF119 GF117
H6 IFPE_IOVDD NC
GF119
U25M J6 IFPF_IOVDD GF117
NC DVI-DL DVI-SL/HDMI DP
u
9/14 XTAL_PLL
NV_PLLVDD 0.3MM=12mils 78mA NC I2CZ_SDA IFPF_AUX H4
L9 EV@HCB1608KF/1A/30ohm_6 NV_PLLVDD L6 PLLVDD IFPF_AUX H3
+1.05V_GFX NC I2CZ_SCL
M6 SP_PLLVDD
C29 C42 GPU_SP_PLLVDD 0.3MM=12mils
EV@22u/6.3V_8 EV@0.1u/10V_4 SP_VID_PLLVDD N6 VID_PLLVDD IFPF_L3 J5
GF119 NC TXC
Near GPU Under GPU NC TXC IFPF_L3 J4
NC GF117
NC TXD3 TXD0 IFPF_L2 K5
+1.05V_GFX L10 EV@BLM15PX181SN1D(180,1.5A)_4 NC IFPF_L2 K4
TXD3 TXD0
Q
R336 EV@10K/F_4 R342 EV@10K/F_4
C58 C48 A10 XTALSSIN XTALOUTBUFF C10 NC TXD4 TXD1 IFPF_L1 L4
C61 C60 IFPF NC TXD4 TXD1 IFPF_L1 L3
EV@22u/6.3V_8 EV@4.7u/6.3V_6 EV@0.1u/10V_4 CLK_27M_VGA_2 C11 XTALIN XTALOUT B10 XTALOUT IFPF_L0 M5
NC TXD5 TXD2
EV@0.1u/10V_4 IFPF_L0 M4
bga595-nvidia-n13p-gv2-s-a2 COMMON NC TXD5 TXD2
A close to balls one by one ball A
NC HPD_F GPIO19 F7
CLK_27M_VGA_2
XTALOUT Y11
1 3
+1.05V_GFX [13,14,40]
2 4
C367
EV@10p/50V_4
EV@27MHZ C366
EV@10p/50V_4
PROJECT : ZYL/ZYLA
1A
DGPU 3/5 (Display)
www.vinafix.vn
5 4 3 2 1
5 4 3 2 1
<VGA>
16
l
U25L Binary mode strapping:
10/14 MISC2
For N15V-GM-B sku:
Device ID=0x1140
E10 VMON_IN0 R3= N.C.
F10 D12
1.ROM_SCLK =10K pull down. Strap0 Strap1 Strap2 Strap3
a
VMON_IN1 ROM_CS R37 EV@10K_4 +3V_GFX Vendor Vendor P/N
ROM_SI B12 ROM_SI
ROM_SO
2.ROM_SI= 10k pull down HYNIX HT5C4G63AFR-11C 0 0 1 0
3.ROM_SO= 10k pull down
ROM_SO A12
STRAP0 D1 C12 ROM_SCLK
STRAP0 ROM_SCLK MICRON MT41J256M16HA-093G:E 1 0 1 1
i
STRAP1
STRAP2
D2
E4
STRAP1 4.Strap3~0 = RVL memory
SAMSUNG K4W4G164D-BC1A 1 0 0 1 Default
binary mode setting.
D STRAP2 D
STRAP3 E3 STRAP3
STRAP4 D3 STRAP4
5.Strap4 =10k pull down
t
GF119 GF117
C1 +3V_GFX
R3 STRAP5_NC NC
BUFRST D11 R21 *EV@10K_4 +3V_MAIN
R362 *EV@40.2K/F_4 F6 MULTISTRAP_REF0_GND PGOOD D10

N15V-GM NC
R334 R18
n
GF119 GF117
R353 R351 R357 R355 R349
R38 *EV@40.2K F4 MULTISTRAP_REF1_GND NC R335 EV@10K/F_4 *EV@10K/F_4 *EV@10K/F_4 EV@10K/F_4 *EV@10K/F_4
CEC E9
F5 TP34 STRAP0
R34 *EV@40.2K MULTISTRAP_REF2_GND NC *EV@4.99K/F_4 *EV@4.99K/F_4 *EV@4.99K/F_4
ROM_SI STRAP1
ROM_SO STRAP2 STRAP0~3:
ROM_SCLK STRAP3
e
bga595-nvidia-n13p-gv2-s-a2 COMMON STRAP4
R341 R340 R19

+3V_GFX [13,17,40]
EV@10K/F_4 EV@10K/F_4 EV@10K/F_4 R352 R350 R356 R354 R348
+3V_MAIN [13,17]
*EV@10K/F_4 EV@10K/F_4 EV@10K/F_4 *EV@10K/F_4 EV@10K/F_4
N15V-GM Stuff 10K

U25N
d
8/14 MISC1
D9 GFX_SCL
I2CS Slave Address= 0x9E (default)
I2CS_SCL
I2CS_SDA D8 GFX_SDA N15V-GM: Stuff 10K pull down
A9 DGPU_EDIDCLK
i
I2CC_SCL EV@2.2K_4 R337 N15V-GM: Memory strap setting Please follow N15x latest RVL "RVL-06891-001".
I2CC_SDA B9 DGPU_EDIDDATA EV@2.2K_4 R343
C C
E12 THERMDN GF117 GF119

I2CB_SCL C9 N13P_SCL EV@2.2K_4 R338 N15V-GM VRAM Configuration Table:
f
NC
F12 THERMDP I2CB_SDA C8 N13P_SDA EV@2.2K_4 R30
NC
Strap
[3:0] DESCRIPTION Vendor Vendor P/N QCI P/N
JTAG_TCK AE5 JTAG_TCK
JTAG_TMS AD6
JTAG_TDI AE6
JTAG_TMS 0100 (0x4) DDR3 256MBx16,1000MHz HYNIX H5TC4G63AFR-11C
JTAG_TDO AF6
JTAG_TDI 4Gb 1101 (0xD) DDR3 256MBx16,1000MHz MICRON MT41J256M16HA-093G:E
TP39 JTAG_TRST#AG4
JTAG_TDO
C6
1001 (0x9) DDR3 256MBx16,1000MHz SAMSUNG K4W4G1646D-BC1A
JTAG_TRST GPIO0
n
B2 TP10
GPIO1
GPIO2 D6
GPIO3 C7 STRAP3
GPIO4 F9
GPIO5 A3 Optimus ---> 4.99k PD
A4 TP9
GPIO6
GPIO7 B6 Resistor P/N
GPIO8 A6 GPIO8_OVERT#
10K ---> CS31002FB26
o
GPIO9 F8 GPIO9_ALERT
GPIO10 C5
GPIO11 E7
PWM-VID [39]
GPIO12 D7 GPIO12_ACIN
GPIO13 B4 DGPU_PSI
DGPU_PSI [39]
GF117 GF119
NC GPIO16 D5
NC GPIO20 E6
GPIO21 C4 GPU_PEX_RST_HOLD#
NC
C
B B
GPIO8 VGA thrmtrip# => inform EC SMBus(VGA)

over temperature protect
a
dGPU_OTP# = EC control +3V_GFX +3V_MAIN
+3V_GFX
GPIO8_OVERT# 1 3
GPIO9_ALERT dGPU_OTP# [19]
R25 EV@10K/F_4
+3V_GFX Q13 EV@2N7002K R14
t
DGPU_PSI R346 *EV@10K/F_4 R15 EV@10K/F_4
2
EV@10K/F_4
GPIO8_OVERT# R345 EV@10K/F_4 Q11
R20 *EV@0_4 R22 *0/short_4 5
JTAG_TMS PEGX_RST# [13]
R48 *EV@10K/F_4
GFX_SCL 4 3
JTAG_TDI MBCLK2 [19,22]
R49 *EV@10K/F_4
n
GPIO12_ACIN R11 EV@10K/F_4 2
GPU_PEX_RST_HOLD# R347 *EV@10K/F_4 GFX_SDA 1 6

+3V_GFX MBDATA2 [19,22]
JTAG_TCK R57 *EV@10K/F_4 VGA/VGA EC/S5
EV@2N7002DW
JTAG_TRST# R60 EV@10K/F_4
a
Q9
2
EV@2N7002K dGPU_OPP# = EC control

GPIO12_ACIN 1 3
A dGPU_OPP# [19] A
GPIO12 AC detect
AC high
DC low
u
Vendor P/N 820M QCI P/N
N15V-GM-B-A2 GeForce 820M 0x1140 AJ0N15V0T03

PROJECT : ZYL/ZYLA
1A
DGPU 4/5 (MIO/GPIO)
Q
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
17
l
+3V_GFX [13,16,40]
+3V_MAIN [13,16]
+3V [4,5,7,9,11,12,13,19,20,22,24,25,26,27,28,35,37,39,40]
ia
D +3V D
t
+3V_GFX
C127
EV@0.1u/10V_4
n
60mil
5
R10
EV@0_8 U10 2 R65 *short_4
HWPG_1.5VGFX [40]
e
4
[12] DGPU_PWROK GPU_PWR_GD
1 GPU_PWR_GD [39]
N15V stuff not support GC6. 60mil R64 EV@TC7SH08FU
3
+3V_MAIN EV@100K_4
id
*EV@0_4 R63
C C
n f
+3V_GFX
+3V
R16
o
EV@4.7K_4
R12
3V_MAIN_PWGD [39,40]
EV@4.7K_4
3
R17
2 EV@100K/F_4 For N15V-GM no Support GC6 Stuff R1299
3
C
+3V_MAIN R9 EV@4.7K_4 2
C18 Q12 EV@0_4 R62 GPU_PWR_GD
[40] FBVDDQ_EN
1
Q10 EV@1000p/50V_4 EV@DTC144EU

1
B C17 EV@MMBT3904-7-F PD at GPU power side B

*EV@1000p/50V_4 +1.05V_GFX and GPU core power EN R61
EV@100K_4 C122 *EV@0.1u/10V_4
n ta
ua
A A

PROJECT : ZYL/ZYLA
Q
1A
DGPU 5/5 (Power/Ground)
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
18
l
+1.05V_GFX [13,14,15,40]
[14]
[14]
[14]
VMA_DQ[63..0]
VMA_DM[7..0]
VMA_WDQS[7..0]
CHANNEL A: 2048MB DDR3X16
a
[14] VMA_RDQS[7..0]
VRAM9 VRAM11 VRAM10 VRAM12
i
VREFC_VMA1 M8 E3 VMA_DQ12 VREFC_VMA1 M8 E3 VMA_DQ21 VREFC_VMA3 M8 E3 VMA_DQ40 VREFC_VMA3 M8 E3 VMA_DQ62
VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ9 VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ19 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ45 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ58
VREFDQ DQL1 F2 VMA_DQ13 VREFDQ DQL1 F2 VMA_DQ20 VREFDQ DQL1 F2 VMA_DQ41 VREFDQ DQL1 F2 VMA_DQ63
FBA_CMD9 DQL2 VMA_DQ11 FBA_CMD9 DQL2 VMA_DQ18 FBA_CMD9 DQL2 VMA_DQ47 FBA_CMD9 DQL2 VMA_DQ56
t
N3 F8 N3 F8 N3 F8 N3 F8
D [14] FBA_CMD9 FBA_CMD11 P7 A0 DQL3 H3 VMA_DQ14 FBA_CMD11 P7 A0 DQL3 H3 VMA_DQ23 FBA_CMD11 P7 A0 DQL3 H3 VMA_DQ43 FBA_CMD11 P7 A0 DQL3 H3 VMA_DQ61 D
[14] FBA_CMD11 FBA_CMD8 P3 A1 DQL4 H8 VMA_DQ10 FBA_CMD8 P3 A1 DQL4 H8 VMA_DQ16 FBA_CMD8 P3 A1 DQL4 H8 VMA_DQ46 FBA_CMD8 P3 A1 DQL4 H8 VMA_DQ57
[14] FBA_CMD8 FBA_CMD25 A2 DQL5 VMA_DQ15 FBA_CMD25 A2 DQL5 VMA_DQ22 FBA_CMD25 A2 DQL5 VMA_DQ42 FBA_CMD25 A2 DQL5 VMA_DQ60
N2 G2 N2 G2 N2 G2 N2 G2
[14] FBA_CMD25 FBA_CMD10 P8 A3 DQL6 H7 VMA_DQ8 FBA_CMD10 P8 A3 DQL6 H7 VMA_DQ17 FBA_CMD10 P8 A3 DQL6 H7 VMA_DQ44 FBA_CMD10 P8 A3 DQL6 H7 VMA_DQ59
[14] FBA_CMD10 FBA_CMD24 P2 A4 DQL7 FBA_CMD24 P2 A4 DQL7 FBA_CMD24 P2 A4 DQL7 FBA_CMD24 P2 A4 DQL7
[14] FBA_CMD24 FBA_CMD22 R8 A5 FBA_CMD22 R8 A5 FBA_CMD22 R8 A5 FBA_CMD22 R8 A5
n
[14] FBA_CMD22 FBA_CMD7 R2 A6 D7 VMA_DQ7 FBA_CMD7 R2 A6 D7 VMA_DQ31 FBA_CMD7 R2 A6 D7 VMA_DQ33 FBA_CMD7 R2 A6 D7 VMA_DQ54
[14] FBA_CMD7 FBA_CMD21 A7 DQU0 VMA_DQ0 FBA_CMD21 A7 DQU0 VMA_DQ24 FBA_CMD21 A7 DQU0 VMA_DQ39 FBA_CMD21 A7 DQU0 VMA_DQ48
T8 C3 T8 C3 T8 C3 T8 C3
[14] FBA_CMD21 FBA_CMD6 R3 A8 DQU1 C8 VMA_DQ5 FBA_CMD6 R3 A8 DQU1 C8 VMA_DQ30 FBA_CMD6 R3 A8 DQU1 C8 VMA_DQ34 FBA_CMD6 R3 A8 DQU1 C8 VMA_DQ55
[14] FBA_CMD6 FBA_CMD29 L7 A9 DQU2 C2 VMA_DQ3 FBA_CMD29 L7 A9 DQU2 C2 VMA_DQ26 FBA_CMD29 L7 A9 DQU2 C2 VMA_DQ37 FBA_CMD29 L7 A9 DQU2 C2 VMA_DQ50
[14] FBA_CMD29 FBA_CMD23 R7 A10/AP DQU3 A7 VMA_DQ4 FBA_CMD23 R7 A10/AP DQU3 A7 VMA_DQ28 FBA_CMD23 R7 A10/AP DQU3 A7 VMA_DQ35 FBA_CMD23 R7 A10/AP DQU3 A7 VMA_DQ53
e
[14] FBA_CMD23 FBA_CMD28 A11 DQU4 VMA_DQ2 FBA_CMD28 A11 DQU4 VMA_DQ27 FBA_CMD28 A11 DQU4 VMA_DQ36 FBA_CMD28 A11 DQU4 VMA_DQ51
N7 A2 N7 A2 N7 A2 N7 A2
[14] FBA_CMD28 FBA_CMD20 A12/BC DQU5 VMA_DQ6 FBA_CMD20 A12/BC DQU5 VMA_DQ29 FBA_CMD20 A12/BC DQU5 VMA_DQ32 FBA_CMD20 A12/BC DQU5 VMA_DQ52
T3 B8 T3 B8 T3 B8 T3 B8
[14] FBA_CMD20 FBA_CMD4 T7 A13 DQU6 A3 VMA_DQ1 FBA_CMD4 T7 A13 DQU6 A3 VMA_DQ25 FBA_CMD4 T7 A13 DQU6 A3 VMA_DQ38 FBA_CMD4 T7 A13 DQU6 A3 VMA_DQ49
[14] FBA_CMD4 FBA_CMD14 M7 A14 DQU7 FBA_CMD14 M7 A14 DQU7 FBA_CMD14 M7 A14 DQU7 FBA_CMD14 M7 A14 DQU7
[14] FBA_CMD14 A15 A15 A15 A15
d
FBA_CMD12 M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2
[14] FBA_CMD12 FBA_CMD27 N8 BA0 VDD#B2 D9 +1.5V_GFX FBA_CMD27 N8 BA0 VDD#B2 D9 FBA_CMD27 N8 BA0 VDD#B2 D9 +1.5V_GFX FBA_CMD27 N8 BA0 VDD#B2 D9
[14] FBA_CMD27 FBA_CMD26 M3 BA1 VDD#D9 G7 FBA_CMD26 M3 BA1 VDD#D9 G7 FBA_CMD26 M3 BA1 VDD#D9 G7 FBA_CMD26 M3 BA1 VDD#D9 G7
[14] FBA_CMD26 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
i
K2 K2 K2 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
VMA_CLK0 J7 VDD#N1 N9 VMA_CLK0 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9
[14] VMA_CLK0 CK VDD#N9 CK VDD#N9 [14] VMA_CLK1 CK VDD#N9 CK VDD#N9
f
VMA_CLK0# K7 R1 VMA_CLK0# K7 R1 VMA_CLK1# K7 R1 VMA_CLK1# K7 R1
[14] VMA_CLK0# FBA_CMD3 CK VDD#R1 FBA_CMD3 CK VDD#R1 [14] VMA_CLK1# FBA_CMD19 CK VDD#R1 FBA_CMD19 CK VDD#R1 +1.5V_GFX
K9 R9 K9 R9 K9 R9 K9 R9
[14] FBA_CMD3 CKE VDD#R9 CKE VDD#R9 +1.5V_GFX [14] FBA_CMD19 CKE VDD#R9 CKE VDD#R9
FBA_CMD2 K1 A1 FBA_CMD2 K1 A1 FBA_CMD18 K1 A1 FBA_CMD18 K1 A1

[14] FBA_CMD2 FBA_CMD0 ODT VDDQ#A1 FBA_CMD0 ODT VDDQ#A1 [14] FBA_CMD18 FBA_CMD16 ODT VDDQ#A1 FBA_CMD16 ODT VDDQ#A1
C L2 A8 L2 A8 L2 A8 L2 A8 C
[14] FBA_CMD0 FBA_CMD30 CS VDDQ#A8 FBA_CMD30 CS VDDQ#A8 [14] FBA_CMD16 FBA_CMD30 CS VDDQ#A8 FBA_CMD30 CS VDDQ#A8
n
J3 C1 J3 C1 J3 C1 J3 C1
[14] FBA_CMD30 FBA_CMD15 RAS VDDQ#C1 FBA_CMD15 RAS VDDQ#C1 FBA_CMD15 RAS VDDQ#C1 FBA_CMD15 RAS VDDQ#C1
K3 C9 K3 C9 K3 C9 K3 C9
[14] FBA_CMD15 FBA_CMD13 CAS VDDQ#C9 FBA_CMD13 CAS VDDQ#C9 FBA_CMD13 CAS VDDQ#C9 FBA_CMD13 CAS VDDQ#C9
L3 D2 L3 D2 L3 D2 L3 D2
[14] FBA_CMD13 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
VMA_WDQS1 F3 VDDQ#F1 H2 VMA_WDQS2 F3 VDDQ#F1 H2 VMA_WDQS5 F3 VDDQ#F1 H2 VMA_WDQS7 F3 VDDQ#F1 H2
VMA_RDQS1 G3 DQSL VDDQ#H2 H9 VMA_RDQS2 G3 DQSL VDDQ#H2 H9 VMA_RDQS5 G3 DQSL VDDQ#H2 H9 VMA_RDQS7 G3 DQSL VDDQ#H2 H9
o
DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9
VMA_DM1 E7 A9 VMA_DM2 E7 A9 VMA_DM5 E7 A9 VMA_DM7 E7 A9

VMA_DM0 D3 DML VSS#A9 B3 VMA_DM3 D3 DML VSS#A9 B3 VMA_DM4 D3 DML VSS#A9 B3 VMA_DM6 D3 DML VSS#A9 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
VMA_WDQS0 C7 VSS#G8 J2 VMA_WDQS3 C7 VSS#G8 J2 VMA_WDQS4 C7 VSS#G8 J2 VMA_WDQS6 C7 VSS#G8 J2
VMA_RDQS0 B7 DQSU VSS#J2 J8 VMA_RDQS3 B7 DQSU VSS#J2 J8 VMA_RDQS4 B7 DQSU VSS#J2 J8 VMA_RDQS6 B7 DQSU VSS#J2 J8
C
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9
[14] FBA_CMD5 RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1
VMA_ZQ1 L8 VSS#T1 T9 VMA_ZQ2 L8 VSS#T1 T9 VMA_ZQ3 L8 VSS#T1 T9 VMA_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
a
Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R33 VSSQ#B9 D1 R358 VSSQ#B9 D1 R50 VSSQ#B9 D1 R365 VSSQ#B9 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
t
EV@243/F_4 D8 EV@243/F_4 D8 EV@243/F_4 D8 EV@243/F_4 D8
VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
B
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 B
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
n
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
EV@VRAM _DDR3_HYNIX_256MX16 EV@VRAM _DDR3_HYNIX_256MX16 EV@VRAM _DDR3_HYNIX_256MX16 EV@VRAM _DDR3_HYNIX_256MX16
a
+1.5V_GFX +1.5V_GFX FBA_CMD17 TP11 +1.5V_GFX +1.5V_GFX
[14] FBA_CMD17
FBA_CMD1 TP35
[14] FBA_CMD1
10/14 modify
VMA_CLK0 R360 R23 R47 R371
u
EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4
R31 VMA_CLK1
EV@162/F_4
VREFC_VMA1 VREFD_VMA1 R58 VREFC_VMA3 VREFD_VMA3
VMA_CLK0# EV@162/F_4
Fermi : Change to 160 ohm C372 VMA_CLK1# C96 C386

R361 R26 C26 R44 EV@0.1u/10V_4 R370 EV@0.1u/10V_4
1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402) EV@0.1u/10V_4 EV@0.1u/10V_4 Fermi : Change to 160 ohm
Q
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402) EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4
1 : CS11602JB00 ,RES CHIP 160 1/16W +-5%(0402)
2 : CS11622FB07 ,RES CHIP 162 1/16W +-1%(0402)
+1.5V_GFX
A +1.5V_GFX A
C362 EV@10u/6.3V_6 C400 EV@10u/6.3V_6 +1.5V_GFX
+1.5V_GFX C364 EV@1u/10V_4 C128 EV@10u/6.3V_6 C20 EV@10u/6.3V_6

C390 EV@1u/10V_4
+1.5V_GFX C34 EV@10u/6.3V_6 C124 EV@1u/10V_4 C363 EV@0.1u/10V_4 C361 EV@10u/6.3V_6
C132 EV@1u/10V_4
C404
C371
EV@1u/10V_4
EV@1u/10V_4 C37 EV@1u/10V_4
C370
C403
EV@0.1u/10V_4
EV@0.1u/10V_4
C393 EV@1u/10V_4 C381 EV@1u/10V_4 C113 EV@1u/10V_4 C383 EV@0.1u/10V_4
C121 EV@1u/10V_4 C365 EV@1u/10V_4 C24 EV@1u/10V_4 C369 EV@0.1u/10V_4 C115 EV@0.1u/10V_4 PROJECT : ZYL/ZYLA
C384 EV@1u/10V_4 C23 EV@1u/10V_4 C368 EV@1u/10V_4 C114 EV@0.1u/10V_4 C25 EV@0.1u/10V_4 Size Document Number Rev
1A
N15P- DDR3 VRAM 1/2
www.vinafix.vn
5 4 3 2 1
5 4 3 2 1
EC 985LB1(KBC)
19
l
1.8V p/n: AJ009850F02 +3VPCU
1.8V interface
Discription:IC CONTROLLER(128P)NPCE985LB1DX(LQFP) S5_ON R205 4.7K/J_4
a
R156 2.2/J_6
L15 PBY160808T-250Y-N/3A/25ohm_6 +A3VPCU 1 2 +1.8V 985L-A0 connects to +3v / 985L-B1 connects to +1.8v
C176 C167 2013/07/31
30mil SM BUS PU(KBC)
i
+3VPCU SMBus Tr fail (spec
0.1u/10V_4 10U/6.3V_6 1000 ns max, result
1046 ns)
10mA MBCLK R201 4.7K/J_4
Change PU
E775AGND MBDATA R204 4.7K/J_4 resister(R424,R428)
t
D18 from 10K to 4.7K
1
D +3VPCU D
VCCSPI R172 *RB500V-40 C191 C184 C180 D16
R153 2.2/J_6 0_6 R208 0_4
1 2 +3VPCU_EC 0.03A(30mils) 4.7U/10V_6 0.1u/10V_4 0.1u/10V_4 5V/30V/0.2p_4
+3V
MBCLK2 R213 4.7K/J_4 R214 *0_4 +3VPCU
2
C168 C178 C249 C271 C236 C171 MBDATA2 R210 4.7K/J_4
115
102
20140423:
19
46
76
88
4
4.7U/10V_6 0.1u/10V_4 *.1u/16V_4 0.1u/10V_4 39p/50V_4 0.1u/10V_4 U13
n
Default use +3V
VCC1
VCC2
VCC3
VCC4
VCC5
AVCC
VDD
E775AGND C164 *10u/6.3V_6 ICMNT
H_PROCHOT# [5,35]
C172 0.01U/25V_4
3
3 97
CLK_24M_KBC [7,28] LFRAME# LFRAME GPIO90/AD0 ICMNT_R TEMP_MBAT [30]
126 98 R164 *0/short_4 ICMNT Q24
[7,28] LAD0 LAD0 GPIO91/AD1 ICMNT [30]
e
127 A/D 99
[7,28] LAD1 LAD1 GPIO92/AD2 PROCHOT_EC
128 100 2
[7,28] LAD2 LAD2 GPIO93/AD3 THRM_MOINTOR [8]
1
[7,28] LAD3 2 LAD3
R177
[7] CLK_24M_KBC LCLK EC_DRAMRST_CNTRL
101 TP19 R161 2N7002K
*22/J_4 8 GPIO94/DA0 105
[7,28] CLKRUN# D/A
1
GPIO11/CLKRUN GPI95/DA1
GPI96/DA2
106 100K_4 Q54 need Replacement at BOT layer.
SIO_A20GATE 121
d
GPIO85/GA20
C194 SIO_RCIN# 122
TP18 KBRST/GPIO86
*10p/50V_4 64
GPIO01/TB2 ACIN [30]
29 LPC 79
i
[12] SIO_EXT_SCI# ECSCI/GPIO54 GPIO02 SLP_SUS#_EC [12]
95
6 GPIO03 96 NBSWON# [22]
TP20 GPIO24/LDRQ GPIO04 SLP_SUS_ON [36]
108
124 GPIO05 93 LID# [22]
[26] AMP_MUTE# GPIO10/LPCPD GPIO06/IOX_DOUT/RTS1 EC_PWROK
94
f
GPIO07 EC_FPBACK# [22]
PLTRST# 7 114
[12,13,24,25,27,28] PLTRST# LREST GPIO16 109 BT_POWERON [28]
123 GPIO30 15
DPWROK_EC [12] 20140421: PLTRST#
[28] IOAC_PCIERST# GPIO67/PWUREQ GPIO36/CTS1 TP23 Delete 1.05V_GFX_EN for Page.40
80 VRON
GPIO41 HWPG_EC VRON [35]
125 17 20140418:
[12] SERIRQ SERIRQ GPIO42/SCL3B/TCK 20
GPIO43/SDA3B/TMS SUSC# [12] Add VRON for Page.35
1
+3V 9 21
[12] SIO_EXT_SMI# GPIO65/SMI GPIO44/TDI SUSB# [12]
n
C GPIO 24 C521 D37 D38 Close to EC C
R211 SIO_EXT_SCI# GPO47/SCL4 25 TP_POWER_ON 5V/30V/0.2p_4 5V/30V/0.2p_4
GPIO50/PSCLK3/TDO TP_POWER_ON [37] 0.1U/10V_4
10K_4 54 26
[21] MX0 S5_ON [31,33,37,38]
2
55 KBSIN0 GPIO51 27
R185 SIO_EXT_SMI# [21] MX1 56 KBSIN1 GPIO52/PSDAT3/RDY 28
TP24 20140421:
10K_4
[21] MX2
57 KBSIN2 GPIO53/SDA4 73
PCH_SLP_S0_N [12] Delete DGPU_PWROK
[21] MX3 58 KBSIN3 GPIO70 74 PWROK_EC_uR TP_EN_EC [21] EC_PWROK
R198 *0/short_4
[21] MX4 KBSIN4 GPIO71 RSMRST#_uR EC_PWROK [2,12]
59 75 R196 *0/short_4
o
[21] MX5 KBSIN5 GPIO72 EMU_LID RSMRST# [12]
60 82
[21] MX6 KBSIN6 GPIO75/SPI_SCK TP22
61 83
[21] MX7 KBSIN7 GPO76/SHBM RF_EN [28]
SERIRQ 84
53 GPIO77 91 WAKE_SRC_1 [12,27,28]
[21] MY0 KBSOUT0/JENK GPIO81 DNBSWON# [12]
52 110 pin91 in 985L is 1.8V only +3V_S5
[21] MY1 KBSOUT1/TCK GPO82/IOX_LDSH/TEST HWPG(KBC)
1
51 112
[21] MY2 50 KBSOUT2/TMS GPO84/IOX_SCLK/XORTR 107 USBON# [24,25]
D17
[21] MY3 KBSOUT3/TDI GPIO97 EC_ODD_EJ [22]
*14V/38V/100P_4 49 KB R195
[21] MY4 48 KBSOUT4/JEN0
[21] MY5
2
47 KBSOUT5/TDO 31 dGPU_OTP#
[21] MY6 dGPU_OTP# [16]
C
43 KBSOUT6/RDY GPIO56/TA1 117 10K_4
[21] MY7 42 KBSOUT7 GPIO20/TA2/IOX_DIN_DIO 63 SUSON [36]
[21] MY8 KBSOUT8 GPIO14/TB1 FANSIG [22] HWPG_EC
41 D19 *BAS316
[21] MY9 40 KBSOUT9/SDP_VIS 32 [33] HWPG_1.0V
[21] MY10
39 KBSOUT10/P80_CLK TIMER GPIO15/A_PWM 118
TP27
D20 *BAS316
[21] MY11 KBSOUT11/P80_DAT GPIO21/B_PWM PCBEEP_EC [26] [34,37] HWPG_1.05V
38 62
[21] MY12 37 KBSOUT12/GPIO64 GPIO13/C_PWM 65 PWRLED# [25]
D21 *BAS316
[21] MY13 KBSOUT13/GPIO63 GPIO32/D_PWM BATLED0# [25] [32] HWPG_1.8V
36 22
[21] MY14 35 KBSOUT14/GPIO62 GPIO45/E_PWM 16 CPUFAN# [22]
D22 BAS316
[21] MY15 KBSOUT15/GPIO61/XOR_OUT GPIO40/F_PWM/RI1 SUSLED# [25] [34,37] HWPG_1.5V
34 81 TP45
[21] MY16 GPIO60/KBSOUT16 GPIO66/G_PWM
33
a
66
[21] MY17 GPIO57/KBSOUT17 GPIO33/H_PWM/SOUT1 BATLED1# [25] 20140421:
2014/04/21: Change to HWPG_1.5V
+3V [4,5,7,9,11,12,13,17,20,22,24,25,26,27,28,35,37,39,40]
MBCLK 70 Delete GPIO66 DGPU_PWR_EN for +3V_GFX
+3VPCU [6,8,21,22,25,26,30,31,32,37,39,40] [30] MBCLK GPIO17/SCL1
MBDATA 69
t
+1.8V [4,5,6,7,9,12,20,21,27,28,37] [30] MBDATA GPIO22/SDA1
MBCLK2 67 SMB 113
+1.8VPCU [12,32,37] [16,22] MBCLK2 GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR PCH_EDP_BLON_R SUSWARN#_EC [6]
MBDATA2 68 14 R192 0_4
[16,22] MBDATA2 GPIO74/SDA2 GPIO34/SIN1/CIRRXL dGPU_OPP# PCH_EDP_BLON [4,22]
119 IR 23
120 GPIO23/SCL3 GPIO46/CIRRXM/TRST 111 PROCHOT_EC dGPU_OPP# [16]
GPIO31/SDA3 GPO83/SOUT_CR/TRIST
B
<20090721_FAE suggestion> B
Stuff 100K and close to EC side <20130722>Change power from +3V
72 86 PCH_SPI_SO_R R454 *0/short_4
[21] TPCLK GPIO37/PSCLK1 F_SDI/F_SDIO1 SOC_SPI_MISO_R1 [6] for improving power consumption to +3V_S5 for power sequence issue
n
71 87 PCH_SPI_SI_R R184 *0/short_4
[21] TPDATA 10 GPIO35/PSDAT1 F_SDO/F_SDIO0 90 SPI_CS0#_UR_EC SOC_SPI_MOSI_R1 [6]
Reserve for writing ME ROM [5] EN_OVERRIDE GPIO26/PSCLK2 PS/2 FIU F_CS0 PCH_SPI_CLK_R
R182 *0/short_4
SOC_SPI_CS#_R1 [6]
11 92 R178 *0/short_4
[21] TP_INT_EC# GPIO27PSDAT2 F_SCK SOC_SPI_CLK_R1 [6] PCH_SPI_SO_R +3V_S5
77 30
[30,35] MAINON GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN_DIO TP26
85 VCC_POR# R189 *47K/F_4 HWPG_1.0V R193 10K_4
a
+1.05V_VTT_EC VCC_POR +3VPCU HWPG_1.05V
R187 0_4 12 R186 R197 10K_4
VCORF
VTT
AGND
EC_PECR_R HWPG_1.8V
GND1
GND2
GND3
GND4
GND5
GND6
R190 *43/J_4 13 104 R203 10K_4

TP21 PECI VREF AC_PRESENT_EC [5]
100K_4
PECI interface should be used on Bay Trail platform,
thus VTT pin can wire to GND and PECI signal NPCE985LB1DX
5
18
45
78
89
116
103
VCORF_uR 44
can be left un-connected.
u
L14 PBY160808T-250Y-N/3A/25ohm_6
SM BUS ARRANGEMENT TABLE MAINON SLP_SUS_ON
C270
SM Bus 1 Battery
1u/6.3V_4 R191 R175
E775AGND 100K/F_4 100K/F_4
SM Bus 2 PCH
Q
SM Bus 3 GPU
GND GND
S5_ON SUSON
985LB1 Pin88 R202 R160

*100K/F_4 100K/F_4
A A
20130606 Colay with 985L

GND GND
+3VPCU_EC R154 *0_6 VCCSPI
C173 C182
R155 0_6 10U/6.3V_6 0.1U/10V_4

+1.8VPCU
PROJECT : ZYL/ZYLA
www.vinafix.vn
1A
NPCE885/FLASH
5 4 3 2 1
5 4 3 2 1
20
l
EDP Conn.
ia
+3V
U23 CN9
t
C346 IC(5P) G5243AT11U
G_5
D D
+1.8V +VIN_BLIGHT
*1U/6.3V_4 5 1 +LCDVCC_1 R327 *0/short_8 LCDVCC 40
IN OUT 39
4 2 38
IN GND 37
1
C348 C343 C342 C344 LCDVCC
3 R333 36
[4] PCH_DISP_ON ON/OFF 35
*0.1u/10V_4 0.1u/10V_4 33p/50V_4 10u/10V_8 10K_4
n
INT
2
R325 *short_6 CCD_PWR 34
+3V 33
R326
*100K/F_4 32
[4] DDI1_EDP_HPD_R 31 G_4
30
3
29
28
e
PCH_DPST_PWM
EDP_HPD_R [4] PCH_DPST_PWM BLON_CON 27
2 [22] BLON_CON
Q39 EDP_HPD_R 26
2N7002K 25
INT_eDP_AUXP C359 EDP@0.1u/16V_4 eDP_AUXP 24
[4] INT_eDP_AUXP INT_eDP_AUXN eDP_AUXN 23
R328 [4] INT_eDP_AUXN C358 EDP@0.1u/16V_4
1
100K/F_4 22
INT_eDP_TXP1 C357 EDP@0.1u/16V_4 eDP_TXP1 21
d
[4] INT_eDP_TXP1 INT_eDP_TXN1 eDP_TXN1 20
[4] INT_eDP_TXN1 C356 EDP@0.1u/16V_4
19
GND GND INT_eDP_TXP0 C355 EDP@0.1u/16V_4 eDP_TXP0 18
[4] INT_eDP_TXP0 INT_eDP_TXN0 eDP_TXN0 17
[4] INT_eDP_TXN0 C354 EDP@0.1u/16V_4
i
L23 16
+VIN_BLIGHT R332 *0/short_4 USBP3+_R 15
+VIN USBP3-_R 14
R331 *0/short_4
CCD_PWR 13
*short_8 C353 *4.7U/25V_8 USBP3+ 12
[7] USBP3+
f
C349 C347 C345 USBP3- 11
0.1U/50V_6 C352 0.1U/50V_6 CCD [7] USBP3- 10 G_1
*10p/50V_4 1000p/50V_4 9
C351 0.01U/25V_4 8
7
6
5
4
n
C C
3
R330 100K/F_4 eDP_AUXP 2
1
G_0
EDP@50398-04071-001
R329 100K/F_4 eDP_AUXN

+3V
o
+VIN [29,30,31,35,36,37,38,39,40] Refer to intel CRB
+1.8V [4,5,6,7,9,12,19,21,27,28,37]
+5V [22,23,26,37]
+3V [4,5,7,9,11,12,13,17,19,22,24,25,26,27,28,35,37,39,40]
HDMI Conn.
a C EMI (EMC)
t
C_TX0_HDMI+
CN11
R377 *100/F_4 20
B
HDMI SMBus Isolation +1.8V C_TX0_HDMI- [4] IN_D2 C412 0.1U/10V_4 C_TX2_HDMI+ 1
2 D2+
SHELL1
B
C411 0.1U/10V_4 C_TX2_HDMI- 3 D2 Shield

Q40 [4] IN_D2# D2-
n
R369 2.2K_4 C_TX1_HDMI+ C410 0.1U/10V_4 C_TX1_HDMI+ 4
+1.8V [4] IN_D1 D1+
5 5
R379 *100/F_4 C409 0.1U/10V_4 C_TX1_HDMI- 6 D1 Shield
HDMI_SCLK [4] IN_D1# C_TX0_HDMI+ D1-
4 3 C406 0.1U/10V_4 7
[4] SDVO_CLK C_TX1_HDMI- [4] IN_D0 D0+
8
C405 0.1U/10V_4 C_TX0_HDMI- 9 D0 Shield 23
C_TX2_HDMI+ [4] IN_D0# C_TXC_HDMI+ D0- GND
2 C402 0.1U/10V_4 10
a
[4] IN_CLK CK+
11 22
1 6 HDMI_SDATA R380 *100/F_4 C401 0.1U/10V_4 C_TXC_HDMI- 12 CK Shield GND
[4] SDVO_DATA [4] IN_CLK# CK-
13
C_TX2_HDMI- RB500V-40 14 CE Remote
+1.8V 5V_HSMBCK HDMI_SCLK NC
R363 2.2K_4 D12 2 1 R364 2.2K_4 15
PJ4N3KDW C_TXC_HDMI+ +5V 5V_HSMBDT HDMI_SDATA DDC CLK
2 1 R367 2.2K_4 16
D13 RB500V-40 17 DDC DATA
HDMI_5V GND
u
R376 *100/F_4 C385 *10P/50V_4 18
C382 *10P/50V_4 19 +5V
C_TXC_HDMI- HP DET 21
SHELL2
HDMI_HPD HDMI connector
C95
VC9
*TVM0G5R5M220R
220P/50V_4
Q
HDMI-Level shift (HDM) Close to HDMI connector
+1.8V
DGPU_CL_HDMIP R76
R74
619/F_4
619/F_4
C_TX2_HDMI+
C_TX2_HDMI-
HDMI-detect (HDM) R46
3
+3V Q42 10K_4

2N7002K R73 619/F_4 C_TX1_HDMI+ +5V
A R71 619/F_4 C_TX1_HDMI- A
2
C_TX0_HDMI+ [4] HDMI_HPD_CON
R70 619/F_4 Q16
R69 619/F_4 C_TX0_HDMI- 3 1 HDMI_5V
IN OUT
3
2
R67 619/F_4 C_TXC_HDMI+ GND
1
R66 619/F_4 C_TXC_HDMI- AP2331SA-7 C116 D14

R381 1 2 2 HDMI_HPD *220p/50V_4 *AZ5125-01J
*100K/F_4 Q14
C413 2N7002K
0.1U/10V_4 R45
Close to Q31 100K/F_4 Quanta Computer Inc.
1
PROJECT : ZYL/ZYLA
www.vinafix.vn
1A
LCD/HDMI/Camera
5 4 3 2 1
5 4 3 2 1
TOUCHPAD BOARD CONN (TPD
l
I2C/PS2 co-lay)
+TPVDD_1 +3V_S5 L30 *0_6
+TPVDD_1 21
a
L29 0_6
50mil
+TPVDD
i
R233 R234 C496
0.1u/10V_4
+1.8V 10K_4 10K_4
t
R232 R255 R254 CN19
D +TPVDD_1 D
200K/F_4 1
2.2K/J_4 2.2K/J_4
2
[19] TPCLK
3
U31 [19] TPDATA
C483 4
0.1U/25V_4 1 8 C280 I2C_TP_SDA_R 5
GND EN
n
C495 C494 I2C_TP_SCL_R 6
2 7 0.1U/25V_4 *0.1u/10V_4 *0.1u/10V_4 TP_INT#_R 7 9
VREF1 VREF2 8 10
I2C_TP_SDA_R [19] TP_EN_EC
[7] I2C_0_SDA
4 5
SDA1 SDA2 connector to EC, check
I2C_TP_SCL_R TP CN
e
[7] I2C_0_SCL 3 6
SCL1 SCL2
PCA9306
TP_INT#_R
d
+1.8V_S5
i
pull high at SOC side +TPVDD_1 C493
+TPVDD_1 *10P/50V_4
R225
*10K_4
f
reserve for auto wake up from S3 issue.
[6] TP_INT#
R252
3
R237
2
10K_4 R259
C *10K_4 10K_4 C
n
3 1 TP_INT#_R 2
[19] TP_INT_EC#
3
Q34 2N7002K
2N7002K Q28
1
2 TP_INT#_R
o
2N7002K
Q27
1
use for Acer request to change design.
KEYBOARD (KBC)
a C +3VPCU
t
RP9
CN20 10 1 MX3
MX4 9 2 MX2
B B
1 MX0 MX5 8 3 MX1
MX0 [19]
2 MX1 MX6 7 4 MX0
MX1 [19]
n
3 MX2 MX7 6 5
MX2 [19]
4 MX3
MX3 [19]
5 MX4 *10K_10P8R
MX4 [19] +3VPCU [6,8,19,22,25,26,30,31,32,37,39,40]
6 MX5
MX5 [19] +1.8V [4,5,6,7,9,12,19,20,27,28,37]
7 MX6
MX6 [19] <EMI> +3V_S5 [2,9,12,19,24,27,28,34,35,37,39,40]
8 MX7
a
MX7 [19] +1.8V_S5 [6,7,9,12,37]
9 MY17 MX4 1 2
MY17 [19] +TPVDD [28,37]
10 MY16 MX5 3 4 CP13
MY16 [19]
11 MY15 MX6 5 6 *220P_8P4R
MY15 [19]
12 MY14 MX7 7 8
MY14 [19]
13 MY13 MY0 1 2
MY13 [19]
14 MY12 MY1 3 4
u
CP12
MY12 [19]
15 MY11 MY2 5 6 *220P_8P4R
MY11 [19]
16 MY10 MY3 7 8
MY10 [19]
17 MY9 MY4 1 2
MY9 [19]
18 MY8 MY5 3 4 CP11
MY8 [19]
19 MY7 MY6 5 6 *220P_8P4R
MY7 [19]
20 MY6 MY7 7 8
MY6 [19]
21 MY5 MY8 1 2
MY5 [19]
22 MY4 MY9 3 4 CP10
MY4 [19]
Q
23 MY3 MY10 5 6 *220P_8P4R
MY3 [19]
24 MY2 MY11 7 8
MY2 [19]
25 MY1 MY12 1 2
MY1 [19]
26 MY0 MY13 3 4 CP9
MY0 [19]
MY14 5 6 *220P_8P4R
MY15 7 8
27 MX0 1 2
A 28 MX1 3 4 CP14 A
MX2 5 6 *220P_8P4R
KB CONN MX3 7 8
MY17 C282 *100p/50V_4

MY16 C281 *100p/50V_4

PROJECT : ZYL/ZYLA
1A
KB/BT/TP/LED/Power Connector
5 4
www.vinafix.vn 3 2
Date: Thursday, July 10, 2014 Sheet
1
21 of 44
5 4 3 2 1
22
l
SATA ODD
Connector
a
CN15
14
i
GND14
1
GND1 2 SATA_TXP_1ST_ODD_C C469 0.01u/25V_4 SATA_TXP1
RXP 3 SATA_TXN_1ST_ODD#_C C468 0.01u/25V_4 SATA_TXN1
RXN 4
t
D GND2 5 SATA_RXN_1ST_ODD#_C C466 0.01u/25V_4 SATA_RXN1 D
TXN 6 SATA_RXP_1ST_ODD_C C464 0.01u/25V_4 SATA_RXP1
TXP 7
GND3
+5V_ODD +5V
8 SATA_DP R183 *1K_4
DP 9 R450 *0/short_8
+5V 10
n
+5V 11 C448 C447 C452 C451 C449 C450
+
MD 12
GND 13 0.01U/25V_4 0.01U/25V_4 *0.1u/16V_4 *0.1u/16V_4 10U/6.3V_6 *100u/6.3V_3528
GND
15
GND15
6030D-13G20
e
EC_ODD_EJ [19]
R167 10K_4 +3V
d
SATA_TXP1
[5] SATA_TXP1 SATA_TXN1
[5] SATA_TXN1
i
SATA_RXN1
[5] SATA_RXN1 SATA_RXP1
[5] SATA_RXP1
f
+5V [20,23,26,37]
+3V [4,5,7,9,11,12,13,17,19,20,24,25,26,27,28,35,37,39,40]
+1.5V [9,23,26,34]
C +3VPCU [6,8,19,21,25,26,30,31,32,37,39,40] C
o n
CPU FAN CTRL(THM)
a C HALL IC (HSR)
t
1st source ：EOD Power Switch. (FSW)
B +3V +5V +3V +5V 2nd source：AL008251000 -- YBT B
3rd source ：AL009132001
+3VPCU
4th source ：AL009249000
n
R94 R81 R92 R80
1K/J_4
10K_4 10K_4 AL009247000 -- BCD
*short_8 C9 1u/10V_4 AL009132001 -- ANC Main source
CN12 AL008251000 -- YBT 2nd
1
+5V_FAN1
4 6
2
30mil +3VPCU
a
3 5 2 LID#
1 3 FAN_PWM_CN1 2
[19] CPUFAN# 1
2
Q19 +3V HE9
MMBT3904-7-F FAN1 APX9132H AI D9 R241
3
*VPORT_6 10K_4
SW10
[19] FANSIG
R130 MISAKI_SW_H1.5
1
10K_4
u
NBSWON# 1 2
For EMI C141 C139
[19] NBSWON#
3 4
1
*220p/50V_4 *220p/50V_4 D15 RB500V-40 5
[20] BLON_CON LID# [19] 6
C284 D23
0.1u/10V_4 *VPORT_6
+3V
2
BLON_CON
3
R129
Q
10K_4
CPU Thermal sensor(THS) / 2 BL#
MB Local TEMP
Q22
3
2N7002K
U28
1
*EMC1412-1-ACZL-TR C423 *0.01U/16V_4

2
A MBCLK2 8 1 PCH_EDP_BLON [4,19] A
[16,19] MBCLK2 +3V Q21
SCLK VCC
MBDATA2 7 2 THERMDA 2N7002K R139
[16,19] MBDATA2 SDA DXP TP42
1
ALERT# 6 3 THERMDC *100K_4
TP40 ALERT# DXN TP41
3
R414 *10K/F_4 4 5
+3V OVERT# GND 2
EC_FPBACK# [19]
Q23
Main:AL001412003 EMC1412-1-ACZL-TR(98h) DTC144EUA
1
2nd:AL000431014 TMP431ADGKR(98h) Quanta Computer Inc.

PROJECT :
ZYL/ZYLA
ODD/FAN/Hall/PSW 1A
www.vinafix.vn
5 4 3 2 1
5 4 3 2 1
l
SATA HDD1 23
a
HDD1
i
D D
t
CN21
10
9 SATA_TXP_1ST_HDD_C C514 0.01U/25V_4 SATA_TXP0
8 SATA_TXN_1ST_HDD#_C C512 0.01U/25V_4 SATA_TXN0
7
6 SATA_RXN_1ST_HDD#_C C511 0.01U/25V_4 SATA_RXN0
5 SATA_RXP_1ST_HDD_C SATA_RXP0
n
C510 0.01U/25V_4
4
3 +5V_HDD1 120mil R548 *short_8 +5V
12 2 C507
11 1 + C509 C508 C506
*100u/6.3V_3528
e
SATA_CONN 10U/6.3V_6 0.1U/10V_4 0.1U/10V_4
d
SATA_TXP0
[5] SATA_TXP0 SATA_TXN0
i
[5] SATA_TXN0
C C
SATA_RXN0
[5] SATA_RXN0 SATA_RXP0
[5] SATA_RXP0
n f
B
+5V
+1.5V
Co
[20,22,26,37]
[9,22,26,34]
B
n ta
a
A A
u
PROJECT : ZYL/ZYLA
1A
SATA HDD/SATA REDRIVER
Q
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
l
USB HUB TP31
USB_HUB_5V
24
EEPROM_SDA
nOVRP1
nOVRP2
PGANG
+3V_USB
+3V_S5
PSELF
a
R291 0_4 +3V_USB
+3V
i
28
27
26
25
24
23
22
U20
D R292 *0/J_4 15 mil +3V_USB D
I2C_SDA
VCC
SELFPWR
OVR#[1]
OVR#[2]
VREG
GANG
t
52.4mA
20130619 Follow vendor's suggestion(Close to pin 21)
2
R289 *0/short_4 USB_H1_N1 1 21 +3V_USB_D R317 *0/short_4 +3V_USB
[7] USB_H1_N DD-0 VCC_D
2
R288 *0/short_4 USB_H1_P1 2 20 nOVRP3 C515 C517 C518 C516 C519
[7] USB_H1_P DD+0 OVR#[3]
3 19 nOVRP4 0.1U/10V_4 0.1U/10V_4 1u/6.3V_4 1u/6.3V_4 0.1U/10V_4 C315 C318
1
DD-1 GL850G-OHY31 OVR#[4]
2
4 18 EEPROM_SCL 10U/6.3V_4 0.1U/10V_4
TP33
1
+3V_USB 5 DD+1 TEST 17 RESET#_USB C333
n
HUB_USB2_N2 VCC_A_5 RESET#
VCC_A_14
6 16 0.1U/10V_4
VCC_A_9
1
HUB_USB2_P2 7 DD-2 DD+4 15
DD+2 DD-4
XOUT
RREF
GND
DD+3
DD-3
GND
XIN
GND GND
QFN28
(Close to GL850G-31) (Close to pin 28)
e
8
+3V_USB 9
10
11
HUB_USB3_N 12
13
+3V_USB 14
29
GL850G-OHY31
HUB_USB3_P
XOUT
RREF
USB_CAR_P [25]
XIN
+3V_S5 [2,9,12,19,21,27,28,34,35,37,39,40] USB_CAR_N [25] CARDREADER
+3V [4,5,7,9,11,12,13,17,19,20,22,25,26,27,28,35,37,39,40]
+5V_S5 [25,31,33,34,35,36,37,39]
GND
id
+3V_USB
f
+3V_USB
C EEPROM_SDA R302 10K_4 C
HUB_USB3_P R307 *1K_4

R322 HUB_USB3_N R301 *1K_4
100K_4 nOVRP1 R305 10K_4
n
Y10
nOVRP2 R310 10K_4
4 3 XOUT nOVRP3 R316 10K_4
R321 *0/J_4 RESET#_USB nOVRP4 R315 10K_4
[12,13,19,25,27,28] PLTRST#
PSELF R313 10K_4
XIN 1 2
C319 R314
C335
o
12MHz 22P/50V_4 *47K_4
C311 LCS 0.1U/10V_4 PGANG R312 100K/F_4
22P/50V_4
RREF R287 619/F_4
GND GND
GND GND
a C USBPWR2 USBPWR2
B
t
USB 2.0 CONNECTOR X2 2014/07/02 Change to
+
CH71001M687
(100U.6.3V_3528)
C224
100u/6.3V_3528
USB 2.0 Port1 2014/07/02 Change to
C279
100u/6.3V_3528
USB 2.0 Port2
CH71001M687
(100U.6.3V_3528)
n
CN16 CN18
EMI@MCM2012B900GBE/400mA/90ohm EMI@MCM2012B900GBE/400mA/90ohm
+5V_S5 1 6 1 6
HUB_USB2_N2 1 2 USBP6_C- 2 VDD GND6 5 HUB_USB3_N 1 2 USBP7_C- 2 VDD GND6 5
HUB_USB2_P2 4 1 2 3 USBP6_C+ 3 D- GND5 HUB_USB3_P 4 1 2 3 USBP7_C+ 3 D- GND5
4 3 4 D+ 7 4 3 4 D+ 7
a
1u/6.3V_4 USBPWR2 L28 GND1 GND7 8 L31 GND1 GND7 8
1 GND8 GND8
1
C263 U14 Close USB2.0
5 1 D31 D30 USB 2.0 CONN D34 D33 USB 2.0 CONN
IN OUT *5V/30V/0.2p_4 *5V/30V/0.2p_4
2 C274 C275 C278 *5V/30V/0.2p_4 *5V/30V/0.2p_4
2
2
GND
u
4 3
[19,25] USBON# EN /OC
G524B2T11U 470P/50V_4 0.1u/10V_4 *100U/6.3V_1206
[7] SOC_USB_OC0
A Main: DFHD04MR377 Main: DFHD04MR377 A
G524B2T11U: Enable: Low Active /2.5A UB2-UARDM-4K1926-4P-R UB2-UARDM-4K1926-4P-R
Q
PROJECT : ZYL/ZYLA
USB BOARD CONN 1A

5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
25
l
USB 3.0 Connector Need Check P/N and F/P USBPWR1
a
CN13
[7] USBP0-
USB3.0 CONN
[7] USBP0+ 1
i
USBP0-_R 1 VBUS
USBP0- R412 *0/short_4 2
USBP0+_R 3 2 D-
USBP0+ R415 *0/short_4
D 4 3 D+ D
t
USB30_RX1- R446 *0/short_4 USB30_RX1-_R 5 4 GND
[7] USB30_RX1- USB30_RX1+ USB30_RX1+_R 6 5 SSRX-
R447 *0/short_4
[7] USB30_RX1+ 6 SSRX+
7
C424 0.1u/10V_4 USB30_TX1-_C R398 *0/short_4 USB30_TX1-_R 8 7 GND
C421 0.1u/10V_4 USB30_TX1+_C R393 *0/short_4 USB30_TX1+_R 9 8 SSTX-
n
+3VPCU [6,8,19,21,22,26,30,31,32,37,39,40] 9 SSTX+
13
12
11
10
+3V [4,5,7,9,11,12,13,17,19,20,22,24,26,27,28,35,37,39,40]
+5V_S5 [24,31,33,34,35,36,37,39] USB30_TX1-
[7] USB30_TX1-
13
12
11
10
USB30_TX1+
[7] USB30_TX1+
+5V_S5 Change footprint 4/23

C415 1u/6.3V_4
USBPWR1
id e USBP0-_R
USBP0+_R
1
RV11
1
RV12
2 *EGA_4
2 *EGA_4
f
C
U27 Close USB3.0 C
5 1 USB30_RX1-_R RV13
1 2 *EGA_4
IN OUT
2 C418 C419 C414 2014/07/02 Change to USB30_RX1+_RRV14
1 2 *EGA_4
GND CH71001M687
+
n
USBON# 4 3 (100U.6.3V_3528)
[19,24] USBON# EN /OC USB30_TX1-_R RV10
1 2 *EGA_4
G524B2T11U 470P/50V_4 0.1u/10V_4 100u/6.3V_3528
USB30_TX1+_R RV9 1 2 *EGA_4
[7] SOC_USB_OC1
o
G547E2P81U: Enable: Low Active /2.5A
B
Card Reader+ LED/B Connector
a C B
n t +3VPCU
CN23
1 13 +3V +3VPCU
a
+3V 2 14
3
[19] PWRLED# 4
[19] SUSLED# 5 C336 C520
[19] BATLED0# 6 39P/50V_4 39P/50V_4
[19] BATLED1# 7
u
[12,13,19,24,27,28] PLTRST# 8
9
[24] USB_CAR_N For ESD
10
[24] USB_CAR_P 11
A 12 A
Card reader+LED/B CONN
Q
PROJECT : ZYL/ZYLA
1A
USB 3.0 / Card Reader+LED CONN
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
HP-R2
Grounding circuit(ADO) +3VPCU
26
l
HP-L2
PIN1, PIN4, PIN3, PIN6 are ANALOG R273
LINE1-VREFO-L
Codec(ADO) LINE1-VREFO-R Q36
100K_4
+1.5V
a
MIC2-VREFO 1 6 SLEEVE
R268
2
CODEC_VREF C307 2.2U/6.3V_4 for discharge
ADOGND
3
INT_AMIC-VREFO C301 10U/6.3V_4 4 3 RING2 *100K_4
ADOGND
Q35
R282 100K/F_4 5
+5VA 2 R267 10K_4 PCH_AZ_CODEC_RST#
t
placed close to codec
C317
C312
D 2N7002DW D
C316 ADOGND PJA138K C288
1u/10V_4
10U/6.3V_4
*1u/10V_4
1
1u/10V_4 C303
C300
0.1u/10V_4 10U/6.3V_4
n
+AZA_VDD
Place next to pin 26
Analog-MIC Demodulation Filter
36
35
34
33
32
31
30
29
28
27
26
25
+1.5VA
U19 2 Power (ADO)
0
A
ADOGND
CPVEE
HP-OUT-L
LINE1-VREFO-L
MIC2-VREFO
LDO1-CAP
AVDD1
AVSS1
CPVDD
CBN
HP-OUT-R
LINE1-VREFO-R
VREF
e
C326
1
d 8
C327
/ ANALOG
10U/6.3V_4 0.1u/10V_4 4
d +3V +1.8V_INT_AMIC-VREFO
ADOGND 37
CBP LINE2-L
24 LINE2-L C295 1u/10V_6 MIC1_INT_L_C
0 R274 1K/J_4 MIC1_INTL1 1
+1.8V_INT_AMIC-VREFO U21
4
A
1u/10V_6 MIC1_INT_R_C
ADOGND
38
AVSS2 LINE2-R
23 LINE2-R C296
-1
R275 1K/J_4
C DN001542000
mic-a-m-qtzea01hf-2p-top
3
IN OUT
4
Place next to pin 40 C323 10U/6.3V_4 39 22 LINE1-L 8

M h R318 2
LDO2-CAP LINE1-L
a GND
d
U22
I: *2.2K/J_4
Analog 40
AVDD2 LINE1-R
21 LINE1-R
C n 1
1
2
MIC1_INTL1 R323 INT_AMIC-VREFO C332 1
SHDN SET
5 R319 *8.2K/F_4
Digital L22 *0/short_6 +5V_PVDD 41 20 F g 2 C337

10K_4
*G923-330T1UF
+5V PVDD1 NC
Io e
i
*0.1u/10V_4 R320 C334
L_SPK+ 42 19 C297 10U/6.3V_4 INT_AMIC_SMD *22p/50V_4
SPK-L+ MIC1-CAP l
n
ADOGND *10K/F_4
C329 C325 C *0.1u/10V_4
L_SPK- 43
SPK-L-
ALC283 MIC2-R/SLEEVE
18 SLEEVE trace width of SLEEVE l
p & RING2 N
10U/6.3V_4 0.1u/10V_4
R_SPK- are required at leastu o40mil and
1
its length should betw
44 17 RING2 ADOGND
f
SPK-R- MIC2-L/RING2 asshort as possible
R_SPK+
ADOGND Vset =1.25V ADOGND
near Codec 45
SPK-R+ MONO-OUT
16
C
R f Vout =Vset[1+AR(1,2)/AR(2,GND)]
46 15 CODEC_JDREF R278 o
h
20K/F_4 o
o
PVDD2 JDREF ADOGND
Low is power down
x
a
GPIO0/DMIC-DATA
amplifier output PD# 47
PDB GPIO1/DMIC-CLK Sense B
14
y
n t
C
C328
48 13 SENSEA R279 39.2K/F_4 n HP_JD# p C
SDATA-OUT
r
n
TP32 SPDIFO/GPIO2 Sense A
P
e
LDO3-CAP
0.1u/10V_4
SDATA-IN
i
DVDD-IO
PCBEEP
RESETB
BIT-CLK
Placement near lr Audio Codec
n
DVDD
SYNC
49
DVSS
DGND .o
near Codec j Analog t
e
1
10
11
12
c
Digital t
o
o
t
+3V R299 *0/short_6 +AZA_VDD

C309 1.6Vrms m
i
HEADPHONE/MIC/LINE combo (AMP)
C299 1u/10V_4 BEEP_1
c
10U/6.3V_4 PCBEEP R281 47K_4 RB500V-40 D26
SPKR [7]
C321 C291 R276 RB500V-40 D25 -
a
PCBEEP_EC [19]
C322 4.7K_4
Place next to pin 1

0.1u/10V_4 10U/6.3V_4 100p/50V_4
-
+3V +1.5V m
C
- MIC2-VREFO R283 2.2K/J_4 FB1/FB2(SLEEVE/RING2) should choose DC resistance (Rdc) < 30m-ohm
PCH_AZ_CODEC_RST#
q to get the best audio performance for HP crosstalk
PCH_AZ_CODEC_RST# [5]
R284 *0/J_4 t R309 2.2K/J_4
DMIC_DAT z SLEEVE
Combo Jack
PCH_AZ_CODEC_SYNC [5] L17 BLM15AG121SN1D/120/500MA_4
TP30
e CN22
Tied at one point only under TP29
DMIC_CLK DVDD_IO R285 0_4 a RING2 L21 BLM15AG121SN1D/120/500MA_4 4
3
the codec or near the codec
0 HP-L2 R303 56/F_4 HP-L3 L19 BLM15AG121SN1D/120/500MA_4 HP-L4 1
R311 *0/short_4 ACZ_SDIN R286 33_4
PCH_AZ_CODEC_SDIN0 [5]
C304 C305 1
h 2
a
R324 *0/short_4 HP-R2 R298 56/F_4 HP-R3 L18 BLM15AG121SN1D/120/500MA_4 HP-R4
R565
R562
*0/short_4
*0/short_4
PCH_AZ_CODEC_BITCLK [5] 0.1u/10V_4 10U/6.3V_4
f HP_JD#
5
6 7
R550 *0/short_4 C310 *22p/50V_4 -
1
R566 *0/short_4 2 SIT_2SJ3052-005111F
t
D35
C505 *1000p/50V_4 PCH_AZ_CODEC_SDOUT [5] Place next to pin 9 p LINE1-L C320 4.7U/6.3V_6 C294 C330 C324 C306
*14V/38V/100P_4
C290 *1000p/50V_4
- LINE1-VREFO-L
2
R300 4.7K_4 100p/50V_4
t
1
100p/50V_4 100p/50V_4 100p/50V_4 D24 D28 ADOGND
B
o LINE1-VREFO-R R293 4.7K_4
B
ADOGND
+1.5V [9,22,23,34] p LINE1-R C308 4.7U/6.3V_6 ADOGND *14V/38V/100P_4 *14V/38V/100P_4 ADOGND
+5V [20,22,23,37]
2
Cap need near AVDD1 and
.
n
+3V [4,5,7,9,11,12,13,17,19,20,22,24,25,27,28,35,37,39,40]
AVDD2 +3VPCU [6,8,19,21,22,25,30,31,32,37,39,40]
power source input
a
Codec PWR 5V(ADO) Codec PWR 1.5V(ADO)
u
Level shift
DIGITAL ANALOG
Mute(ADO)
DIGITAL ANALOG +1.5V L20 *0/short_6 +1.5VA +3V +1.5V
L16 HCB2012KF220T60/6A/22ohm_8 C331
+5V +5VA +AZA_VDD
Q
U18 1u/6.3V_4
3 4 R306
IN OUT
10K_4
2 R304
GND C298 C292 *1K_4
2
1 5 R280 *29.4K/F_4
SHDN SET *10u/6.3V_6 *0.1u/10V_4
*G923-330T1UF PD# D27 RB500V-40 PCH_AZ_CODEC_RST_R# PCH_AZ_CODEC_RST_R# 3 1 PCH_AZ_CODEC_RST#
C286 C287 R277
*10K/F_4 R308
A *0.1u/10V_4 *10u/6.3V_6 ADOGND
Internal Speaker *10K_4 D29 RB500V-40
AMP_MUTE# [19]
Q38
PJA138K
A
R549 *0/J_4
close pin3
ADOGND
R_SPK+ 35mil for each signal CN24
1
R_SPK-
L_SPK- 2
L_SPK+ 3 5
4 6
SPK_CONN_4P
C339 C341 C340 C338 Quanta Computer Inc.
1000P/50V_4 1000P/50V_4 1000P/50V_4 1000P/50V_4
PROJECT : ZYL/ZYLA
Place these EMI components next to codec
www.vinafix.vn
Codec ALC3225 1A

5 4 3 2 1
5 4 3 2 1
27
l
XTAL2 C111 15P/50V_4
LAN
1
2
Y9
25MHZ +-30PPM
a
VDD10
3
4
XTAL1 C112 12P/50V_4
R54 2.49K/F_4 RSET
10 mils TP38 +1.8V +3V
i
TP12
TP13
LANVCC
t
R72
D +3V [4,5,7,9,11,12,13,17,19,20,22,24,25,26,28,35,37,39,40] D
+1.8V [4,5,6,7,9,12,19,20,21,28,37] 10K_4
+3V_S5 [2,9,12,19,21,24,28,34,35,37,39,40]
2
32
31
30
29
28
27
26
25
U9
1 3 PCIE_REQ_LAN#_R
AVDD33
AVDD10
CKXTAL2
CKXTAL1
LED0
RSET
LED1/GPO
LED2(LED1)
[5] PCIE_CLKREQ3_LAN#
33 Q18
n
GND PJA138K
+3V
MDI_0+ 1 24 R374
MDI_0- MDIP0 REGOUT REGOUT +3V_S5
2 23 VDDREG/VDD33 1K/J_4
MDIN0 VDDREG(VDD33)
e
3 22
VDD10 MDI_1+ AVDD10(NC) DVDD10(NC) VDD10 PCIE_LAN_WAKE#_R
4 21 R68 *1K/J_4
MDI_1- 5 MDIP1 LANWAKEB 20 ISOLATEB
MDIN1 ISOLATEB
2
MDI_2+ 6 19
MDI_2- 7 MDIP2(NC) RTL8111GS-CG PERSTB 18 PCIE_RXN0_LAN_R C396 0.1u/10V_4
PLTRST# [12,13,19,24,25,28]
8 MDIN2(NC) HSON 17 PCIE_RXP0_LAN_R PCIE_RXN3_LAN [5]
VDD10 C399 0.1u/10V_4 R373
AVDD10 HSOP PCIE_RXP3_LAN [5]
*15K_4 Q17
3 1 PCIE_LAN_WAKE#_R
d
[12,19,28] WAKE_SRC_1
AVDD33(NC)
*DTC144EUA
REFCLK_N
MDIN3(NC)
MDIP3(NC)
REFCLK_P
CLKREQB
LANVCC R75 0_4
+3V_S5 LANVCC Consider VCC33 may be connected to Main
HSIN
HSIP
i
Power or chipset/bios's GPO, the pull-low
resistor R14 can be NC only when Main Power
40 mils (Iout=1A) 40 mils (Iout=1A) or chipset/bios's GPO can ensure to drive the
9
10
11
12
13
14
15
16
R378 *0/short_8 ISOLATEB pin to a voltage level < 0.8V at the
f
system state S1~S5.
MDI_3+ If the ISOLATEB pin can not be well-controlled to
C408 C407 MDI_3- a voltage level < 0.8V at S1~S5, the pull-low
0.1u/10V_4 10U/6.3V_6 LANVCC resistor R14 is needed to make sure the LAN
chip is well isolated.
CLK_PCIE_LANN [6]
n
C C
CLK_PCIE_LANP [6]
PCIE_TXN3_LAN [5]
PCIE_TXP3_LAN [5]
PCIE_REQ_LAN#_R
o
LANVCC VDDREG/VDD33
For RTL8111G(S) For RTL8111G(S)
RTL8111GS * Place 0.1uF CAP close to each * Place 1uF CAP close to each VDD10 pin-- 22 (reserve)
40 mils (Iout=1A) REGOUT (SWR mode) support VDD10 pin-- 3, 8, 22, 30 VDD10
C
R366 *0/short_8
40 mils (Iout=1A) 40 mils (Iout=1A)
C135 C110 C134 C106 40 mils (Iout=1A) C387 C388 L13 4.7uH
0.1u/10V_4 0.1u/10V_4 4.7U/6.3V_6 4.7U/6.3V_6 0.1u/10V_4 4.7U/6.3V_6

C126 C129 C391 C394 C397 C398 C395 C389
4.7U/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 1u/6.3V_4 0.1u/10V_4
a
For RTL8111GS
* Place 0.1uF/4.7uF CAP close to each Remove For Not Using SWR mode
VDD33 pin-- 11, 32 close to Pin23.
t
Tramsformer
B
RJ45 Connector B
n
U24 Need Check P/N and F/P
MDI_0+ LAN_MX0+
Layout:All termination CN10
1 TD1+ MX1+ 24
signal should have 30
a
MDI_0- 2 TD1- MX1- 23 LAN_MX0- mil trace
3 TCT1 MCT1 22 LAN_MCT0 R24 75/F_12 LANCT3
4 21 LAN_MCT1 R28 75/F_12 LAN_MX0+ 1

TCT2 MCT2 LAN_MX0-
u
2
MDI_1+ 5 20 LAN_MX1+ LAN_MX1+ 3
TD2+ MX2+ LAN_MX2+ 4
MDI_1- 6 19 LAN_MX1- LAN_MX2- 5 C19 *0.01U/50V/X7R_4
TD2- MX2- LAN_MX1- 6
LAN_MX3+ 7 9 C78 *0.1U/10V_4
LAN_MX3- 8 10
MDI_2+ 7 18 LAN_MX2+ R13 *short_8
TD3+ MX3+
MDI_2- 8 17 LAN_MX2-
TD3- MX3-
Q
9 16 LAN_MCT2 R40 75/F_12 LGND LGND
TCT3 MCT3
LAN_RJ45
10 15 LAN_MCT3 R43 75/F_12

TCT4 MCT4
MDI_3+ 11 14 LAN_MX3+
TD4+ MX4+
MDI_3- 12 13 LAN_MX3-
TD4- MX4-
A C22 A
0.01U/50V_4 C360
NS692417 10P/3KV/NPO_1808
LGND

PROJECT : ZYL/ZYLA
www.vinafix.vn
1A
LAN
5 4 3 2 1
5 4 3 2 1
l
WLAN
+3V_Mini1_VDD
+3V_Mini1_VDD
28
a
+3V_Mini1_VDD Unmount R509, R511 for
CN14 broadcom WLAN LED issue
R451 *0/short_4 BT_POWERON_C 51 52 R413
[19] BT_POWERON Reserved +3.3V
49 50
i
PLTRST# R452 *0/J_4 PLTRST#_C 47 Reserved GND 48 *4.7K/J_4
R453 *0/J_4 CLK_24M_DEBUG_C 45 Reserved +1.5V 46 WPAN_LED# R437 *0/J_4
[7] CLK_24M_DEBUG Reserved LED_WPAN# WLAN_LED#
43 44 TP44 +3V_S5 R137 *0/J_8
41 GND LED_WLAN# 42 WIMAX_LED# R438 *0/J_4 +3V_Mini1_VDD
t
39 +3.3Vaux LED_WWAN# 40
D
37 +3.3Vaux GND 38 R140 *0/short_8 +3V_Mini1_VDD D
GND USB_D+ USBP2+ [7] +3V
35 36
GND USB_D- USBP2- [7]
33 34
[5] PCIE_TXP2_WLAN 31 PETp0 GND 32 WLAN_CLK_SDATA C157 C437 C438 C162
[5] PCIE_TXN2_WLAN PETn0 SMB_DATA WLAN_CLK_SCLK
29 30 10U/6.3V_6 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
27 GND SMB_CLK 28
25 GND +1.5V 26 R439 *0/J_4 IOAC_PCIERST#
n
[5] PCIE_RXP2_WLAN PERp0 GND IOAC_PCIERST# [19]
[5] PCIE_RXN2_WLAN 23 24
21 PERn0 +3.3Vaux 22 PLTRST#_2 R440 *0/short_4
GND PERST# RF_EN PLTRST# [12,13,19,24,25,27]
19 20
UIM_C4 W_DISABLE# RF_EN [19]
17 18
UIM_C8 GND
15 16 LFRAME#_C R441 *0/short_4
GND UIM_VPP LFRAME# [7,19]
e
13 14 LAD3_C R442 *0/short_4
[6] CLK_PCIE_WLANP REFCLK+ UIM_RESET LAD2_C LAD3 [7,19]
11 12 R443 *0/short_4
[6] CLK_PCIE_WLANN REFCLK- UIM_CLK LAD1_C LAD2 [7,19]
9 10 R444 *0/short_4
CLK_PCIE_WLAN_REQ#_R 7 GND UIM_DATA 8 LAD0_C LAD1 [7,19]
R445 *0/short_4 +3V +3V_Mini1_VDD
CLKREQ# UIM_PWR LAD0 [7,19]
5 6
3 Reserved +1.5V 4
GND
GND
PCIE_WAKE#_R 1 Reserved GND 2
WAKE# +3.3V
d
WLAN CONN
53
54
*2N7002DW R134 R138
i
*4.7K/J_4 *4.7K/J_4
5
4 3 WLAN_CLK_SDATA
[7,11] SMB_RUN_DAT
f
+1.8V +3V_Mini1_VDD
+3V_Mini1_VDD 2
1 6 WLAN_CLK_SCLK
[7,11] SMB_RUN_CLK
R163 R162
10K_4 *4.7K/J_4 Q20
2
2
n
C C
1 3 CLK_PCIE_WLAN_REQ#_R 3 1 PCIE_WAKE#_R
[5] PCIE_CLKREQ2_WLAN# [12,19,27] WAKE_SRC_1
Q25 Q26
PJA138K *PJA138K R135 *0/J_4
R166 *0/J_4
o
R131 *0/J_4
+TPVDD [21,37]
+3V [4,5,7,9,11,12,13,17,19,20,22,24,25,26,27,35,37,39,40]
+1.8V [4,5,6,7,9,12,19,20,21,27,37]
+3V_S5 [2,9,12,19,21,24,27,34,35,37,39,40]
C
TPM (TPM)
a
TPM_VDD
t
+3V R159 *TPM@2.2_6
TPM_VDD
R107 *TPM_I@0_4 TPM_VDD C166 C425 C420 C158 C161

B B
R106 *TPM_N@0_4 TPM_VSB *TPM@10u/6.3V_6 *TPM@0.1U/10V_4 *TPM@0.1U/10V_4 *TPM@0.1U/10V_4 *TPM@0.1U/10V_4
n
24
19
10
U11
5
R146
VDD3
VDD2
VDD1
VSB
*TPM_N@10K_4 TPM_VSB
+TPVDD R95 **TPM_N@0_4
R104 *TPM_I@4.7K_4 R99 *TPM_N@0_4
a
+3V_S5
LAD3 17 7 R103 **TPM_I@4.7K_4
LAD2 20 LAD3 PP 6 R105 **TPM_I@20K_4 C142 C140
LAD2/SPI_IRQ GPX/GPIO2 TPM_VDD
LAD1 23 2
LAD0 26 LAD1/MOSI GPIO1 TP14 *TPM_N@10u/6.3V_6 *TPM_N@0.1U/10V_4
LFRAME# 22 LAD0/MISO 1 TP15
TPM_SERIRQ 27 LFRAME/SCS GPIO0/XOR_OUT 9 R101 *TPM_I@0_4 PLTRST#
21 SERIRQ GPIO3/BADD 8 R102 **TPM_N@10K_4
[7] CLK_TPM LCLK/SCLK TEST
u
C160 **TPM@10p/50V_4 15 3
16 CLKRUN/GPIO04 NC1 12 pin9 : 9655要要 reset , 9660 and Nuvoton NC pin
R145 *TPM_N@0_4 28 LRESET/SPI_RST NC2 13
[7,19] CLKRUN# LPCPD NC3 14
PLTRST# NC4
GND1
GND2
GND3
GND4
LPCPD#
TP17
*TPM_S@NPCT620/650_TSSOP28
4
11
18
25
Q
AL000650K00 : NPCT650AA0WX R158 **TPM_I@0_4
AL009655K01 : SNI SLB9655TT1.2 +1.8V
+1.8V +3V
PU at page 14 R165
**TPM_I@10K_4 U12
1 6
VCCA VCCB
A SOC_SERIRQ 3 4 TPM_SERIRQ A
[7,12] SOC_SERIRQ A B
2 5 R157
GND OE +1.8V
**TPM_I@10K_4
**TPM_I@G2129TL1U
GND
20140303:NPCT650 TPM doesn't need SERIRQ.
PROJECT : ZYL/ZYLA
www.vinafix.vn
1A
WiFi & BT & TPM
5 4 3 2 1
5 4 3 2 1
HOLE(OTH)
l
29
ia
HOLE20 HOLE22 HOLE29 HOLE13 HOLE18 HOLE12 HOLE26
D *H-C315D110P2 *HG-C315D110P2 *hg-tc315bc236d110p2 *HG-C315D110P2 *H-C315D110P2 *HG-C315D110P2-V5 *HG-C315D110P2 D
t
7 6 7 6 7 6 6 7 6
8 5 8 5 8 5 5 8 5
9 4 9 4 9 4 4 9 4
n
1
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
HOLE23 HOLE27 HOLE25 HOLE15
e
*HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2 *HG-C315D110P2
7 6 7 6 7 6 7 6
8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4
GPU nuts Mini card nuts
d
1
2
3
1
2
3
1
2
3
1
2
3
HOLE16 HOLE19 HOLE17 HOLE21
EV@H-C236D138P2 EV@H-C236D138P2 EV@H-TC236I138BC236D138P2 H-C217D61P2
i
HOLE14
*H-C110D110N
HOLE24 HOLE28
f
C
*HG-C315D110P2 *H-C315D110P2 C
1
7 6
8 5
9 4
1
n
1
2
3
o
CPU nuts
HOLE9 HOLE10 HOLE11
*H-TC256BC236D161P2 *H-TC256BC236D161P2 *H-TC256BC236D161P2 +VCC_CORE C212 *0.1U/10V_4 +VCC_GFX
C
C205 *1000p/50V_4
1
+VA_IACM C429 *0.1U/25V_4 +VIN
reserve for ESD
a
B B
C428 *1000p/50V_4
t
C522 0.1U/25V_4 +1.05V_GFX C258 0.1U/25V_4 +3V
C262 *0.1U/25V_4 +VIN
n
C47 *1000p/50V_4
C523 0.1U/25V_4 +VA_IACM C302 0.1U/25V_4 +5V_S5
a
C430 2.2n/50V_6 +VA_IACM
C524 0.1U/25V_4 +3V +3VPCU C285 0.1U/25V_4 +5V_S5
u
0.1U/25V_4 C143 +3VPCU
A A
Q
PROJECT : ZYL/ZYLA
1A
USB BOARD CONN
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
30
l
DFPJ06MR013-- 95W
a
DFPJ06MR007--- 45W
ti
D
ZE7 D
+VA_IACM
POWER_JACK 2013/07/24
dcjk-2dc2003-000111-3p-v PR109 change from
CS+0108F200 to CS+0208F200
+VA
Place this ZVS QM3016D +VAD +VIN
n
PJ9 close to INPUT PR105
PQ37
1 RC1206-R020
2 1 2 +VA_IACM 4 3
1
3
PC161 PC177 PC211 PC219
15
14
13
12
11
46
47
48
49
43
25
24
23
22
21
50
51
57
56
1
e
6
PD9 *0.1u/25V_4 *0.01U/50V_4 PU19 4.7U/25V_8 0.01U/50V_4
7
6
5
4
PC92 P4SMAJ20A
VSYS
VSYS
VSYS
VSYS
VSYS
VSYS
VSYS
VSYS
VSYS
VSYS
VSYS
VSYS
VSYS
VSYS
VSYS
VAD
VAD
VAD
VAD
VAD
0.1U/25V_4 31
2
PR107 PR108 NC
*0/short_4 *0/short_4 20
BATDIS_G PR156 10
*0/short_4 VBATT 19
PA VBATT CHG_VBATT
d
18
PC194 *1000P/50V_4 VBATT 17 2013/07/24
VBATT 16 PR122 change from
20140506 VBATT
PR188 PC212
CS+0108F200 to CS+0208F200
IACM 2 *2.2/J_6 *2200P/50V_4
Add noise filter cap
i
IACP 3 IACM 53 PL16 PR198 +BATCHG
PR55 IACP LX 52 6.8uH_7X7X3 RC1206-R020
560K/F_4 PC195 *1000P/50V_4 LX 27 CHG_LX 1 2
LX
37
ADDIV OZ8691LN-B LX
33
f
CHG_VAC 40 34
VAC LX 41 PC210
LX 0.47U/25V_6 PC214 PC223
PR178 MBDATA PR171 *0/short_4 8690_DATA 8 PR194 10U/25V_8 10U/25V_8
C 84.5K/F_4 MBCLK PR170 *0/short_4 8690_CLK 7 SDA 26 CHG_BST *0/short_6 CBST1 C
SCL BST PR59 PR60
32 CHG_VDDP
2 1 *0/short_4 *0/short_4
n
CHG_CEN 4 VDDP PD13
[19,35] MAINON CEN
COMP
GNDP
GNDP
GNDP
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
ACAV
1N4148WS
ICHM
ICHP
IOUT
PR166 *0_4 PC206
PD12 PR174 PR173 2.2U/10V_4
MEW316 20/F_6 100K/F_4
36
30
29
28
42
35
5
55
54
45
44
39
38
2 1
o
+VA
8690AGND
PD11 PC196
MEW316 0.47U/25V_6 8690AGND PR172 8690AGND ICHP
2 1 *0/short_4 ICHM
+BATCHG
[19] ACIN
PC191
Follow Command to change same as ZQK pin assignment
[37] +VAD_LD
C
PC42 0.047U/25V_4 PJ10
PR180 1000P/50V_4
100K/F_4 9 8
7 BATT_EN#
VAC= AC Adapter detection 8690AGND PR53
6
PR208 *0/short_4
8690AGND 10/F_4 PC229 PC231
5
ACAV = To indicate the adapter status. ICMNT [19] 4
SMC 100P/50V_4 0.1U/25V_4
8690AGND SMD
3
Pin ACAV goes high when Vvac > 2
8.7V/13.2V & Vvac > Vichm + 0.8V the PC41 PC40
TEMP_MBAT_C
10 1
a
47P/50V_4 0.01U/50V_4
Vvac = 8,7 or 13.2V threshold can be C114F3-108A1-L_Batt_Conn
chosen via SMbus commend PR210 PR211
8690AGND 100/J_4 100/J_4
t
B
Place this cap B
close to EC MBDATA [19]

MBCLK [19]
1
PR209
100/J_4 PC227 PC228
n
*47p/50V_4 *47p/50V_4
2
PR164 *0/short_6 [19] TEMP_MBAT
PD15 PD14
a
8690AGND PR202 PDZ5.6B PDZ5.6B
100K_4
u
+3VPCU
Q
A A

PROJECT : ZHJ
Charger (OZ8690ALN) 1A

5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
DC/DC +3VPCU/+5V_S5 +3VPCU [6,8,19,21,22,25,26,30,32,37,39,40]
31
l
+5V_S5 [24,25,33,34,35,36,37,39]
SYS_SHDN# [32,38] +3.3 Volt +/- 5%
LDO(MAX)=100mA
Countinue current:2A
Remove JP15 Peak current:2.7A
a
PR157 +3V_LDO +VIN
10K/F_4 PU16
SYS_SHDN# 6 1 OCP minimum:A
LDO VIN
2200P/50V_4
i
0.1U/25V_4
4.7U/25V_8
4.7U/25V_8
PC165
PC169
PC168
PC166
PC179 14 PC155
10U/6.3V_6 AGND 0.1U/25V_4
670AGND
t
D 3 2 D
NC PGND
PR49 5
10K/F_4 CLK
+3VPCU
PC164
10 NB670BST NB670BST_S +3VPCU
n
PR47 PR151
SYS_HWPG *0/short_4 NB670PG 4 BST *0/short_6 PL13
PGOOD
8 NB670SW
0.1U/25V_4 3.3uH_7X7X3
Remove JP13
SW 9
SW 15
*220uF/6.3V_6X4.2
e
PR43 SW 16 PR46
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
+VIN SW
PC149
PC151
PC156
PC159
*665K/F_4 *2.2/J_6 +
VL
PC142
PR158 PC152
11 *0/short_4
0.1u/10V_4
PR148 NB670ENLDO 12 VCC
ENLDO
*330K/F_4
d
PC160 PC34
1u/6.3V_4 *2200P/50V_4
PR147 *0/short_4
PR149
i
SYS_SHDN# *0/short_4
670AGND
NB670EN 13 7 NB670VOUT
[19,33,37,38] S5_ON EN VOUT
f
PR39 *0_4
PC158 PC180
*0.1u/10V_4 *0.1u/10V_4
C
unstuff NB670 C
o
6
PU21
NC VIN
1
Remove JP18
+VIN
n +5 Volt +/- 5%
Countinue current:5.7A
Peak current:7.5A
C 0.1U/25V_4
4.7U/25V_8
4.7U/25V_8
2200P/50V_4
1
PC217
PC216
PC215
PC218
OCP minimum: A
0.1U/25V_4
14
PC45
+
AGND PC239
671AGND
3 2 33U/25V_6x4.5
2
LP# PGND
5
PR183 NC
*0/short_4
a
+5V_S5
10 NB671BST NB671BST_S
PC44
Remove JP17
4 BST PR58 4.7_6 PL18
PGOOD 0.1U/25V_4 3.3uH_7X7X3
t
B 8 NB671SW B
SYS_HWPG NB671PG SW 9
PR184 *0/short_4 SW 15
220u/6.3V_6X4.2
SW 16 PR56
0.1u/10V_4
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
22U/6.3V_6
SW
PC238
PC234
PC235
PC232
PC241
PC240
*2.2/J_6 +
PR205
n
11 *0/short_4
VCC
PC224 PC43
Exchange AGND and PGND 5/7 10U/6.3V_4 *2200P/50V_4
PR57 *0/short_4
a
7 NB671VOUT
671AGND VOUT
PR61
S5_ON NB671EN 13 PR200 82K/F_4
*0/short_4 EN 12 NB671FB
u
FB
PC46
*0.1u/10V_4 PR199
NB671GQ-Z 11K/F_4
671AGND
Q
A A

PROJECT : ZHJ
3/5VS5 (NB670/NB669) 1A

5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
l
32
tia
D D
en
[12,19,37] +1.8VPCU
[6,8,19,21,22,25,26,30,31,37,39,40] +3VPCU
+1.8V Volt +/- 5%
d
Peak current:0.11A
i
OCP minimum:A
f
C C
PC185
n
PR163
+1.8VPCU
*2200P/50V_4 *2.2/J_6
PR54 *0/short_4 554PG_1.8V PU18
[19] HWPG_1.8V PL15 1uH_7X7X3
4 1 554LX_1.8V
o
PG NC 554FB_1.8V_S PR168 *0/short_4
9 2
+3VPCU PVIN LX PC199 PC186
removed PR161 and PR165
0.1u/10V_4
10 3
PC190
*22P/50V_4 PR179
PVIN LX 20K/F_4 22U/6.3V_6
7 554NC_1.8V PC197
R1
NC *68P/50V_4
PR167 554SVIN_1.8V 8 6 554FB_1.8V
SVIN FB
C
10_6 PR176
11 5 554EN_1.8V
10U/6.3V_6
0.01U/50V_4
GND EN
PC187
PC188
PR177
1u/6.3V_4
20K/F_4 R2
V0=0.6*(R1+R2)/R2
PC193
10K/F_4
RT8068AZQW PC198
0.1u/10V_4
a
SYS_SHDN# [31,38]
t
B B
an
A
5
Q u 4 3 2
Size
Date:
Document Number
+1.8VPCU
PROJECT : ZHJ
Thursday, July 10, 2014

1
Sheet 32 of 44
Rev
1A
A
www.vinafix.vn
5 4 3 2 1
l
33
+1.0V Volt +/- 5%
[9,37] +1.0V_S5
a
[24,25,31,34,35,36,37,39] +5V_S5 Peak current:3.2A
[2,9,12,19,21,24,27,28,34,35,37,39,40] +3V_S5 OCP minimum:A
ti
D D
PC202 PR181 +1.0V_S5
n
*2200P/50V_4 *2.2/J_6
554PG_1.0V
[19] HWPG_1.0V
PR189 *0/short_4 PU20
PL17 removed PR169 ,PR175 and PR182
4 1 554LX_1.0V
e
PG NC 1uH_7X7X3 554FB_1.0V_S PR196 *0/short_4
9 2
+5V_S5 PVIN LX PC222 PC208
0.1u/10V_4
10 3
PC207
*22P/50V_4 PR195
PVIN LX 6.65K/F_4 22U/6.3V_6
7 554NC_1.0V PC213
R1
NC
d
*68P/50V_4
PR185 554SVIN_1.0V 8 6 554FB_1.0V
SVIN FB
10_6
11 5 554EN_1.0V PR191 *0/short_4
0.01U/50V_4
10U/6.3V_6
i
GND EN
PC203
PC205
PR192
1u/6.3V_4
R2
V0=0.6*(R1+R2)/R2
PC209
10K/F_4
RT8068AZQW PC220
*0.1u/10V_4
f
C S5_ON [19,31,37,38] C
n
20140609:
Change PR192 from 10K to 9.31K Ohm
Co
ta
B B
an
A
5
Q u 4 3 2
Size
Date:
Document Number
+1.0V
PROJECT : ZHJ

1
Sheet 33 of 44
Rev
1A
A
www.vinafix.vn
5 4 3 2 1
l
34
ia
[2,9,12,19,21,24,27,28,35,37,39,40] +3V_S5
D [5,9] +1.05V D
t
[9,22,23,26] +1.5V
n
+1.05V Volt +/- 5%
+3V_S5 Countinue current:0.75A
PC254
Peak current:1A
e
4.7U/6.3V_6
OCP minimum:A
+1.05V
4
PU22
PR238
d
VIN
[19,37] HWPG_1.05V PL21
5 3 8002LX1.05V
PG LX
*0/short_4 2.2uH/1.85A_2.5X2X1.2
PR235 removed PR232 and PR234
i
PR233 10K_4 1 2 *0/short_4
[35,37] IMVP_PWRGD EN GND
PC251 PC250 PC252
FB
0.1u/10V_4
PC253
10U/6.3V_6
*10U/6.3V_6
f
APW8824
0.47uF/6.3V_4
6
C C
R1
PR236
11.3K/F_4
PR237
n
R2 15K/F_4
VO=(0.6(R1+R2)/R2)
o
+1.5V Volt +/- 5%
+3V_S5
Peak current:0.03A
C
PC137 PC130 3 5 OCP minimum:A
VIN NC
0.1u/10V_4
10U/6.3V_6
+1.5V
PU13
G9661 6
B VOUT B
a
HWPG_1.05V PR133 2
EN
20K/F_4
+5V_S5 4 8 PC129 PC127 PC135
PC128 VDD GND 0.1u/10V_4
10U/6.3V_6
*10U/6.3V_6
t
ADJ
0.1U/10V_4 1 9
PGOOD GND1
PC140
7
1u/6.3V_4
PR138
R1
n
91K/F_4
2013/08/19 Change PR161 from 88.7k to 91k for
[19,37] HWPG_1.5V HD audio codec issue
PR132 *0/short_4 R2 PR134
100K/F_4
a
VO=(0.8(R1+R2)/R2)
R2<120Kohm
u
A A
Q
PROJECT : ZHJ
+1.05V/1.5V 1A

5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
l
35
20130617 Change +1.05V to +1.0V
[6,9,37] +1.0V
+1.0V
Close to VR [8,9,29] +VCC_GFX
a
[20,29,30,31,36,37,38,39,40] +VIN
0.1u/10V_4
VR_SVID_ALERT# close to CPU
PC66
[24,25,31,33,34,36,37,39] +5V_S5
PR71 PR75 PR73
i
73.2/F_4 73.2/F_4 *73.2/F_4
VR_SVID_ALERT#
VR_SVID_DATA
t
D VR_SVID_CLK D
VR_SVID_DATA and VR_SVID_CLK close to VR
Remove JP19
n
PR214
2K/F_4
PC230
330p/50V_4
AXG
PR68 +VIN
2.2/F_6
95833_BOOTG
1
PR64 PC50
4.7u/25V_8
4.7u/25V_8
2200p/50V_4
0.1U/50V_6
1
e
PR207 21K/F_4 1000p/50V_4 PC60 +
PC56
PC55
PC236
PC237
PR219
2
+VCC_GFX 0.22u/25V_6
PC249
D1
D1
D1
2
PC49 1.78K/F_4 21K/F_4 95833_UGATEG 33U/25V_6x4.5
*330p/50V_4
PR62 PC52 PC58
PR186 1 G1 PL19
*10_4 0.47uH_7X7x3 DCR=4.2mOhm
d
499/F_4 470p/50V_4 220P/50V_4 95833_PHASEG S1/D2 9 95833_PHASEG 1 2
+VCC_GFX
[8] VCC_AXG_SENSE PR187 *0/short_4
2.2/J_6
4
PR190 *0/short_4 8 G2
PR66
3.65K/F_6
[8] VSS_AXG_SENSE
i
+
+VCC_GFX
330u/2V_7343
PC54 95833_ISUMNG 95833_LGATEG
Parallel *0.01U/50V_4 TDC : A
1/F_4
PC233
S2
0.1u/10V_4
S2
S2
10U/6.3V_8
PR193 PQ44
PC226
PC225
649/F_4
787/F_4
2200p/50V_6
*10_4 PEAK : 14A
PR63
PC59
f
7
6
5
AON6978(30V,20A,2.3W)
OCP : A
Width : mil
PC53
PR212
PR213
Close to the
95833_ISUMPG
GFX_CORE Load Line :
PR216
CPU side.
2.61K/F_4
PC48 -5.9mV/A for 2.xW SDP
PR206
4700P/25V_4
n
C *0.1u/25V_4 C
+5V_S5
95833_NTCG
95833_ISUMPG
95833_COMPG
33n/25V_4
47n/16V_4
PC57
PC51
10K/F_4_4250NTC
+1.0V 95833_ISUMNG
PR223
PR204
11K/F_4
*0/short_6
PR222
1/F_6
PR217
o
PC47
+3V_S5 +3V 0.1U/25V_4
PR220
33
32
31
30
29
28
*499/F_4
1u/10V_4
1U/16V_6
1.91K/F_4
1.91K/F_4
*100K/F_4
PAD
NTCG
ISUMPG
ISUMNG
RTNG
FBG
COMPG
Close to the Close with
PR78
PC61
PR215
PR218
PC242
PR67 *0_4 22 VR side. AXG inductor
[19] VRON VCCP
[19,30] MAINON 2 21
C
VR_ON VDD
PR69 *0/short_4
26 95833_BOOTG
15 BOOTG
[34,37] IMVP_PWRGD PGOOD
25 95833_UGATEG
PR65 UGATEG
TP25 27
PGOODG 24 95833_PHASEG
*0/short_4 PHASEG
a
[5,19] H_PROCHOT#
6
VR_HOT# LGATEG
23 95833_LGATEG Core
PU9
ISL95833HRTZ-T
Remove JP20
20
t
PC65 3 PWM2 PR76
SCLK +VIN
43p/50V_4 2.2/F_6
19 95833_LGATE1 95833_BOOT1
2200p/50V_4
LGATE1
4.7u/25V_8
4.7u/25V_8
0.1U/50V_6
1
4 PC63
PC67
PC76
ALERT#
2
B 95833_PHASE1 B
18 0.22u/25V_6
PC243
PC244
PHASE1
D1
D1
D1
2
n
95833_UGATE1
5 17 95833_UGATE1
SDA UGATE1
VR_SVID_CLK PR70 20/F_4 1 G1 PL20
[6] VR_SVID_CLK 95833_BOOT1
16 0.47uH_7X7x3 DCR=4.2mOhm
ISUMN
ISUMP
BOOT1
COMP
ISEN2
ISEN1
95833_PHASE1 S1/D2 9 95833_PHASE1 1 2 +VCC_CORE

NTC
RTN
PR72
FB
a
VR_SVID_ALERT#
PR79
[6] VR_SVID_ALERT#
4
8 G2
2.2/J_6
3.65K/F_6
8
10
11
12
13
14
*0/short_4
95833_LGATE1 +
+VCC_CORE
330u/2V_7343
VR_SVID_DATA PR74 16.9/F_4 PQ45
1/F_4
S2
95833_ISUMP
0.1u/10V_4
S2
S2
10U/6.3V_8
[6] VR_SVID_DATA 95833_COMP TDC : A
PC247
PC248
PC245
95833_NTC
2200p/50V_6
PR77
PC75
PEAK : 12A
7
6
5
u
*0/short_4
AON6978(30V,20A,2.3W)
OCP : A
PR227
PR228
Width : mil
4700P/25V_4
PR221 95833_ISUMP
+5V_S5 PR83 PC72 PC68 64.9K/F_4
PC70
2.61K/F_4
PC77
VCORE Load Line :
PR81
787/F_4
*0.1u/25V_4
499/F_4 470p/50V_4 220P/50V_4 -5.9mV/A for 2.xW SDP
PR80 PC74 Close to the
33n/25V_4
47n/16V_4
PR229 1.78K/F_4 21K/F_4 1000p/50V_4
PC69
PC73
VR side.
Q
649/F_4
PR82
PR225
10K/F_4_4250NTC
95833_ISUMN
PR230
11K/F_4
+VCC_CORE PR226 PC246
PR224
2K/F_4 330p/50V_4
PC78
95833_ISUMN 0.1U/25V_4
PC79
PR87 *330p/50V_4 Close with
Parallel
95833_NTC
95833_NTCG
*10_4 phase1 inductor

A A
[8] VCC_SENSE PR89 *0/short_4
[8] VSS_SENSE PR86 *0/short_4
PR231 PR84 PR203 PR201

PR88 470K_4 NTC 27.4K/F_4 470K_4 NTC 27.4K/F_4
*10_4 PC71
*0.01U/50V_4
PR85 PR197
Close to the
CPU side. 3.83K/F_4 3.83K/F_4
PROJECT : ZHJ
www.vinafix.vn
1A
+VCC_CORE/+VGFX (ISL95833)
5 4 3 2 1
1 2 3 4 5
36
[2,8,11,37]
[11]
+1.35VSUS
+VDDQ_VTT
ial
t
A A
[24,25,31,33,34,35,37,39] +5V_S5
( VTT / 0.75A )
+1.35VSUS
en Remove JP14
+VIN +1.35V +/- 5%
d
+VDDQ_VTT
Peak current:5A
2200P/50V_4
PU17 PC170
0.1U/25V_4
4.7U/25V_8
4.7U/25V_8
3 2
PC171
PC37
PC172
PC36
PC157
OCP minimum: A
i
VTT VLDOIN 0.1U/25V_4
5
1 *10U/6.3V_6
PC175 VTTSNS PQ38
10U/6.3V_6 AON7410
f
4
VTTGND 14 51216DRVH 4
DRVH
7 PC173 +1.35VSUS
B GND 15 51216VBST PR152 51216VBST_S B
( VDDQ / 0.375mA ) VBST Remove JP16
3
2
1
21 2.2/J_6
PR159 GND 0.1U/25V_4 PL14
n
5 13 51216SW 51216SW
[11] +VDDQ VTTREF SW
100/J_4
5
2.2uH_7X7X3
PC163 PC181 PC178 11 51216DRVL PR48
0.1U/10V_4 0.22u/10V_4 DRVL *2.2/J_6 + PC154
PR162 PC167
o
*0.1u/10V_4 10 4 *0/short_4 330u/2.5V_6X4.2 0.1U/10V_4
PR42 *0/short_4 51216S3 17 PGND
[19] SLP_SUS_ON S3
9 51216VDDQSNS PQ39 PC39
VDDQSNS
3
2
1
PR41 *0/short_4 51216S5 16 AON7752 *2200P/50V_4
[19] SUSON S5 +1.8VREF
PC162 PR150 *0/short_4 51216PG 20
[2] HWPG_1.35V PGOOD 6
VREF
C
PR44 51216TRIP 18
*0.1u/10V_4
TRIP PC184
Rds(on)=13mohm
120K/F_4
0.1U/10V_4 PR51
PR45 51216MODE19 10K/F_4
MODE
47K/F_4
8 51216REFIN
12 REFIN
+5V_S5 V5IN
a
PC176 APW8819QAI PC183 PR52
0.01U/25V_4 31.6K/F_4
1u/6.3V_4
t
C C
Fsw = 400KHz
an
D
1
Q u 2 3 4
Size
Date:
Document Number
PROJECT : ZHJ
DDR3 (APW8819)
5
Sheet 36 of 44
Rev
1A
D
www.vinafix.vn
5 4 3 2 1
+12VALW
37
[4,5,7,9,11,12,13,17,19,20,22,24,25,26,27,28,35,39,40] +3V +1.8V
l
[20,22,23,26] +5V
[6,7,9,12,21] +1.8V_S5
PR137 [9,33] +1.0V_S5 +1.8VPCU
+VIN +VIN PR40
PR35 1M_6
*22_6
PC133 22_8
[2,9,12,19,21,24,27,28,34,35,39,40] +3V_S5
a
PR136 0.1U/25V_4
[24,25,31,33,34,35,36,39] +5V_S5
3
G5934VIN 2 1 PR37
[30] +VAD_LD [2,8,11,36] +1.35VSUS
3
17 G5934VOUT
PC132 1M_4 PQ23 PC33
22_6 [4,5,6,7,9,12,19,20,21,27,28] +1.8V
3
19 G5934CN
18 G5934CP
1U/35V_6 PC131 2N7002K PQ24 0.1U/10V_4
i
[6,9,35] +1.0V
20130620 Reserved RC delay PC134
[9] +1.35V
2 AO3404
0.008A
0.1U/25V_4 PQ21 2
DCAP
[20,29,30,31,35,36,38,39,40] +VIN
0.47U/25V_6 DTC144EUA PQ22 2
[12,19,32] +1.8VPCU
3
PR141 20K/F_4 PR36 2N7002K PC31
t
20
16
[19,31,33,38] S5_ON [6,8,19,21,22,25,26,30,31,32,39,40] +3VPCU
D PR38 1M_4 2200p/50V_4 +1.8V D
1
PC141 HWPG_1.5V 2
VOUT
CP
D_CAP
VIN
CN
1
0.1U/10V_4
1
*0/short_4
1 15 PC30
1
ON1 PG PC35 PC38
0.1U/10V_4
n
0.1U/10V_4 *10U/6.3V_6
+12VALW
2 14 +1.35V
[19] TP_POWER_ON ON2 VSENSE
+VIN PR153 +1.35VSUS
e
+12VALW
PU15 PR50
1M_6
G5934RZ1U
3 13 22_8
[19,34] HWPG_1.5V ON3 REG
3
PR154 PQ41 PQ35 PC153
PC139 1M_4 2N7002K AO3404 0.1U/10V_4
1U/16V_4
d
HWPG_1.5V
0.034A
4 2 2 2
ON4 PQ40
7 G5934DISC3 PR144 +5V DTC144EUA PQ25 PC174
DISC3
3
*0/short_4 2N7002K 2200p/50V_4 +1.35V
PR160 PR155
1
+3V_S5 PR142 *0/short_4 G5934DISC1 5 6 G5934DISC2 PR145 +TPVDD
2 1M_4
DISC1 DISC2 *0/short_4 [19,34] HWPG_1.05V
DRIVER4
DRIVER3
DRIVER1
DRIVER2
*0/short_4
DISC4
f
PC182 PC145 PC144
GND
1
+3VPCU 0.1U/10V_4 *10U/6.3V_6
0.1U/10V_4
12
11
10
21
G5934DISC4
n
3
C C
PQ26 PC148
AO3404 2.2U/6.3V_4
EC_GPIO50_SUS 2
2.8A
HWPG1.8VD
+TPVDD
4
PC146
o
+3V 2200P/50V_4
1
3 PC143
2 5 +3VPCU 2200P/50V_4
1 PR143 PC64
PC136 PC138 *0/short_4 PC150 PC62 4.7U/10V_6
PC147 2200P/50V_4
*10U/6.3V_6
0.1U/10V_4 PQ34 0.1U/10V_4
*10U/6.3V_6
MDV1528Q
C
2014/04/18 :
+3V
Remove PC139/R148/R149 for +1.0VSX
Remove PC157/R340/R341/R346 for +1.35VSX
+1.0V_S5
1.43A
a
S5D PC192
0.1U/10V_4
t
MAIND +3VPCU +1.8VPCU
2.5A
4
PC22
+5V
B 2200P/50V_4
0.281A 20130717 no S0ix power plane B
3
3
3 PQ19 PC25 PQ20 PC28
2 5 AO3404 0.1U/10V_4 AO3404 0.1U/10V_4
n
+5V_S5 +1.35VSUS
1
2 2
PC201
0.1U/10V_4
PC204
PQ43 PC221 0.038A 0.056A
*10U/6.3V_6
MDV1528Q 0.1U/10V_4 +3V_S5 +1.8V_S5
a
PC29 PC32
1
1
2200P/50V_4 0.1U/10V_4
PC27 PC26 PC24 PC23 20140505

0.1U/10V_4 0.1U/10V_4
Change PQ14 from SOT23 to QFN3X3
*10U/6.3V_6
*10U/6.3V_6
+1.0V +12VALW
u
+1.0V_S5
+VIN
PR27 PR31
5
22_8 1M_6
3
PR30 PQ42 PC189
3
1M_4 PQ16 MDV1528Q 0.1U/10V_4
2N7002K 4
2
Q
+5V
2.1A
+VIN PQ15 2
DTC144EUA PQ14 PC200
3
2
1
3
2N7002K 2200p/50V_4 +1.0V
PR28 PR29
1
2 1M_4
1
PR32 PR34 [34,35] IMVP_PWRGD
*1M_4 *22_8 *0/short_4
PC19 PC21 PC20
1
3
A A
PQ18 0.1U/10V_4 *10U/6.3V_6
0.1U/10V_4
*2N7002K
2
3
PQ17
*2N7002K
PR33
1
2 *1M_4
PROJECT : ZHJ
1
Dis-charge IC (G5934) 1A
5 4
www.vinafix.vn 3 2
Date: Thursday, July 10, 2014
1
Sheet 37 of 44
5 4 3 2 1
38
al
+VIN
ti
D PD10 D
DA2J10100L
en
PR129
1M_6
1
SW9
PQ33 MISAKI_SW_H1.5
d
AO3409
2 1 2
3 4
i
5
3
6
f
3
S5_ON 2
[19,31,33,37] S5_ON
PQ32 PR130
Thermal protection
1
n
C DTC144EUA *0/short_6 C
Need fine tune VL VL
o
for thermal protect point SYS_SHDN# [31,32]
Note placement position

PR139 PC125 PR131
PR135 200K/F_4 0.1U/50V_6 200K_6
C
3
1.91K/F_4
8
PR146 2.469V 3
10K/F_4_4250NTC + 1 2
2
- PQ9
a
3
PU14A 2N7002K
4
AS393MTR-E1 PC126
1
t
0.1U/50V_6
S5_ON 2
PR140
B PQ36 200K/F_4 B
2N7002K
n
1
a
5
+ 7
6
note: PR173 change to 1.5k/F -
u
CS21502FB14 RES CHIP 1.5K +-1% 1/16W(0402) PU14B
AS393MTR-E1
20140702 Change PR135 from 1.5K/F_4 to 1.91K/F_4 for
thermal request
Q
For EC control thermal protection (output 3.3V)
A A

PROJECT : ZHJ
1A
Thermal / Hole
5 4
www.vinafix.vn 3
Date:
2
Thursday, July 10, 2014 Sheet
1
38 of 44
5 4 3 2 1
l
39
ia
+5V_S5
t
D D
PR23
*0/short_6 +VIN_GPU_CORE Remove JP11
+VIN
11/4 Change to 6.81K/F 11/4 Change to 12.4K/F
EV@2200p/50V_4
EV@0.1u/50V_6
EV@4.7u/25V_8
EV@4.7u/25V_8
EV@33U/25V_6x4.5
1
PR118
18 1658R-PVCC
+
PC105
PC107
PC15
PC16
PC104
PR12 EV@6.81K/F_4 PR17 EV@12.4K/F_4 EV@2.2/F_6
1
3V_MAIN_PWGD 1658R-VREF 1658R-BOOT1
PC11
2
e
EV@1u/10V_4
2
PC94 *EV@0.01U/25V_4 PC102
5
PR114 1 2 EV@0.22u/25V_6
EV@100K/F_4 PU11
PR103 1 1658R-BOOT1
PVCC
+VIN_GPU_CORE 1658R-OCS/CB 9 BOOT1 1658R-UGATE1 4 PQ29
PR97 *EV@1/F_4 OCS/CB 2 1658R-UGATE1 EV@AON6414AL
d
PR20 *EV@0_4 *EV@499K/F_4 UGATE1
[5] VGPU_EN
1
2
3
20 1658R-PHASE1 PL11
3V_MAIN_PWGD PR115 *0/short_4 1658R-EN 3 PHASE1 EV@0.24uH_7X7X3
[17,40] 3V_MAIN_PWGD EN 19 1658R-LGATE1 1658R-PHASE1
DCR=1.1m ohm
i
LGATE1 +VGPU_CORE
DGPU_PSI PR113 *0/short_4 1658R-PSI 4
[16] DGPU_PSI PSI
5
EV@UP1658RQKF PR26
EV@2.2/F_6
f
PWM-VID PR109 *0/short_4 1658R-VID 5 15 1658R-BOOT2 +
EV@330u/2V_7343
[16] PWM-VID VID BOOT2 1658R-LGATE1 4
EV@0.1u/10V_4
EV@10u/6.3V_8
14
PC113
PC114
PC109
1658R-UGATE2
1 2 1658R-VREF 8 UGATE2
1
2
3
PC96 EV@1u/10V_4 VREF 16 1658R-PHASE2 PQ31 PC17
C PHASE2 EV@AON6752 EV@1000p/50V_6 C
1658R-REFADJ 6 17 1658R-LGATE2 PR21 EV@10K_4
n
REFADJ LGATE2 1 2 +3V
+3V_S5 +3VPCU R1 7
REFIN 13
PR13
PR98
EV@7.5K/F_4
R2 PGOOD
1658R-PG PR116 *0/short_4
GPU_PWR_GD [17]
1658R-REFIN
*EV@0.01U/25V_4
12
PC98
EV@27K/F_4 1658R-COMP
COMP
o
EV@4700P/25V_4
GND
PR111 PR110 10
FB
FBRTN
1
+VIN_GPU_CORE
PC100
EV@10K_4 *EV@10K_4
1
PR100 PR117
11
21
DGPU_PSI
C EV@0_4
R3 EV@2.2/F_6
EV@22P/50V_4
2
1658R-FBRTN
PC97 1658R-BOOT2
2
1
EV@5600P/25V_4
PC101
EV@16K/F_6
EV@2.2n/50V_4
EV@0.1u/50V_6
EV@4.7u/25V_8
EV@4.7u/25V_8
PR19 1658R-FB PC103
PR112
PC108
PC106
PC14
PC13
2
5
C
*EV@0_4 EV@0.22u/25V_6
1658R-UGATE2 4
PR101
EV@6.2K/F_4
R4
1
2
3
Phase Number of Operation PQ28 PL10
*EV@22P/50V_4
1
EV@0_4
EV@0_4
EV@AON6414AL EV@0.24uH_7X7X3 DCR=1.1m ohm
PC99
PR104
PR102
PR106 1658R-PHASE2 +VGPU_CORE
*EV@5.1K/F_4
a
2
5
PR99
EV@1.74K/F_4
R5 PR25
+ +
EV@330u/2.5V_6X4.2
EV@2.2/F_6
EV@330u/2V_7343
3
1658R-LGATE2 4
EV@0.1u/10V_4
EV@10u/6.3V_8
B B
PC112
PC111
PC110
PC119
20131018 no need standby function
1
2
3
2 PQ30 PC18
PQ27 EV@AON6752 EV@1000p/50V_6
*EV@2N7002K
n
1
Standby PC95
1
*EV@1u/10V_4
Function
2
+VGPU_CORE
a
N15V-GM
PR122
EV@0_4
Component Value Config D
N15V-GM
u
PR121 EV@0_4
[13] VGA_VCCSENSE R1 27K +VGPU_CORE

[13] VGA_VSSSENSE
PR119 EV@0_4 Countinue current:33.5A
R2 7.5K Peak current:51.5A
PR120
Q
EV@0_4 OCP:75A
Parallel R3 0 FSW:300KHz
A L/L=0mV/A A
R4 6.2K
R5 1.74K
C 5.6nF Quanta Computer Inc.

PROJECT : ZQ0
1A
+VGPU_CORE (UP1658RQKF)
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
40
[13,14,15] +1.05V_GFX
l
[13,14,18] +1.5V_GFX
[13,16,17] +3V_GFX
a
+1.05V_GFX
PC122
TDC : 1.553A
20140421:
i
PR128 PEAK : 2.29A
Change 554PG_1.05V to Test PAD.
TP37 *EV@2200P/50V_4 *EV@2.2_6 +1.05V_GFX Width : 90mil
t
554PG_1.05V PU12
D D
Remove JP12 4 1 554LX_1.05V
PL12 EV@1uH_7X7X3
Remove JP14
PG NC 554FB_1.05V_S
9 2 PR123
+3V_S5 PVIN LX
EV@0.1u/10V_4
PC116 *0/short_4 PC124
PC123
10 3 *EV@22P/50V_4 PR126
n
PVIN LX EV@20K/F_4 EV@22U/6.3V_6
7 554NC_1.05V PC117
R1
NC *EV@68P/50V_4
PR127 554SVIN_1.05V 8 6 554FB_1.05V
SVIN FB
EV@10_6 PR124
11 5 554EN_1.05V
EV@0.01U/50V_4
EV@10U/6.3V_6
e
GND EN 20140529:
PC121
PC120
EV@1u/6.3V_4
EV@20K/F_4 R2 PR125
Change PR125 from 10K to 26.7K Ohm
PC118
EV@26.7K/F_4
EV@RT8068AZQW
PC115
EV@0.1u/10V_4
V0=0.6*(R1+R2)/R2
d
3V_MAIN_PWGD [17,39]
i
20140421:
Change Enable from 3V_MAIN_PWRGD
f
+VIN +3V_GFX +12VALW +3VPCU
n
C PR16 PR24 PR22 C
3
EV@1M_4 EV@22_8 EV@1M_4
dGPU_D 2
3
o
3
PR18 PQ13
EV@0_4 PR15 EV@AO3404 +3V_GFX
1
[12] DGPU_PWR_EN
2 EV@1M_4 2 2
PC12
+3V_GFX TDC : 0.17A
PEAK : 0.342A
1
PQ12 PQ11 *EV@2.2n/50V_4

PQ10 EV@2N7002K EV@2N7002K
Width : 20mil
1
PC10 PR14 EV@PDTC143TT
1
*EV@1u/10V_4 EV@100K_4
C
2
Remove JP9
1.5VGFX_VCC
1.5VGFX_VIN
+VIN
a
PC87 EV@2200p/50V_6
PC88 EV@4.7u/25V_8
PC89 EV@4.7u/25V_8
PC90 EV@4.7u/25V_8
PC91 EV@4.7u/25V_8
PR96
t
EV@100K/F_4
PR91 PR93
*EV@499K/F_4 EV@1/F_6
PR94 1.5VGFX_BST 1.5VGFX_BST1
B 20140609: B
[17] HWPG_1.5VGFX
*0/short_4 Change PL9 from 3.3uH to 2.2uH
n
+1.5V_GFX
10
1
PC80 +1.5V_GFX
PR239 EV@0.1u/50V_6 PL9
Remove JP10 1.5 Volt +/- 5%
BST
VIN
EV@200K/F_4 EV@2.2uH_7X7X3
1.5VGFX_EN 13 8 1.5VGFX_SW TDC : 3.24A
a
EN SW1
EV@0.1u/50V_6
EV@22u/6.3V_8
EV@22u/6.3V_8
EV@22u/6.3V_8
20140606: 1.5VGFX_PG 4 9 PEAK : 4.25A
modify +1.5V_GFX PG sequence PG SW2
Width : 170mil
3 15
PR92 LP# PU10 SW3 PR11
5 EV@NB671 16 *EV@4.7_6
[17] FBVDDQ_EN NC1 SW4
u
*0/short_4 6 7
NC2 VOUT
Change to 1.35V_GFX
*0/short_4
PR95
PC82 14 2
AGND PGND
PC86
PC85
PC84
PC83
*EV@0.1u/10V_4 PC9
VCC
PC93 *EV@680p/50V_6
FB
EV@0.1u/16V_4
11
12
Q
1.5VGFX_VCC
PC81
EV@1u/6.3V_4 1.5VGFX_FB
VREF=0.604V PR90
EV@82K/F_4
A 20140606: PR9 A
modify +1.5V_GFX PG sequence EV@64.9K/F_4
20140709 Change PR9 from 54.9K to 66.5K for EMI
request and +1.5V_GFX will Change to 1.35V_GFX
PR10

*0/short_6
PROJECT : ZQ0
1A
+1.5V_GFX/+1.05V_GFX/+3V_GFX
5 4
www.vinafix.vn
3 2
Date: Thursday, July 10, 2014 Sheet
1
40 of 44
5 4 3 2 1
Bay Trail-M Power On Timing without S0ix (G3 to S0)

41
l
+3V_RTC
a
SOC_RTEST#
SRT_CRST# >9ms
i
VIN
+3VPCU
t
D D
TP_POWER_ON
+TPVDD
n
SYS_HWPG
SYS_SHDN#
e
+1.8VPCU
HWPG_1.8V
d
S5_ON
+5V_S5
i
+3V_S5
+1.8V_S5
f
+1V_S5
HWPG_1.0V
RSMRST# >10us
n
C
(SOC_RSMRST#) C
SUS_PWRDOWNACK
(SUSWARN#_EC)
NBSWON#
(SOC_PWRBTN#)
o
SLP_S4# (SUSC#)
SLP_SUS_ON
+1.35VSUS
C
HWPG_1.35V
>26us
SLP_S3# (SUSB#)
SUS_ON
a
+VDDQ_VTT
+VDDQ
t
+SMDDR_VREF_DIMM
SOC_DRAM_PWROK
B B
MAINON
n
+1.05V
IMVP_PWRGD
+1.05VS
a
HWPG_1.05V
HWPG_EC
+5V
u
+3V
+1.8V
+1.35V
SDIO3_PWR_EN#
Q
+VSDIO
EC_PWROK
>99ms
SOC_VCCA_PWROK
(DRAM_CORE_PWROK)
A CORE_PWROK A
(PMC_CORE_PWROK)
Soft Straps Read
PCH SPI Interface
>1ms
PCH_SLP_S0#
(PCH_SLP_S0_N)
SOC_PLTRST# >60us
PLTRST#
G3 -> S5/S4 S5/S4 -> S3 S3 -> S0 PROJECT :ZYL
www.vinafix.vn
1A
Bay Trail-M Power Sequence
5 4 3 2 1
1 2 3 4 5 6 7 8
42
l
VGA power up sequence
a
+3VPCU
0ohm
PCH MOSFET +3V_GFX +3V_MAIN
i
(0805)
GPIO_S0_SC36 DGPU_PWR_EN
A A
t
MOSFET 3V_MAIN_PWGD
PG All 3.3V
t>0
NVVDD
n
PXE_VDD
+1.05V
+3V_S5 t>0
+1.05V_GFX FBVDDQ
e
S/W LDO N15x Power on sequance
APW8804QBI-TRG
3V_MAIN_PWGD Notes: -All 3.3V includes all rails powered at 3.3V
-PEX_VDD 1.05V inculdes all rails that are shared
HWPG_+1.05V_GFX
PG
id
PWM-VID (GPU GPIO11)
f
VIN
B
+VGPU_CORE B
3V_MAIN_PWGD VIN +1.5V_GFX
n
PWM
S/W LDO
VGPU_PWRGD NB671
0ohm FBVDDQ_EN HWPG_1.5VGFX
o
(0402) DGPU_PWROK
VGPU_PWRGD
a C C
t
GPIO_S0_SC37
n
VGA Reset
ua
PLTRST#
PEGX_RST#
PCH DGPU_HOLD_RST#
PEX_RST timing
Q
D D
I/O 3.3V
PEX_RST
Trise >= 1uS Tfail <=500nS Quanta Computer Inc.

PROJECT : ZYL
1A
GPU PWR CRL
1 2 3 4 5 6 7 8
www.vinafix.vn
5 4 3 2 1
ZYL POWER BLOCK DIAGRAM 43

S5_ON
ON1 PU16 Driver1
S5D
ial
t
D TP_POWER_ON D
ON2 DC/DC Driver2
HWPG_1.5V
ON3
G5934RZ1UDriver3 MAIND
HWPG1.8VD EC_GPIO50_SUS IMVP_PWRGD
n
ON4 Driver4
PQ38 PU13
PAGE37 N-MOSFET Switch LDO
AO3404 APW8824
+TPVDD +1.05V
e
PAGE37 PAGE34
S5D HWPG_1.05V TDC=P 1A/C 0.75A

PQ17 PU14
N-MOSFET LDO
d
AO3404 G9661
+3V_S5 +1.5V
PAGE37 PAGE34
i
TDC=0.038A HWPG1.8VD TDC=P 0.03A/C 0.023A
PQ16
f
N-MOSFET
MDV1528Q
+3V
PAGE37
C
TDC=P 32.7A/C 2A TDC=2.8A C
n
PU8 S5_ON IMVP_PWRGD
NB670L-LDO5
PQ14
PU6
+3VPCU N-MOSFET
DC/DC Switch LDO +1.0V_S5 AO3404 +1.0V
APW8804QBI-TRG
NB670LGQ-Z PAGE37
o
PAGE33 TDC=P 3.2A/C 2.4A TDC=0.64A
Adapter 60W SYS_SHDN#
19V*3.16A PAGE31
PU7
+VIN Switch LDO
C
APW8804QBI-TRG
Battery 2S2P PAGE32
4 cell 48Wh S5D HWPG_1.5V
PQ13 PQ11
N-MOSFET N-MOSFET
+1.8VPCU AO3404 +1.8V_S5 AO3404 +1.8V
a
PAGE37 PAGE37
TDC=P 0.11A/C 0.08A TDC=0.056A TDC=0.008A
PU10
t
S5_ON MAIND
PQ34
B +5V_S5 +5V B
DC/DC N-MOSFET
MDV1528Q
NB670LGQ-Z TDC=P 7.5A/C 5.7A TDC=2.5A
n
PAGE37
PAGE31 HWPG_1.05V
a
PQ28
SUSON N-MOSFET
PU9 S5 +1.35VSUS AO3404 +1.35V
PAGE37
DC/DC TDC=P 5A/C 3.7A TDC=0.034A
u
APW8819QAI
SLP_SUS_ON
S3 +VDDQ_VTT ( VTT / 0.525A )
PAGE36
+VDDQ ( VDDQ / 0.375mA )

MAINON
Q
PU12 +VCC_CORE TDP=12A
DC/DC
ISL95833HRTZ-T
A PAGE35 +VCC_GFX TDP=14A A

PROJECT : ZYL
1A
ZYL Power Block Diagram
www.vinafix.vn
5 4 3 2 1
5 4 3 2 1
l
Model Date CHANGE LIST
ZYL REV:A 1. FIRST RELEASED
a
Check CPU of P/N.
Change VRAM of P/N.
i
Check PJ6 for UMA or Dis- GVA.
t
D VGA Chip (Buy and Sell) D
AJ0N15V0T07
VR4GbIII9:
HYNIX Graphic DDRIII 900 4Gb H5TC4G63AFR-11C
n
AKD5PGWTW13 (B/S)
MICRON Graphic DDRIII 900 4Gb MT41J256M16HA-093G:E
AKD5PZSTL05 (B/S)
e
SAMSUNG Graphic DDRIII 900 4Gb K4W4G1646D-BC1A
AKD5PGWT504 (B/S)
CPU (Buy and Sell)
Intel BayTrial M
d
cpu n3530
VGA Chip (Buy and Sell)
i
AJ0N15V0T07
VRAM (Buy and Sell) VR2GbIII9

HYNIX Graphic DDRIII 900 2Gb H5TC2G63FFR-11C
AKD5MZDTW04 ; AKD5MZDTW05 (B/S)
f
MICRON Graphic DDRIII 900 2Gb MT41J128M16JT-093G:K
AKD5MGSTL15 ; AKD5MGSTL25 (B/S)
SAMSUNG Graphic DDRIII 900 2Gb K4W2G1646Q-BC1A

AKD5MGST511 ; AKD5MGST513 (B/S)
n
C C
5/27 1.PAGE.22 , modify SW10 pin3 connect to pin1 ,pin2 connect to pin4&pin5&pin6
2.PAGE.24 , modify CN16 & CN18 footprint from "USB-TARA4-9B1323-9P-SMT" to "UB2-UARDM-4K1926-4P-R"
ZYL REV:B 5/28 1.PAGE.25 , SWAP CN23 USB_CAR_N & USB_CAR_P
5/29 1.PAGE.40 , Change PR125 from 10K to 26.7K due to 1.05V_GFX output is incorrect
o
6/6 1.PAGE.6 , Change C458、C453 from 10P/50V to 12P/50V
2.PAGE.40 , Add PR239 to modify +1.5V_GFX PG sequence
6/9 1.PAGE.29 , change hole 18、hole20、hole28 footprint from "HG-C315D110P2" to "H-C315D110P2"
2.PAGE.19 , Add D37 D38 C521
3.PAGE.20 , change R66 R67 R69 R70 R71 R73 R74 R76 from 620ohm to 619 ohm
C
4.PAGE.29 , Change C430 from "CH22206K917" to "CH22206J911"
5.PAGE.22 , Change C464 C466 C468 C469 from "0.01u/16V_4" to "0.01u/25V_4"
6/10 1.PAGE.29 , reserve & mount C522 C523 C524 for ESD
2.PAGE.40 , Change PL9 from 3.3uH to 2.2uH for modified 1.5V_GFX efficiency.
6/11 1.PAGE.24 , delete R465 R468 R522 R530 & mount L28,L31 for EMI
a
6/13 1.PAGE.7 , PAGE.26,PAGE.28 , unmount R427,C310,R452,R453
2.PAGE.19 , mount D16 and change value form 14V/38V to 5V/30V
3.PAGE.26 , mount C338,C339,C340,C341 for EMI
t
6/25 1.PAGE.6 , Change G9、G10 footprint from "SOLDERJUMPER-2" to "RC0603-C"
ZYL REV:C 2.PAGE.26 , Change R311、R324、R565、R562、R550、R566 、L23、R13 from "0ohm" to "shortpad"
B B
6/27 1.PAGE.7 & 28 , Unmount R411 & Delete R147,R148,R149
n
2.PAGE.9 , Delete R180 for CPU +1.0V voltage
7/1 1.PAGE.24 & 25 , Change C279,C224,C414 from 100u/6.3V_3216 to 100U/6.3V_3528
7/2 1.PAGE.38 , Change PR135 from 1.5K/F_4 to 1.91K/F_4 for thermal request
a
7/9 1.PAGE.40 , Change PR9 from 54.9K to 64.9K for EMI request and +1.5V_GFX will Change to 1.35V_GFX

PROJECT : ZYL/ZYLA
Q u DOC NO. PROJECT MODEL : ZYL/ZYLA APPROVED BY: DATE:
A
www.vinafix.vn
1A
Change list PART NUMBER: DRAWING BY: REVISON:
5 4 3 2 1

Dent Ial: WWW - Vinafix.vn

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5 4 3 2 1

Intel Bay Trail-M Platform Block Diagram

SATA - ODD 32.768KHz

Date: Thursday, July 10, 2014 Sheet 1 of 44

Q43A Q43B EC_PWROK 2

PJ4N3KDW PJ4N3KDW 5 *0.1U/10V_4

GND HWPG_1.35V [36]

Date: Thursday, July 10, 2014 Sheet 2 of 44

Date: Thursday, July 10, 2014 Sheet 3 of 44

GND R144 *short_0/J_4 ICLK_SATA_TERMP BB10 AT7 PCIE_TXP2_WLAN_C C433 0.1U/10V_4

[12] SOC_KBC_SCI R133 *short_0/J_4 SATA_GP0 BA12 AP12 WLAN x1

Default NC No Pull High / Low

Default Pull Low 10K(GND) AC_PRESENT_NM

Quanta Computer Inc.

Date: Thursday, July 10, 2014 Sheet 5 of 44

+1.8V_S5 TP_INT# B18

RTC_X2 15P/50V_4 C476

SPI NOR FLASH +3V_RTC

6/25 Change G9、G10 footprint from

Quanta Computer Inc.

Port 1 is debug port K6

BH30 I2C_NFC_SOC_SDA I2C_5_SDA R417 *560_4

DATA- 910 ohm

Date: Thursday, July 10, 2014 Sheet 7 of 44

default 25 degree for detect temperature

Quanta Computer Inc.

C206 C211 REV = 1.15

A11 AC36 AG38 AH47 AT24 AY36 BF30 E8 K9 U3

VLV_M_D/BGA VLV_M_D/BGA VLV_M_D/BGA VLV_M_D/BGA VLV_M_D/BGA

Date: Thursday, July 10, 2014 Sheet 10 of 44

PC2100 DDR3 SDRAM SO-DIMM

C264 10U/6.3V_6 +3V Quanta Computer Inc.

Follow CHK list

Date: Thursday, July 10, 2014 Sheet 11 of 44

+1.8V *10K_4 R251 R224 *10K_4 +3V

[5] DGPU_HOLD_RST#_Q 1 3 DGPU_HOLD_RST# [13]

Date: Thursday, July 10, 2014 Sheet 12 of 44

*EV@200/F_4 R372 PEX_TSTCLK AF22 AG18 +3V

EV@2.49K/F_4 R59 PEX_TERMP AF25 PEX_TERMP

Quanta Computer Inc.

D18 FBA_WCK01 FBA_DQS_RN0 F19 VMA_RDQS0 C15 EV@22u/6.3V_8

C87 close ball H22 35mA FB_PLLAVDD GF117

Quanta Computer Inc.

bga595-nvidia-n13p-gv2-s-a2 COMMON GPIO18 C2

A close to balls one by one ball A

R362 *EV@40.2K/F_4 F6 MULTISTRAP_REF0_GND PGOOD D10

R341 R340 R19

N15V-GM Stuff 10K

E12 THERMDN GF117 GF119

GPIO8 VGA thrmtrip# => inform EC SMBus(VGA)

GPU_PEX_RST_HOLD# R347 *EV@10K/F_4 GFX_SDA 1 6

EV@2N7002K dGPU_OPP# = EC control

N15V-GM-B-A2 GeForce 820M 0x1140 AJ0N15V0T03

Q10 EV@1000p/50V_4 EV@DTC144EU

B C17 EV@MMBT3904-7-F PD at GPU power side B

Quanta Computer Inc.

FBA_CMD2 K1 A1 FBA_CMD2 K1 A1 FBA_CMD18 K1 A1 FBA_CMD18 K1 A1

VMA_DM1 E7 A9 VMA_DM2 E7 A9 VMA_DM5 E7 A9 VMA_DM7 E7 A9

Fermi : Change to 160 ohm C372 VMA_CLK1# C96 C386

C362 EV@10u/6.3V_6 C400 EV@10u/6.3V_6 +1.5V_GFX

+1.5V_GFX C364 EV@1u/10V_4 C128 EV@10u/6.3V_6 C20 EV@10u/6.3V_6

R190 *43/J_4 13 104 R203 10K_4

can be left un-connected.

+1.8V 10K_4 R251 R224 10K_4 +3V

EMC1412-1-ACZL-TR C423 0.01U/16V_4