Chapter 16

Problem Solutions
16.1
(a)
VTN =
Cax =

2e s N a
Cax

2 fp + VSB 2 fp

ax (3.9)(8.85 10 14 )
=
= 7.67 108
450 108
tax

2e s N a = 2 (1.6 10 19 ) (11.7 ) ( 8.85 1014 )( 8 1015 )

Then
5.15 108
VTN =
2(0.343) + VSB 2(0.343)
7.67 108
For VSB = 1 V :

1/ 2

= 5.15 10 8

VTN = 0.671 1.686 0.686 VTN = 0.316 V

For VSB = 1 V :
VTN = 0.671 2.686 0.686 VTN = 0.544 V
(b)
For VGS = 2.5 V, VDS = 5 V, transistor biased in the saturation region.
ID
For VSB
ID
For VSB

= K n (VGS VTN ) 2
= 0,
= 0.2(2.5 0.8) 2 = 0.578 mA
= 1,

I D = 0.2 ( 2.5 [ 0.8 + 0.316]) = 0.383 mA

2

For VSB = 2,
I D = 0.2 ( 2.5 [ 0.8 + 0.544]) = 0.267 mA
2

16.2
(a)
ID =

VDD vO
= K n 2(VGS VTN )vO vO2
RD

5 (0.1)
2
= K n 2 ( 5 0.8 )( 0.1) ( 0.1)
3

40 10
5
8 10 W
or K n = 1.476 104 A / V 2 =

2 L
W
So that = 3.69
L
b.
From Equation (16.10).

K n RD [VIt VTN ] + [VIt VTN ] VDD = 0

2

(0.1476)(40) [VIt 0.8] + [VIt 0.8] 5 = 0

2

1 (1) 2 + 4(0.1476)(40)(5)
2(0.1476)(40)
or [VIt 0.8] = 0.839
or [VIt 0.8] =

So that VIt = 1.64 V

P = I D (max) VDD

5 (0.1)
= 0.1225 mA
40
or P = 0.6125 mW

and I D (max) =

16.3
a.
From Equation (16.10), the transistor point is found from
K n RD (VIt VTN ) 2 + (VIt VTN ) VDD = 0
K n = 50 A / V 2 , RD = 20 k , VTN = 0.8 V
(0.05)(20)(VIt VTN ) 2 + (VIt VTN ) 5 = 0
1 1 + 4(0.05)(20)(5)
= 1.79 V So VIt = 2.59 V
2(0.05)(20)
V0t = 1.79 V
Output voltage for vI = 5 V is determined from Equation (16.12):
VIt VTN =

v0 = 5 (0.05)(20) 2(5 0.8)v0 v02

v02 9.4v0 + 5 = 0
So v0 =

b.

9.4 (9.4) 2 4(1)(5)

= 0.566 V
2(1)
For RD = 200 k,

1 1 + 4(0.05)(200)(5)
= 0.659 V So VIt = 1.46 V
2(0.05)(200)
V0t = 0.659 V

(VIt VTN ) =

v0 = 5 (0.05)(200) 2 ( 5 0.8 ) v0 v02

or 10v02 85v0 + 5 = 0
v0 =

16.4
(a)

85

(85 ) 4 (10 )( 5 )
= 0.0592 V
2 (10 )
2

P = IV

0.25 = I (33) I = 75.76 A

3.3 0.15
R=
R = 41.6 K
0.07576
2
k W
I = n (VGS VTN )
2
L

2
80 W
W
75.76 = ( 3.3 0.8 ) = 0.303
2 L
L
(b)
VDS (sat) = VGS VTN
V VDS (sat)
2
I D = K n (VGS VTN ) = DD
R
3.3 (VGS 0.8 )
0.08
2

( 0.303) (VGS 1.6VGS + 0.64 ) =

41.6
2
0.504 (VGS2 1.6VGS + 0.64 ) = 4.1 VGS
0.504VGS2 + 0.1936VGS 3.777 = 0
0.1936 0.03748 + 4(0.504)(3.777)
2(0.504)
= 2.55 V

VGS =
VGS

For 0.8 VGS 2.55 V

Transistor biased in saturation region
16.5
(a)
P = I VDD
0.25 = I (3.3) I = 75.76 A
For Sat Load
2
80 W
W
I = 75.76 = ( 3.3 0.15 0.8 ) = 0.343
2
L
L
L L
2
2
80
80 W
( 0.343)( 3.3 0.15 0.8 ) = I = 75.76 = 2 ( 2.5 0.8 )( 0.15 ) ( 0.15 )
2
2
L

D
W

= 3.89
L D

Eq 16.21

3.89
3.3 0.8 + 0.8 1 +

0.343

= 5.994
VIt =
4.3677
3.89
1+
0.343
0.8 VGS 1.372 V

16.6
(a)
From Equation (16.23)
KD
K
2
2
2 ( 3 0.5 )( 0.25 ) ( 0.25 ) = ( 3 0.25 0.5 ) D = 4.26

KL
KL

KD
K
2
2
2 ( 2.5 0.5 )( 0.25 ) ( 0.25 ) = ( 3 0.25 0.5 ) D = 5.4

KL
KL

(b)

iD = K L (VGSL VTNL ) = K L (VDD vO VTNL ) 2

2

(c)

0.080
2
=
(1)(3 0.25 0.5) iD = 0.203 mA
2
P = iD VDD = (0.203)(3) P = 0.608 mW

for both parts (a) and (b).

16.7
P = 0.4 mW = iD VDD = iD (3) iD = 0.1333 mA
iD = K L (VDD vO VTNL ) 2
2
0.080 W
W
0.1333 =
( 3 0.1 0.5 ) = ( 0.2304 )
2
L

L
L L
W
So = 0.579
L L

KD
2
2
2 ( 2.5 0.5 )( 0.1) ( 0.1) = ( 3 0.1 0.5 )

KL

KD
W
= 14.8 so that = 8.55
KL
L D

VIt =

3 0.5 + 0.5 1 + 14.8

1 + 14.8
or
VIt = 1.02 V , VOt = 0.52 V

16.8
We have
KD
2
2 ( vI VTND ) vO vO2 = (VDD vO VTNL )
KL

(W / L )D
2
2
2 (VDD VTN VTN )( 0.08VDD ) ( 0.08VDD ) = (VDD 0.08VDD VTN )

(W / L )L
(W / L )D
2
2
2
= ( 0.92 0.2 )VDD = 0.5184VDD
2 (VDD 2 ( 0.2 )VDD ) ( 0.08VDD ) 0.0064VDD

(W / L )L
(W / L )D
(W / L )D
= 5.4
[0.096] = 0.5184
(W / L )L
(W / L )L
16.9
VOH = VB VTN = Logic 1
So
(a)
VB = 4 V VOH
(b)
VB = 5 V VOH
(c)
VB = 6 V VOH
(d)
VB = 7 V VOH
For vI = VOH

= 3V
= 4V
= 5V
= 5 V ,since VDS = 0

K D 2 ( vI VT ) vO vO2 = K L [VB vO VT ]

Then
(a)

(1) 2 ( 3 1)VOL VOL2 = ( 0.4 ) [ 4 VOL 1]

(b)

(1) 2 ( 4 1)VOL V

(c)

(1) 2 ( 5 1)VOL VOL2 = ( 0.4 ) [6 VOL 1]

2
OL

VOL = 0.657 V

= ( 0.4 ) [5 VOL 1] VOL = 0.791 V

2

VOL = 0.935 V

(d)
Load in non-sat region
iDD = iOL
2
2
= ( 0.4 ) 2 ( 7 VOL 1)( 5 VOL ) ( 5 VOL )
(1) 2 ( 5 1) VOL VOL

2
2
8VOL VOL
= ( 0.4 ) 2 ( 6 VOL )( 5 VOL ) ( 25 10VOL + VOL
)
2
= ( 0.4 ) 2 ( 30 11VOL + VOL
) 25 + 10VOL VOL2
2
2

= ( 0.4 ) 60 22VOL + 2VOL

25 + 10VOL VOL
2
2
8VOL VOL
= 14 4.8VOL + 0.4VOL
2
1.4VOL
12.8VOL + 14 = 0

VOL =

12.8 163.84 4 (1.4 )(14 )

2 (1.4 )

VOL = 1.27V
For load
VDS ( sat ) = 7 1.27 1 = 4.73V
VDS = 5 1.27 = 3.73 non-sat

16.10
a.

For load VOt = VDD + VTNL = 5 2 = 3 V

KD
(VIt VTND ) = VTNL
KL
500
(VIt 0.8 ) = ( 2 )
100
VIt = 1.69 V
Load
VOt = 3 V

Driver: VOt = VIt VTND = 1.69 0.8 = 0.89 V

VIt = 1.69 V
Driver
V0t = 0.89 V
From Equation (16.29(b)):

b.
2
500
2(5 0.8)v0 v02 = ( 2 )
100
5v02 42v0 + 4 = 0
v0 =

c.

42

( 42 ) 4 ( 5)( 4 )
v0 = 0.0963 V
2 (5)
2

iD = K L ( VTNL ) = 100 ( 2 ) iD = 400 A

2

16.11
2
2
500

2 ( 3 0.5 )( 0.1) ( 0.1) = ( VTNL )

50
So

( VTNL )

= 4.9 VTNL = 2.21 V

16.12
(a)
P = iD VDD
150 = iD ( 3) iD = 50 A
iD = K L (VTNL ) 2
2
80 W
W
50 = ( 1) = 1.25
2
L
L
L L
2
KD
2
2 ( 3 0.5 )( 0.1) ( 0.1) = ( 1)

KL

K D (W / L ) D
W
=
= 2.04 = 2.55
K L (W / L ) L
L D
For the Load:
VOt = VDD + VTNL = 3 1 VOt = 2 V

2.04 (VIt 0.5 ) = ( 1) VIt = 1.20 V

For the Driver:

VOt = VIt VTND = 1.20 0.5 VOt = 0.70 V
VIt = 1.20 V

(b)

NM L = VIL VOLU
NM H = VOHU VIH

VIL = 0.5 +

( 1)
= 0.902 V
( 2.04 )(1 + 2.04 )

2 ( 1)
= 1.31 V
VIH = 0.5 +
3 ( 2.04 )
Then VOHU = ( 3 1) + ( 2.04 )( 0.902 0.5 ) = 2.82 V

VOLU =

(1.31 0.5)

= 0.405 V
2
NM L = 0.902 0.405 NM L = 0.497 V
NM H = 2.82 1.31 NM H = 1.51 V

16.13
a.
From Equation (16.29(b)):
2
W
W
2
2 ( 2.5 0.5 )( 0.05 ) ( 0.05 ) = [ ( 1)]
L
L
D
L
W

=1
L L

W
= 5.06
L D

Then

2
80
iD = (1) ( 1)
2
or iD = 40 A

b.

P = iD VDD = ( 40 )( 2.5 ) P = 100 W

16.14
a.

vI = 0.5 V iD = 0 P = 0
vI = 5 V, From Equation (16.12),

i.
ii.

v0 = 5 ( 0.1)( 20 ) 2 ( 5 1.5 ) v0 v02

2v02 15v0 + 5 = 0
v0 =

15

(15 ) 4 ( 2 )( 5 )
v0 = 0.35 V
2 ( 2)
2

5 0.35
= 0.2325 mA
20
P = iD VDD = ( 0.2325 )( 5 ) P = 1.16 mW

iD =

b.
ii.

vI = 0.25 V iD = 0 P = 0
i.
vI = 4.3 V, From Equation (16.23),

100 2 ( 4.3 0.7 ) v0 v02 = 10 [5 v0 0.7 ]

10 7.2v0 v02 = 18.49 8.6v0 + v02

Then
11v02 80.6v0 + 18.49 = 0
v0 =

80.6

(80.6 ) 4 (11)(18.49 )
v0 = 0.237 V
2 (11)
2

Then
iD = 10 [5 0.237 0.7 ] = 165 A
2

P = iD VDD = (165 )( 5 ) P = 825 W

c.

i.
ii.

vI = 0.03 V iD = 0 P = 0
vI = 5 V
2

iD = K L ( VTNL ) = (10 ) ( 2 ) = 40 A
2

P = iD VDD = ( 40 )( 5 ) P = 200 W

16.15
vo1 = 3.8V
Load & Driver in Sat, region, ML1, MD1

iDL = iDD
2
2
W
W
( vGSL VTNL ) = ( vGSD VTND )
L L
L D

(1) ( 5 vo1 0.8 ) = (10 )( vI 0.8 )

2

0.16 = 10 ( vI 0.8 )

vI = 0.9265V

Now MD2: Non Sat and ML2: Sat

iDL = iDD
2
W
W
2
( vGSL VTNL ) = 2 ( vo1 VTND ) vo 2 vo 2
L L
L D

(1)( 5 vo 2 0.8 )
( 4.2 vo 2 )

= (10 ) 2 ( 3.8 0.8 ) vo 2 vo22

= 10 6vo 2 vo22

17.64 8.4vo 2 + vo22 = 60vo 2 10vo22

11vo22 68.4vo 2 + 17.64 = 0
vo 2 =

68.4 4678.56 4 (11)(17.64 )

2 (11)

vo 2 = 0.270 V

16.16
a.
VIH

From Equation (16.41),

2 ( 2 )
= 0.8 +
VIH = 1.95 V = v01
3( 4)

M D 2 in non-saturation and M L 2 in saturation.

2
= K L ( VTNL )
K D 2 ( v01 VTND ) v02 v02
2
4 2 (1.95 0.8 ) v02 v02
= (1) ( 2 )

2
4v02
9.2v02 + 4 = 0

v02 =

9.2

( 9.2 ) 4 ( 4 )( 4 )
v02 = 0.582 V
2 ( 4)
2

Both M D1 and M L1 in saturation region. From Equation (16.28(b)).

4 ( vI 0.8 ) = ( 2 )

or vI = 1.8 V
b.

VIL = 0.8 +

( +2 )
= 1.25 V = v01
4 (1 + 4 )

M D 2 in saturation, M L 2 in non-saturation

2
2
K D [ vO1 VTND ] = K L 2 ( VTNL )( 5 vO 2 ) ( 5 vO 2 )

4 (1.25 0.8 ) = 2 ( 2 )( 5 v02 ) ( 5 v02 )

2

( 5 v02 )
5 v02 =

4 ( 5 v02 ) + 0.81 = 0

( 4)

4 (1)( 0.81)

2 (1)

= 0.214 V

so
v02 = 4.786 V
To find vI :
4 ( v01 0.8 ) = (1) ( ( 2 ) )
2

v01 0.8 = 1
v01 1.8 = V
VIH = 1.95 V, VIL = 1.25 V
c.

16.17
a.
i.
Neglecting the body effect,
v0 = VDD VTN
Assume VDD = 5 V, then v0 = 4.2 V
ii.

Taking the body effect into account: From Problem 16.1.

VTN = VTN 0 + 0.671 0.686 + VSB 0.686
and VSB = v0
Then
v0 = 5 0.8 + 0.671 0.686 + v0 0.686

v0 = 4.756 0.671 0.686 + v0

0.671 0.686 + v0 = 4.756 v0
0.450 ( 0.686 + v0 ) = 22.62 9.51v0 + v02
v02 9.96v0 + 22.3 = 0
v0 =

b.

9.96

( 9.96 )

4 ( 22.3)

v0 = 3.40 V
2
PSpice results similar to Figure 16.13(a).

16.18
Results similar to Figure 16.13(b).
16.19
a.
M X on, M Y cutoff.
From Equation (16.29(b)):
2
KD
2
2 ( 5 0.8 )( 0.2 ) ( 0.2 ) = ( 2 )

KL
or
b.

KD
= 2.44
KL

For v X = vY = .5 V

2 ( 2.44 ) 2 ( 5 0.8 ) v0 v02 = ( 2 )

4.88v02 41.0v0 + 4 = 0
v0 =

41

( 41) 4 ( 4.88 )( 4 )
2 ( 4.88 )
2

or
v0 = 0.0987 V
c.
2
80
iD = (1) ( 2 ) = 160 A
2

P = (160 )( 5 ) P = 800 W

for both parts (a) and (b).

16.20
(a)

Maximum value of vO in low state- when only one input is high, then,

2
KD
2
2 ( 3 0.5 )( 0.1) ( 0.1) = ( 1)

KL

KD
= 2.04
KL

(b)
P = iD VDD
0.1 = iD (3) iD = 33.3 A
2
k W
iD = n ( VTNL )
L
2
L
2
80 W
W
33.3 = ( 1) = 0.8325
2 L L
L L

W
Then = 1.70
L D

(c)

3 ( 2.04 ) 2 ( 3 0.5 ) vO vO2 = ( 1) vO = 0.0329 V

16.21
(a)

One driver in non-sat,

2
2

I D = K L ( VTNL ) = K D 2 (VGS VTND ) VDSD VDSD

2
KD
2

( 1) = K 2 ( 3.3 0.5 )( 0.1) ( 0.1)

L

KD
= 1.82
KL

(b)

P = VDD
0.1 = ( 3.3) I = 30.3 A
2
80 W
W
30.3 = I = ( 1) = 0.7575
2 L L
L L

W
= 1.38
L D

(c)
0.1
= 0.05 V
2
0.1
= 0.0333 V
Three inputs High, vo
3
0.1
= 0.025 V
Four inputs High, vo
4

Two inputs High, vo

(i)
(ii)

(iii)

16.22
a.
P = iD VDD
250 = iD ( 5 ) iD = 50
k' W
2
iD = n [ VTNL1 ]
2
L
ML1
2
60 W
50 = ( 2 )
2 L ML1
W
So that = 0.417
L ML1

KD
2
2 ( vI VTND ) vO vO2 = [ VTNL ]
KL
2
KD
2
2 ( 5 0.8 )( 0.15 ) ( 0.15 ) = ( 2 )

KL

or

KD
W
= 3.23
= 1.35
KL
L MD1

b.
For v X = vY = 0 v01 = 5 and v03 = 4.2
Then
2
K D 2 2 ( vO1 VTND ) vO 2 vO2 2 + K D 3 2 ( vO 3 VTND ) vO 2 vO2 2 = K L 2 [ VTNL 2 ]
K D 2 8, K D 3 8, K L 2 1
2
2
+ 8 2 ( 4.2 0.8 ) v02 v02
= (1) ( 2 )
8 2 ( 5 0.8 ) v02 v02
2
2
+ 54.4v02 8v02
=4
67.2v02 8v02
Then
16v02 121.6v0 + 4 = 0

v02 =

121.6

(121.6 ) 4 (16 )( 4 )
2 (16 )

So v02 = 0.0330 V
16.23

a.

We can write

2
2
= K y 2 ( vY vDSX VTN ) vDSY vDSY
= K L [VDD vO VTN ]
K x 2 ( v X VTN ) vDSX vDSX

where v0 = vDSX + vDSY

We have
v X = vY = 9.2 V , VDD = 10 V , VTN = 0.8 V
2
2
and vDSY
terms. Let v0 2vDSX . Then from the first and
As a good first approximation, neglect the vDSX
third terms in the above equation.

9 2 ( 9.2 0.8 ) vDSX (1)(10 2vDSX 0.8 )

(151.2 ) vDSX

84.64 36.8vDSX

So that vDSX = 0.450 V

From the first and second terms of the above equation.
9 2 ( 9.2 0.8 ) vDSX 9 2 ( 9.2 vDSX 0.8 ) vDSY

or
(16.8)( 0.45) = 2 ( 9.2 0.45 0.8) vDSY
which yields vDSY = 0.475 V
Then v0 = vDSX + vDSY = 0.450 + 0.475
or v0 = 0.925 V
We have vGSX = 9.2 V
and vGSY = 9.2 vDSX = 9.2 0.45
or vGSY = 8.75 V
b.
Since v0 is close to ground potential, the body effect will have minimal effect on the results. From
a PSpice analysis:
For part (a):
vDSX = 0.462 V, vDSY = 0.491 V, v0 = 0.9536 V, vGSX = 9.2 V, and vGSY = 8.738 V
For part (b):
vDSX = 0.441 V, vDSY = 0.475 V, v0 = 0.9154 V, vGSX = 9.2 V, and vGSY = 8.759 V
16.24
a.
We can write
2
2
2
= K y 2 ( vY vDSX VTNY ) vDSY vDSY
= K L [ VTNL ]
K x 2 ( v X VTNX ) vDSX vDSX
2
From the first and third terms, (neglect vDSX
),

4 2 ( 5 0.8 ) vDSX = (1) ( 1.5 )

or vDSX = 0.067 V
2
From the second and third terms, (neglect vDSY
),

4 2 ( 5 0.067 0.8 ) vDSY = (1) ( 1.5 )

or vDSY = 0.068 V
Now
vGSX = 5, vGSY = 5 0.067 vGSY = 4.933 V
and v0 = vDSX + vDSY v0 = 0.135 V
Since v0 is close to ground potential, the body-effect has little effect on the results.
16.25

(a)

0.2
= 0.05 V
4
2

VDSD

We have VDS of each driver

K L [ VTNL ] = K D 2 (VGSD VTN ) VDSD

2

2
KD
2

( 1) = K 2 ( 3.3 0.4 )( 0.05 ) ( 0.05 )

L

KD
= 3.478
KL

(b)
P = I VDD
0.15 = I ( 3.3) I = 45.45 A
2
80 W
W
45.45 = ( 1) = 1.14
2 L L
L L

W
= 3.95
L D

16.26
Complement of (B AND C) OR A ( B C ) + A
16.27
Considering a truth table, we find
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
0
which shows that the circuit performs the exclusive-OR function.
16.28
( A + B )(C + D)
16.29
(a)

Carry-out = A ( B + C ) + B C

(b)

For vO1 = Low = 0.2 V

2
KD
2
2 ( 5 0.8 )( 0.2 ) ( 0.2 ) = ( 1.5 )

KL

W
W
For = 1, then = 1.37
L L
L D
W
So, for M 6 : = 1.37
L 6

To achieve the required composite conduction parameter,

W
For M 1 M 5 : = 2.74
L 1 5
16.30

AE: VDS 0.075

2
2
W
(1) ( 1) 2 ( 3.3 0.4 )( 0.075 ) ( 0.075 )

L
D
W
W
W
W
W
= = 2.33 = = = 4.66
L A L E
L B L C L D

16.31
Not given

16.32
a.

From Equation (16.43),

5 0.8 + 0.8
vI = VIt =
= VIt = 2.5 V
1+1
p channel, V0 Pt = 2.5 ( 0.8 ) V0 Pt = 3.3 V
n channel, V0 Nt = 2.5 0.8 V0 Nt = 1.7 V

For vI = 2 V, NMOS in saturation and PMOS in nonsaturation. From Equation (16.49),

2
= 2 ( 5 2 0.8 )( 5 v0 ) ( 5 v0 )

1.44 = 4.4(5 v0 ) (5 v0 ) 2

( 2 0.8)

So ( 5 v0 ) 4.4 ( 5 v0 ) + 1.44 = 0
2

( 5 v0 ) =

4.4

( 4.4 )

4 (1)(1.44 )

2
or
5 v0 = 0.356 v0 = 4.64 V

By symmetry, for vI = 3 V, v0 = 0.356 V

16.33
(a)

80
K n = ( 2 ) = 80 A / V 2
2
40
K p = ( 4 ) = 80 A / V 2
2

VDD + VTP +

(i)

VIt =

Kn
VTN
Kp
Kn
Kp

1+

3.3 0.4 + (1)(0.4)

1+1

VIt = 1.65 V

PMOS:
VOt = VIt VTP = 1.65 ( 0.4 ) VOt = 2.05 V
NMOS:
VOt = VIt VTN = 1.65 ( 0.4 ) VOt = 1.25 V
(iii) For vO = 0.4 V : NMOS: Non-sat: PMOS:Sat
2
= K p [VSGP + VTP ]
K n 2 (VGSN VTN )VDS VDS

2 ( vI 0.4 )( 0.4 ) ( 0.4 ) = ( 3.3 vI 0.4 ) vI = 1.89 V

2

For vO = 2.9 V , By symmetry

vI = 1.65 (1.89 1.65 ) vI = 1.41 V

(b)

80
K n = ( 2 ) = 80 A/V 2
2
40
K p = ( 2 ) = 40 A/V 2
2

80
( 0.4 )
40
VIt = 1.44 V
80
1+
40

3.3 0.4 +

VIt =

(i)

PMOS:
VOt = 1.44 ( 0.4 ) VOt = 1.84 V
NMOS:
VOt = 1.44 0.4 VOt = 1.04 V
For vO = 0.4 V

(iii)

= 40 3.3 vI 0.4]2 vI = 1.62 V

( )[
For vO = 2.9 V : NMOS: Sat, PMOS: Non-sat

(80 ) 2 ( vI 0.4 )( 0.4 ) ( 0.4 )

(80 ) [vI 0.4]

16.34
(a)
(i)

2
= ( 40 ) 2 ( 3.3 vI 0.4 )( 0.4 ) ( 0.4 ) vI = 1.18 V

From Eq. (16.43), switching voltage

VDD + VTP +

vI t =

(ii)

Kn
VTN
Kp

Kn
1+
Kp

2 ( 4)
( 0.4 ) 3.2266
12
=
vIt = 1.776 V
1.8165
2 ( 4)
1+
12

3.3 + ( 0.4 ) +

v0 = 3.1 V , PMOS, non-sat; NMOS, sat

k p W
2
kn W
2
2 (VSG + VTP ) VSD VSD = (VGS VTN )
L
L
2
2
n
p
2
2
40
80
(12 ) 2 ( 3.3 vI 0.4 )( 3.3 3.1) ( 3.3 3.1) = ( 4 ) [ vI 0.4]
2
2
12 [1.16 0.4vI 0.04] = 8 vI2 0.8vI + 0.16
8vI2 1.6vI 12.16 = 0
vI =

(iii)

1.6 2.56 + 4 ( 8 ) (12.16 )

2 (8)

vI = 1.337 V

v0 = 0.2 V PMOS: sat, NMOS, non-sat.

2
2
40
80
(12 ) [3.3 vI 0.4] = ( 4 ) 2 ( vI 0.4 )( 0.2 ) ( 0.2 )
2
2

12 8.41 5.8vI + vI2 = 8 [ 0.4vI 0.2]

12vI2 72.8vI + 102.52 = 0
vI =

72.8 5299.84 4 (12 )(102.52 )

vI = 2.222 V
(b)

2 (12 )

vIt =

(i)

2 ( 6)
( 0.4 ) 3.5928
4
=
2.732
2 (6)
1+
4

3.3 + ( 0.4 ) +

vIt = 1.315 V

(ii)
From (a), (ii)
4 [1.16 0.4vI 0.04] = 12 vI2 0.8vI + 0.16
12vI2 8vI 2.56 = 0
vI =

8 64 + 4 (12 )( 2.56 )
2 (12 )

vI = 0.903 V

(iii)
From (a), (iii)

4 8.41 5.8vI + vI2 = 12 [ 0.4vI 0.2]

4vI2 28vI + 36.04 = 0
vI =

28 784 4 ( 4 )( 36.04 )
2 ( 4)

16.35
a.

vI = 1.70 V

For vO1 = 0.6 < VTN vO 2 = 5 V

N1 in nonsaturation and P1 in saturation. From Equation (16.45),

2 ( vI 0.8 )( 0.6 ) ( 0.6 )2 = [5 vI 0.8]2

1.2vI 1.32 = 17.64 8.4vI + vI2

or
vI2 9.6vI + 18.96 = 0

vI =

9.6

( 9.6 )

4 (1)(18.96 )
2

or
vI = 2.78 V
V0 Nt v02 V0 Pt
b.
From symmetry, VIt = 2.5 V
V0 Pt = 2.5 + 0.8 = 3.3 V
and V0 Nt = 2.5 0.8 = 1.7 V
So 1.7 v02 3.3 V

16.36
a.
V0 Nt v01 V0 Pt
By symmetry, VIt = 2.5 V
V0 Pt = 2.5 + 0.8 = 3.3 V
and V0 Nt = 2.5 0.8 = 1.7 V
So 1.7 v01 3.3 V
b.

For vO 2 = 0.6 < VTN vO 3 = 5 V

N 2 in nonsaturation and P2 in saturation. From Equation (16.57),

 2 ( vI 2 0.8 )( 0.6 ) ( 0.6 )2 = [5 vI 2 0.8]2

1.2vI 2 1.32 = 17.64 8.4vI 2 + vI22

or
vI22 9.6vI 2 + 18.96 = 0
So vI 2 = v01 = 2.78 V

For v01 = 2.78, both N1 and P1 in saturation. Then

vI = 2.5 V
16.37
a.
iPeak = K n ( vI VTN )
iPeak = 0.1 ( 2.5 0.8 ) = 0.538 ( mA )

1/ 2

b.

iPeak = 0.1 (1.65 0.8 ) = 0.269 ( mA )

1/ 2

16.38
(a)

50
K n = ( 2 ) = 50 A / V 2
2
25
K p = ( 4 ) = 50 A / V 2
2

I D , peak = K n ( v1 VTN ) = 50 ( 2.5 0.8 )

2

or I D , peak = 144.5 A
(b)

K n = 50 A / V 2 , K p = 25 A/V 2

From Equation (16.55),

50
5 0.8 +
(0.8)
25
vIt =
= 2.21 V
50
1+
25
Then
I D , peak = K n (VIt VTN ) 2 = 50 ( 2.21 0.8 )

or I D , peak = 99.4 A
16.39

(a)

Switching Voltage, Eq. (16.43)

2 ( 4)
( 0.4 )
8
vIt =
= 1.65 V = vIt
2 ( 4)
1+
8
80
2

iD, peak = ( 4 )(1.65 0.4 ) iD , peak = 250 A
2
(b)
3.3 0.4 +

2 ( 4)
( 0.4 )
4
= 1.436 V = vIt
vIt =
2 ( 4)
1+
4
2
80
iD , peak = ( 4 )(1.436 0.4 ) iD , peak = 172 A
2
(c)
3.3 0.4 +

2 ( 4)
( 0.4 )
12
vIt =
vIt = 1.776 V
2 ( 4)
1+
12
2
80
iD , peak = ( 4 )(1.776 0.4 ) iD , peak = 303 A
2
3.3 0.4 +

16.40
2
a. P = fCLVDD
For VDD = 5 V, P = (10 106 )(0.2 1012 )(5) 2
or P = 50 W
For VDD = 15 V, P = (10 106 )(0.2 1012 )(15) 2
or P = 450 W
b.
For VDD = 5 V, P = (10 106 )(0.2 1012 )(5) 2
or P = 50 W
16.41
(a)

2
P = fCLVDD
= (150 106 )( 0.4 1012 ) ( 5 ) = 1.5 10 3 W / inverter
2

Total power: PT = ( 2 106 )(1.5 103 ) PT = 3000 W !!!!

(b)

For f = 300 MHz

2
1.5 10 = ( 300 106 )( 0.4 1012 ) VDD
VDD = 3.54 V

16.42
3
= 3 107 W
7
10

(a)

P=

(b)

2
P = fCLVDD
CL =

P
2
fVDD

(i)

CL =

(ii)

CL =

(iii)

CL =

3 107

( 5 10 ) ( 5)
6

CL = 0.0024 pF

3 107

CL = 0.00551pF

CL = 0.0267 pF

( 5 10 ) ( 3.3)
6

3 107

( 5 10 ) (1.5)
6

16.43
10
= 2 106 W
5 106
P
CL =
2
fVDD
P=

(a)
(b)

2 106

CL = 0.01 pF

(i)

CL =

(ii)

CL =

(iii)

CL =

16.44
(a)

For vI VDD , NMOS in nonsaturation

(8 10 ) ( 5)
6

2 106

CL = 0.023 pF

CL = 0.111 pF

(8 10 ) ( 3.3)
6

2 106

(8 10 ) (1.5)
6

2
and vDS 0
iD = K n 2 ( vI VTN ) vDS vDS

So

di
1
= D K n 2 (VDD VTN )
rds dvDS

Or
rds =

1
kn W
2 L 2 (VDD VTN )
n

or
1

rds =

W
kn
L
For vI 0,

(VDD VTN )
n
PMOS in nonsaturation

iD = K p 2 (VDD vI + VTP ) vSD vSD

and vSD 0 for vI 0.

So
k p W
di
1
= D 2 (VDD + VTP )
rsd dvSD 2 L p
or
rsd =

1
1
k p

Lp

(VDD + VTP )

W
W
(b) For = 2, = 4
L n
L p
rds =
rsd =

1
r = 2.38 k
50
2
( )( )( 5 0.8) ds
1

( 25 )( 4 )( 5 0.8 )

rsd = 2.38 k

W
For = 2,.
L p
rsd =

1
r = 4.76 k
25
2
( )( )( 5 0.8 ) sd

Now, for NMOS:

vds = id rds or id =

vds
0.5
=
id = 0.21 mA
rds 2.38

For PMOS:
For rsd = 2.38 k ,
id =

vsd
0.5
=
id = 0.21 mA
rsd 2.38

For rsd = 4.76 k ,

id =

vsd
0.5
=
id = 0.105 mA
rsd 4.76

16.45
From Equation (16.63)
3
VIL = 1.5 + (10 1.5 1.5 ) VIL = 4.125 V
8
and Equation (16.62)
1
V0 HU = 2 ( 4.125 ) + 10 1.5 + 1.5
2
or V0 HU = 9.125 V
From Equation (16.69)
5
VIH = 1.5 + (10 1.5 1.5 ) VIH = 5.875 V
8
and Equation (16.68)
1
V0 LU = 2 ( 5.875 ) 10 1.5 + 1.5
2
or V0 LU = 0.875 V
Now
NM L = VIL V0 LU = 4.125 0.875 NM L = 3.25 V
NM H = V0 HU VTH = 9.125 5.875 NM H = 3.25 V

16.46
From Equation (16.71)

VIL = 1.5 +

100

50 1 = 1.5 + 7 2 ( 0.632 ) 1
2

100 + 3

50

(10 1.5 1.5 )

100
1

50

or
VIL = 3.348 V
From Equation (16.70)
1 100

100
V0 HU = 1 +
( 3.348 ) + 10
(1.5 ) + 1.5
2
50
50

or V0 HU = 9.272 V
From Equation (16.77)

VIH

100
2

(10 1.5 1.5 ) 50

= 1.5 +
1 = 1.5 + 7 [1.51 1]

100 100
1 3
+1

50
50

or
VIH = 5.07 V
From Equation (16.76)
100
100
( 5.07 ) 1 + 10 (1.5 ) + 1.5
50

50
V0 LU =
100
2

50
or V0 LU = 0.9275 V
Now NM L = VIL V0 LU = 3.348 0.9275
or NM L = 2.42 V
NM H = V0 HU VIH = 9.272 5.07
or NM H = 4.20 V

16.47
(a)
Kn = KP
3
(VDD + VTP VTN )
8
3
= 0.4 + ( 3.3 0.4 0.4 ) VIL = 1.3375 V
8
1
VOHu = {2 (1.3375 ) + 3.3 0.4 + 0.4}
2
VOHu = 2.9875 V

VIL = VTN +

VIH = 0.4 +

5
( 3.3 0.4 0.4 ) VIH = 1.9625 V
8

1
{2 (1.9625) 3.3 0.4 + 0.4}
2
= 0.3125 V

VOLu =
VOLu

NM H = VOHu VIH = 2.9875 1.9625 NM H = 1.025 V

NM L = VIL VOLu = 1.3375 0.3125 NM L = 1.025 V

(b)

2 ( 4)

( 3.3 0.4 0.4 )

2.5
12
VIL = 0.4 +
2
1 = 0.4 +
( 0.147 )
2
4

( ) +3
( 2 )( 4 )
( 0.333)
1

12

12

VIL = 1.505 V
VOHu =

1
2 ( 4)
1 ( 2 )( 4 )
(1.505 ) + 3.3
( 0.4 ) + 0.4 = {2.5083 + 3.3 0.2667 + 0.4}
1 +
2
12
2
12

VOHu = 2.9708 V

2 ( 4)
2

( 3.3 0.4 0.4 ) 12

2.5
1 = 0.4 +
VIH = 0.4 +
[ 0.2302] VIH = 2.1282 V

0.333)
2 ( 4)
(
2 )( 4 )
(
1 3
+1

12
12

2 ( 4)
2 ( 4)
( 2.1282 ) 1 +
3.3
( 0.4 ) + 0.4
12
12
3.547 3.3 0.2667 + 0.4

VOLu =
=
VOLu = 0.2853 V
1.333
2 ( 4)
2

12
NM H = VOHu VIH = 2.9708 2.1282 NM H = 0.8426 V
NM L = VIL VOLu = 1.505 0.2853 NM L = 1.22 V

16.48
a.
v A = vB = 5 V
N1 and N 2 on, so vDS1 vDS 2 0 V
P1 and P2 off
So we have a P3 N 3 CMOS inverter. By symmetry, vC = 2.5 V (Transition Point).
b.
For v A = vB = vC vI
Want K n ,eff = K p ,eff
kn W
k 3W
= P

2 3L n 2 L P
With kn = 2k P , then
2 1 W
1 W
= 3
2 3 L n 2 L P
9 W
W
Or =
L
n 2 L P

c.

We have
k W 2k p 9 W
Kn = n =

2 L n 2 2 L p
k p W
Kp =
2 L p
Then from Equation (16.55)

Kn
( 0.8 )
Kp

5 + ( 0.8 ) +
VIt =
1+

Kn
Kp

Now
Kn
9
= ( 2) = 9
Kp
2
Then
VIt =

5 + ( 0.8 ) + 3 ( 0.8 )
1+ 3

VIt = 1.65 V

16.49
By definition, NMOS is on if gate voltage is 5 V and is off if gate voltage is 0 V.
State
N1
N2
N3
N4
N5

v0

1
2
3
4

0
0
5
0

off
off
on
on

on
off
on
on

off
on
off
off

on
on
off
on

Logic function ( v X OR vY ) ( v X AND vZ )

Exclusive OR of ( vX OR vY ) with ( vX AND vZ )
16.50
W
NMOS in Parallel = 2
L n
W
4-PMOS in series = 4 ( 4 ) = 16
L p

(b)

CL doubles current must double to maintain switching speed.

W
=4
L n
W
= 32
L p

16.51
W
4-NMOS in series = 4 ( 2 ) = 8
L n
W
4-PMOS in parallel = 4
L p

(b)

16.52

L
W

= 16
n

=8
p

on
off
on
on

W
NMOS in parallel = 2
L n
W
3-PMOS in series = 3 ( 4 ) = 12
L P

(a)

(b)

L
W

=4
n

= 24
p

16.53
W
3-NMOS in series = 3 ( 2 ) = 6
L n
W
3-PMOS in parallel = 4
L p

(a)

(b)

16.54
(a)
(b)

L
W

= 12
n

=8
p

Y = A( B + C )( D + E )

W
For NMOS in pull down mode, 3 in series = 3 ( 2 ) = 6
L n
For PMOS
W
=4
L P, A

(c)

W
= 2 ( 4) = 8

L P , B ,C , D , E

16.55
(a)
(b)

Y = A( BD + CE )

(c)

NMOS: 3 transistors in series for pull down mode.

W
For twice the speed: = 2 ( 3)( 2 ) = 12
L n
W
PMOS: = 2 ( 4 ) = 8
L P, A

W
= 2 ( 2 )( 4 ) = 16

L P , B ,C , D , E
16.56
(a)
(b)

Y = A + BC + DE

W
W
NMOS: = 2
=4

L n, A
L n , B ,C , D , E
PMOS: 3 transistors in series for the pull-up mode

(c)

W
= 3 ( 4 ) = 12
L p

16.57
(a)
(b)

Y = A + ( B + D)(C + E )

(c)

W
NMOS: = 2 ( 2 ) = 4
L n, A

PMOS:
W
= ( 2 ) 3 ( 4 ) = 24
L p
16.58
(a) A classic design is shown:

W
= ( 2 )( 4 ) = 8

L n , B ,C , D , E

A, B, C signals supplied through inverters.

W
W
(b)
For Inverters, = 1 and = 2
L p
L n
W
W
For PMOS in Logic function, let = 1 , then for NMOS in Logic function, = 2.25
L p
L n

16.59
(a)

A classic design is shown:

(b)

W
W
=2
= 1,
L
ND
L NA, NB , NC
W
W
= 8,
=4

L PA, PB
L PC , PD

16.60

( A OR B )

AND C

16.61
W
5-NMOS in series = 5 ( 2 ) = 10
L n
W
5-PMOS in parallel = 4
L p

16.62
By definition:
NMOS off if gate voltage = 0
NMOS on if gate voltage = 5 V
PMOS off if gate voltage = 5 V
PMOS on if gate voltage = 0
State
1
2

N1
off
on

P1
on
off

NA
off
on

NB
off
off

NC
off
off

v01
5
5

N2
on
on

P2
off
off

v02
0
0

3
4
5
6

off
on
off
on

on
off
on
off

off
off
off
off

off
off
off
on

off
on
off
on

5
5
5
0

on
on
on
off

off
off
off
on

Logic function is
v02 = ( v A OR vB ) AND vC
16.63
State
1
2
3
4
5
6
Logic function:
v03 = ( vX OR vZ ) AND vY
16.64

v01

v02

v03

5
0
5
5
5
0

5
0
5
0
5
5

0
5
0
5
0
0

0
0
0
5

16.65

16.66

16.67

2 I = C

dVC
dt

So
1
( 2I ) t
C
For VC = 0.5 V
VC =

0.5 =

16.68
(a)
(i)
(ii)
(iii)
(b)
(i)
(ii)
(iii)
16.69
(a)
(i)
(ii)
(iii)
(b)
(i)
(ii)
(iii)

2 ( 2 x 1012 ) t
25 x 1015

t = 3.125 ms

vO = 0
vO = 4.2 V
vO = 2.5 V
vO = 0
vO = 3.2 V
vO = 2.5 V

vo = 0
vo = 2.9 V
vo = 2.4 V
vo = 0
vo = 2.0 V
vo = 2.0 V

16.70
Neglect the body effect.
v01 (logic 1) = 4.2 V , v02 (logic 1) = 5 V
a.
vI = 5 V vGS 1 = 4.2 V
b.
M 1 in nonsaturation and M 2 in saturation. From Equation (16.23)
W

L
W

L
Or
W

W
2
2 ( vGS 1 VTND ) vO1 vO1 = (VDD vO1 VTNL )
L
D
L
2
2

2 ( 4.2 0.8 )( 0.1) ( 0.1) = (1) [5 0.1 0.8]
D

W
( 0.67 ) = 16.81 = 25.1
D
L D

Now
v01 = 4.2 V vGS 3 = 4.2 V
M 3 in nonsaturation and M 4 in saturation. From Equation (16.29(b)).
W

L
W

W
2
2 ( vGS 3 VTND ) vO 2 vO 2 = [ VTNL ]
D
L L
2
2

2 ( 4.2 0.8 )( 0.1) ( 0.1) = ( 2 ) ( 1.5 )

D

W
(0.67) = 2.25
L D

W
Or = 3.36
L D

16.71
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
indeterminate
0.1
Without the top transistor, the circuit performs the exclusive-NOR function.
16.72
B
A
A
0
1
0
0
1
1
1
0
0
1
0
1
Y = A + AB = A + B
Z = Y or Z = AB

B
1
0
1
0

Y
0
1
1
1

Z
1
0
0
0

16.73

16.74
For = 1, = 0, then Y = B. And for = 0, = 1, then Y = A .
A multiplexer.
16.75
Y = AC + BC
16.76
Y = AB + AB = A B
16.77

A
0
1
0
1

B
0
0
1
1

Y
0
1
1
0

Exclusive-OR function.
16.78
This circuit is referred to as a two-phase ratioed circuit. The same width-to-length ratios between the driver
and load transistors must be maintained as discussed previously with the enhancement load inverter.
When 1 is high, v01 becomes the complement of vI . When 2 goes high, then v0 becomes the
complement of v01 or is the same as vI . The circuit is a shift register.
16.79
Let Q = 0 and Q = 1 ; as S increases, Q decreases. When Q reaches the transition point of the M 5 M 6
inverter, the flip-flop with change state. From Equation (16.28(b)),
KL
VIt =
( VTNL ) + VTND
KD
where K L = K 6 and K D = K 5 .
Then
30
VIt =
( 2 ) + 1 VIt = Q = 2.095 V
100
This is the region where both M 1 and M 3 are biased in the saturation region. Then
S=

K3
( VTNL ) + VTND =
K1

30
( 2 ) + 1
200

or S = 1.77 V
This analysis neglects the effect of M 2 starting to turn on at the same time.
16.80
Let vY = R, v X = S , v02 = Q, and v01 = Q. Assume VThN = 0.5 V and VThP = 0.5 V. For S = 0, we have
the following:

If we want the switching to occur for R = 2.5 V, then because of the nonsymmetry between the two
circuits, we cannot have Q and Q both equal to 2.5 V.
Set R = Q = 2.5 V and assume Q goes low.
For the M 1 M 5 inverter, M 1 in nonsaturation and M 5 in saturation. Then
2
2
K n 2 ( 2.5 0.5 ) Q Q = K p [ 2.5 0.5]

Or
2
Kp
4Q Q = 4

Kn

For the other circuit, M 2 M 4 in saturation and M 6 in nonsaturation. Then

2
K n ( 2.5 0.5 ) + K n (Q 0.5) 2 = K p 2 5 Q 0.5 ( 2.5 ) ( 2.52 )

Combining these equations and neglecting the Q 3 term, we find

Kp

Q = 1.4 V and

kn

= 0.9

16.81
3.3 + ( 0.4 ) + 0.5
vIt =
= 1.7 V
1+1
vI = 1.5 V NMOS Sat; PMOS Non Sat
2
= 2 ( 3.3 vI 0.4 )( 3.3 vo1 ) ( 3.3 vo1 ) vo1 = 2.88 V

vI = 1.6 V vo1 = 2.693 V

vI = 1.7 V vo1 = variable (switching region)

( vI 0.5)

vI = 1.8 V

NMOS Non Sat; PMOS Sat

( 3.3 VI 0.4 )

= 2 ( vI 0.5 ) vo1 vo21 vo1 = 0.607 V

Now
vI = 1.5 V, vo1 = 2.88 V vo 0V

vI = 1.6 V, vo1 = 2.693 V

NMOS Non Sat; PMOS Sat
2
( 3.3 vo1 0.4 ) = 2 ( vo1 0.5 ) vo vo2
vo = 0.00979 V
vI = 1.7 V, v o1 = Switching Mode v0 = Switching Mode.
vI = 1.8 V, vo1 = 0.607 V NMOS Sat; PMOS Non Sat

( v01 0.5)

2
= 2 ( 3.3 v01 0.4 )( 3.3 v0 ) ( 3.3 v0 ) v0 = 3.298 V

16.82
For R = = VDD and S = 0 Q = 0, Q = 1
For S = = VDD and R = 0 Q = 1, Q = 1
The signal is a clock signal.
For = 0, The output signals will remain in their previous state.
16.83
a.

Positive edge triggered flip-flop when CLK = 1, output of first inverter is D and then Q = D = D .

b.

For example, put a CMOS transmission gate between the output and the gate of M 1 driven by a

CLK pulse.

16.84
For J = 1, K = 0, and CLK = 1; this makes Q = 1 and Q = 0 .

For J = 0, K = 1, and CLK = 1 , and if Q = 1, then the circuit is driven so that Q = 0 and Q = 1.
If initially, Q = 0, then the circuit is driven so that there is no change and Q = 0 and Q = 1.
J = 1, K = 1, and CLK = 1, and if Q = 1, then the circuit is driven so that Q = 0.
If initially, Q = 0 , then the circuit is driven so that Q = 1.
So if J = K = 1, the output changes state.
16.85
For J = v X = 1, K = vY = 0, and CLK = vZ = 1, then v0 = 0.
For J = v X = 0, K = vY = 1, and CLK = vZ = 1, then v0 = 1.
Now consider J = K = CLK = 1. With v X = vZ = 1, the output is always v0 = 0, So the output does not
change state when J = K = CLK = 1. This is not actually a J K flip-flop.
16.86
64 K 65,536 transistors arranged in a 256 256 array.
(a)
Each column and row decoder required 8 inputs.
(b)
(i)
Address = 01011110 so input = a7 a6 a5 a4 a3 a2 a1a0
(ii)
Address = 11101111 so input = a7 a6 a5 a4 a3 a2 a1a0
(c)
(i)
(ii)

Address = 00100111 so input = a7 a6 a5 a4 a3 a2 a1a0

Address = 01111011 so input = a7 a6 a5 a4 a3 a2 a1a0

16.87
(a)

1-Megabit memory

= 1, 048,576 1024 1024

Nuclear & input row and column decodes lines necessary = 10

(b)
250K 4 bits 262,144 4 bits 512 512
For 512 lines 9 row and column decoder lines necessary.
16.88
Put 128 words in a 8 16 array, which means 8 row (or column) address lines and 16 column (or row)
address lines.
16.89
Assume the address line is initially uncharged, then
dV
1
I
I = C C or VC = Idt = t
C
C
dt
12
VC C ( 2.7 ) ( 5.8 10 )

=
I
250 106
t = 6.26 10 8 s 62.6 ns

Then t =

16.90

(a)
W
or
L
(b)

5 0.1 35 W
=
1
2 L

2 ( 5 0.7 )( 0.1) ( 0.1)

= 0.329

16 K 16,384 cells

2
= 2 A
1
Power per cell = (2 A)(2 V ) = 4 W
Total Power = PT = (4 W )(16,384) PT = 65.5 mW
iD

Standby current = (2 A)(16,384) IT = 32.8 mA

16.91
16 K 16,384 cells
200
12.2 W
16,384
V
P
12.2
2.5
iD =
=
= 4.88 A DD =
R = 0.512 M
VDD
R
R
2.5
PT = 200 mW Power per cell =

If we want vO = 0.1 V for a logic 0, then

k W
iD = n 2 (VDD VTN ) vO vO2
2 L
2
35 W
4.88 = 2 ( 2.5 0.7 )( 0.1) ( 0.1)

2 L
W
So = 0.797
L

16.92
Q = 0, Q = 1
So D = Logic 1 = 5 V
A very short time after the row has been addressed, D remains charged at VDD = 5 V . Then M p 3, M A, and
M N 1 begin to conduct and D decreases. In steady-state, all three transistors are biased in the nonsaturation
region. Then
2
2
2

K p 3 2 (VSG 3 + VTP 3 ) VSD 3 VSD

3 = K nA 2 (VGSA VTNA ) VDSA VDSA = K n1 2 (VGS 1 VTN 1 ) VDS 1 VDS 1

Or
2
2
K p 3 2 (VDD + VTP 3 )(VDD D ) (VDD D ) = K nA 2 (VDD Q VTNA )( D Q ) ( D Q )

= K n1 2 (VDD VTN 1 ) Q Q 2 (1)

Equating the first and third terms:

2
20
40
2
(1) 2 ( 5 0.8 )( 5 D ) ( 5 D ) = ( 2 ) 2 ( 5 0.8 ) Q Q (2)
2
2
As a first approximation, neglect the ( 5 D ) and Q 2 terms. We find
2

Q = 1.25 0.25 D
(3)
Then, equating the first and second terms of Equation (1):
2
2
20
40
(1) 2 ( 5 0.8 )( 5 D ) ( 5 D ) = (1) 2 ( 5 Q 0.8 )( D Q ) ( D Q )
2
2

Substituting Equation (3), we find as a first approximation: D = 2.14 V

Substituting this value of D into equation (2), we find
2
8.4 ( 5 2.14 ) ( 5 2.14 ) = 4 8.4Q Q 2
We find Q = 0.50 V
Using this value of Q, we can find a second approximation for D by equating the second and third terms of
equation (1). We have
2
20 2 ( 4.2 Q )( D Q ) ( D Q ) = 40 2 ( 4.2Q ) Q 2

Using Q = 0.50 V , we find D = 1.79 V

16.93
Initially M N 1 and M A turn on.
M N 1, Nonsat; M A , sat.
K nA [VDD Q VTN ] = K n1 2 (VDD VTN 1 ) Q Q 2
2

2
40
40
2
(1) [5 Q 0.8] = ( 2 ) 2 ( 5 0.8 ) Q Q
2
2


which yields
Q = 0.771 V

Initially M P 2 and M B turn on

Both biased in nonsaturation reagion
2
2
K P 2 2 (VDD + VTP 3 ) VDD Q VDD Q = K nB 2 (VDD VTNB ) Q Q

2
2
20

40

( 4 ) 2 ( 5 0.8 ) 5 Q 5 Q = (1) 2 ( 5 0.8 ) Q Q

2
2

) (

) (

which yields Q = 3.78 V

Note: (W / L) ratios do not satisfy Equation (16.86)
16.94
For Logic 1, v1:

( 5 )( 0.05 ) + ( 4 )(1) = (1 + 0.05 ) v1 v1 = 4.0476 V

v2 :
(5)(0.025) + (4)(1) = (1 + 1.025)v2 v2 = 4.0244 V

For Logic 0, v1:

(0)(0.05) + (4)(1) = (1 + 0.05)v1 v1 = 3.8095 V
v2 :
(0)(0.025) + (4)(1) = (1 + 0.025)v2 v2 = 3.9024 V

16.95
Not given
16.96
Not given
16.97
Not given

16.98
Quantization error =

(a)

Or LSB 0.10 V
For a 6-bit word , LSB =
1 LSB =

(b)

1
LSB 1% 0.05 V
2

5
= 0.078125 V
64

5
= 0.078125 V
64

3.5424
64 = 45.34 n = 45
5
Digital Output = 101101
45 5
= 3.515625
64
.
1
= 3.5424 3.515625 = 0.026775 < LSB.
2

(c)

16.99
Quantization error =

(a)

1 LSB = 0.10 V

1
LSB 0.5% 0.05 V
2

10
= 0.078125 V
128
1 LSB = 0.078125 V

For a 7-beit word, LSB =

(b)

3.5424
128 = 45.34272 n = 45
10
Digital output = 0101101

(c)

Now

45 10
= 3.515625
128

= 3.5424 3.515625 = 0.026775 V <

16.100
(a)

(b)

0 1 0 1
vo = + + + ( 5 )
2 4 8 16
vo = 1.5625 V
1 0 1 0
vo = + + + ( 5 )
2 4 8 16
vo = 3.125 V

16.101
1
LSB = ( 5 ) = 0.3125 V
16
1
LSB = 0.15625 V
2
10
Now vo =
(5)
20 + R1

(a)

1
LSB
2

For vo = 2.5 + 0.15625 = 2.65625 V

(10 )( 5)

R1 = 1.176 K
2.65625
For vo = 2.5 0.15625 = 2.34375 V
20 + R1 =

20 + R1 =

(10 )( 5 )

2.34375 V
R1 = +1.333 K

For R1 = 1.176 K R1 = 5.88%

10
For R4 : vo =
( 5)
160 + R4
vo = 0.3125 + 0.15625 = 0.46875 V

(b)

(10 )( 5 )

R4 = 53.33K
0.46875
Or vo = 0.3125 0.15625 = 0.15625 V

160 + R4 =

(10 )( 5 )

R4 = 160 K
0.15625
For R4 = 53.33K R4 = 33.33%
160 + R4 =

16.102
(a)

R5 = 320 k
R6 = 640 k
R7 = 1280 k
R8 = 2560 k

(b)

10
vo =
( 5 ) = 0.01953125 V
2560

16.103
(a)
V
5
I1 = 0.50 mA
I1 = REF =
2 R 10
I
I 2 = 1 = 0.25 mA
2
I2
I 3 = = 0.125 mA
2
I3
I 4 = = 0.0625 mA
2
I4
I 5 = = 0.03125 mA
2
I
I 6 = 5 = 0.015625 mA
2
vo = I 6 RF = ( 0.015625 )( 5 )
(b)
vo = 0.078125 V

(c)

vo = [ I 2 + I 5 + I 6 ] RF = [ 0.25 + 0.03125 + 0.015625] ( 5 )

vo = 1.484375 V

(d)

For 101010; vo = ( 0.50 + 0.125 + 0.03125 )( 5 ) = 3.28125 V

For 010101; vo = ( 0.25 + 0.0625 + 0.015625 )( 5 ) = 1.640625 V

vo = 1.640625 V

16.104
1
5
V R V
= 0.3125 V
LSB = REF = REF =
2
8
2
16
16
R

Ideal
3
3V
v A for 011 REF ( R ) = VREF = 1.875 V
8
R
8

1
Range of v A = 1.875 LSB
2
or 1.5625 vA 2.1875 V
16.105
6-bits 26 = 64 resistors
26 1 = 63 comparators
16.106
(a)
10- bit output 1024 clock periods
1
1
1 clock period = = 6 = 1 S
f 10
May conversion time = 1024 S = 1.024 mS
(b)
1
1 5
LSB =
= 0.002441406 V
2
2 1024
5
vA = (128 + 16 + 2 )
= 0.712890625 V
1024
1
So range of v A = vA LSB
2
0.710449219 v A 0.715332031 V
(c)
0100100100 256 + 32 + 4 = 292 clock pulses
16.107
N 5
N = 640 512 + 128
1024
Output = 1010000000
(b)
N 5
N = 381.19 N = 381 256 + 64 + 32 + 16 + 8 + 4 + 1
1.8613 =
1024
Output = 0101111101
(a)

3.125 =