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Exercice 2 : Donner le code VHDL (flot de données ) correspondant à la porte logique OR.
Whith …. Select
a(0)
S Library ieee;
a(1) Use ieee.std_logic_1164.all;
Entity Circuit is
a S Port( a: in std_logic_vector (1 down to 0);
S: out std_logic);
End Circuit;
Architecture Mycircuit of Circuit is
begin
with a select
S<= ‘0’ when ‘’00 ’’ ,
‘1’ when others;
end Mycircuit;
Deuxiéme solution
Exercice 2 : Donner le code VHDL (flot de données ) correspondant à la porte logique OR.
Equations logiques
a(0) Library ieee;
S Use ieee.std_logic_1164.all;
a(1)
Entity Circuit is
a S Port( a: in std_logic_vector (1 down to 0);
S : out std_logic);
End Circuit;
Architecture Mycircuit of Circuit is
begin
S <= a(0) or a(1);
end Mycircuit;
Troisième solution