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Rapport de TP
CARTE FPGA
PRG EN VHDL

Encadrée par :
Mr. ELKARI
REALISEE :
Mme : Khadija
Omayma maamouz

Rajae el waarabi
TP 1 : Développement d’un système numérique

Objectifs :

Développer des systèmes numériques programmables simples (multiplexeur, compteur...).

Simuler un système numérique.

Structure d’un projet

Structure d’un projet Un projet VHDL est très souvent décomposé en sous-structures, appelées
modules ou composants. Comme on pourrait le faire sur un circuit imprimé, il s’agit d’instancier
différents composants et de les relier entre eux par des fils (signaux en VHDL) pour réaliser le
système complet. Chacun de ces modules est alors décrit dans un fichier source indépendant. Chacun
de ces fichiers sources peut alors être testé indépendamment en lui associant un fichier de
simulation (ou testbench). Enfin des fichiers de contraintes permettent de faire le lien entre la
description logicielle et la structure matérielle de la cible et de son environnement (position des
entrées, des sorties...).
Une description en vhdl de schéma suivant :

Bascule D : Porte ET :
library ieee; Library IEEE ;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all; use work.std_arith.all ;
use ieee.std_logic_signed.all; entity ET is
entity basculeD is port ( Port ( A, B : in std_logic ;
D: in std_logic; S : out std_logic ) ;
CE : in std_logic; end nand ;
H : in std_logic; architecture PORTE of and is
Q : out std_logic; begin
CLR : in std_logic); S<= A and B ;
end basculeD; end PORTE ;
architecture rtl of basculeD is
begin
process(CLR,CE,H)

begin
if CLR='1'then Q<='0'; else
if CE='1' and (H='0' and h'event) then Q<=D;
end if;
end if;

end process;
end rtl;
library ieee;
architecture rtl of CIRCUIT is
use ieee.std_logic_1164.all;
signal D_interne: std_logic;
use ieee.std_logic_arith.all;
component porteET
use ieee.std_logic_unsigned.all;
port(
entity CIRCUIT is port (
E1: in std_logic;
a: in std_logic;
E2: in std_logic;
b:in std_logic;
S: out std_logic);
clkEn : in std_logic;
end component;
clk : in std_logic;
component basculeD
clear: in std_logic;
port(
c :out std_logic);
D: in std_logic;
end CIRCUIT;
CE : in std_logic;
H : in std_logic;
Q : out std_logic;
CLR : in std_logic);

end component;

begin
etiq1: porteET port map ( E1 =>a,E2=>b,s=>D_Interne);
etiq2: basculeD port map (H=>clk,CE=>clkEn,clr=>clear,D=>d_interne,Q=>C);
end rtl;
Réalisation d’un compteur modulo 9
Compteur 9
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity comptneuf is
port(
a9,CLR: in std_logic ;
CARRY9 : out std_logic;
Septseg
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity septseg is
port(
b : in std_logic_vector( 3 downto 0);
seg : out std_logic_vector (6 downto
0));

Q9: inout std_logic_vector( 3 downto 0) end;

); architecture behavioral of septseg is

end; begin

architecture behavioral of comptneuf is process(b)

begin begin

process(a9,CLR) case b is

begin when "0000" => seg<="1000000" ;

if CLR='1'then Q9<="0000"; when "0001" => seg<="1111001" ;

elsif (a9='1' and a9'EVENT ) then when "0010" => seg<="0100100" ;

if Q9=8 then Q9<=Q9+1; CARRY9 <='1'; when "0011" => seg<="0110000" ;

if Q9=9 then Q9<="0000"; CARRY9 <='0' ; when "0100" => seg<="0011001" ;

else Q9<=Q9+1; when "0101" => seg<="0010010" ;

end if; when "0110" => seg<="0000010" ;

end if; when "0111" => seg<="1111000" ;

end if; when "1000" => seg<="0000000" ;

end process; when "1001" => seg<="0010000" ;

end behavioral; when others => seg<="1111111" ;

end case;

end process;

end behavioral;
Diviseur de fréquence
Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity Div is

port(

clk_50: in std_logic ;

clk_1: out std_logic

);

end;

architecture behavioral of Div is

signal compt: integer range 0 to 10000000;

begin

process(clk_50)

begin

if( clk_50='0' and clk_50'EVENT) then

if (compt=10000000) then

compt<=0 ; clk_1<='1' ;

else

compt<=compt+1 ; clk_1<='0';

end if;

end if;

end process;

end behavioral;
deviseur de fréquence avec afficheur 7SEG
library ieee; Q : inout std_logic_vector( 3
use ieee.std_logic_1164.all; downto 0);

use ieee.std_logic_arith.all; seg : out std_logic_vector (6

downto 0)
use ieee.std_logic_unsigned.all;
);
entity Divcompt is port (
end component;
clk_a: in std_logic;
begin
clr_b:in std_logic;
etq1: Div port map ( clk_50
sept: out std_logic_vector (6 =>clk_a,clk_1=>D_Interne);
downto 0)
etq2: septsegm port map
);
(CLR=>clr_b,H=>d_interne,seg=>se
end Divcompt; pt);
end rtl;
architecture rtl of Divcompt is
signal D_interne: std_logic;

component Div
port(
clk_50: in std_logic ;
clk_1: out std_logic
);
end component;

component septsegm
port(
H,CLR: in std_logic ;
Méthode 1 ( compteur sans diviseur de fréquence) :
Library ieee; process(Q)
use ieee.std_logic_1164.all; begin
use ieee.std_logic_arith.all; case Q is
use ieee.std_logic_unsigned.all; when "0000" =>
seg<="1000000" ;

entity septsegm is when "0001" =>

seg<="1111001" ;
port(
when "0010" =>
H,CLR: in std_logic ; seg<="0100100" ;
Q : inout std_logic_vector( 3 downto 0); when "0011" =>
seg : out std_logic_vector (6 downto 0) seg<="0110000" ;
); when "0100" =>
seg<="0011001" ;
end;
when "0101" =>
architecture behavioral of septsegm is
seg<="0010010" ;
begin
when "0110" =>
seg<="0000010" ;
process(H,CLR) when "0111" =>
begin seg<="1111000" ;

if CLR='1'then Q<="0000"; when "1000" =>

seg<="0000000" ;
elsif (H='1' and H'EVENT) then
when "1001" =>
if Q=9 then Q<="0000"; seg<="0010000" ;
else Q<=Q+1; when others =>
end if; seg<="1111111" ;

end if; end case;

end process ;
end process;

end behavioral;
Réalisation d’une horloge :
Compteur modulo 9 :
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
Diviseur de fréquence :
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity comp is entity Div is

port( port(
a,CLR: in std_logic ; clk_50: in std_logic ;
CARRY : out std_logic; clk_1: out std_logic
Q: inout integer range 0 to 9 );
); end;
end; architecture behavioral of Div is
architecture behavioral of comp is signal compt: integer range 0 to
begin 50000;

process(a,CLR) begin

begin process(clk_50)

if CLR='1'then Q<=0; CARRY <='0' ; begin

elsif (a'EVENT and a='1') then if( clk_50='0' and clk_50'EVENT)

then
if Q=9 then Q<=0; CARRY <='1' ;
if (compt=50000) then
else Q<=Q+1; CARRY <='0' ;
compt<=0 ; clk_1<='1' ;
end if;
else
end if;
compt<=compt+1 ;
clk_1<='0';
end process;

end behavioral; end if;

end if;
end process;

end behavioral;
Septseg
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity septseg is
port(

b : in integer range 0 to 9 ;
seg : out std_logic_vector (6 downto 0) );
end;
architecture behavioral of septseg is
begin

process(b)
begin
case b is
when 0 => seg<="1000000" ;
when 1 => seg<="1111001" ;

when 2 => seg<="0100100" ;

when 3 => seg<="0110000" ;
when 4 => seg<="0011001" ;
when 5 => seg<="0010010" ;
when 6 => seg<="0000010" ;

when 7 => seg<="1111000" ;

when 8 => seg<="0000000" ;
when 9 => seg<="0010000" ;
when others => seg<="1111111" ;
end case;

end process;

end behavioral;
Programme principale
library ieee;
end component;
use ieee.std_logic_1164.all;
signal sin1,sin2,sin3,sin4,sin5,sin6,H_1:
use ieee.std_logic_arith.all; integer;
use ieee.std_logic_unsigned.all; signal r1,r2,r3,c1,c2,c3,c4,c5,c6,h,m,s:
std_logic;
entity timert is port (
begin
H_50,CLEAR:in std_logic;
etiq0 : div port map(H_50,s);
s1,s2,s3,s4,s5,s6:out std_logic_vector(6 downto 0));
process(cleAR,sin1,sin2,sin3,sin4,sin5,sin6
end timert;
)
architecture rtl of timert is
begin

if(cleaR='1') then r1<='1'; r2<='1';r3<='1';

component comp
else
port(
if (sin1=0) and (sin2=6) then r1<='1';
CLR,a: in std_logic ; m<='1';

CARRY : out std_logic; else r1<='0';m<='0';

Q: inout integer range 0 to 9 end if;

); if (sin3=0) and (sin4=6) then r2<='1';

r1<='1';h<='1';
end component;
else r2<='0';h<='0';

end if;
component septseg
if (sin5=4) and (sin6=2) then r3<='1';
port(
else r3<='0';
b : in integer range 0 to 9 ;
end if;
seg : out std_logic_vector (6 downto 0)
end if;
);
end process;
end component;

etiq1 : COMP port map(r1,s,c1,sin1);

component div
etiq2 : COMP port map(r1,c1,c2,sin2);
port(
etiq3 : septseg port map(sin1,s1);
clk_50: in std_logic ;
etiq4 : septseg port map(sin2,s2);
clk_1: out std_logic

);
end component;

signal sin1,sin2,sin3,sin4,sin5,sin6,H_1: integer;

signal r1,r2,r3,c1,c2,c3,c4,c5,c6,h,m,s: std_logic;

begin

etiq0 : div port map(H_50,s);

process(cleAR,sin1,sin2,sin3,sin4,sin5,sin6)

begin

if(cleaR='1') then r1<='1'; r2<='1';r3<='1';

else

if (sin1=0) and (sin2=6) then r1<='1'; m<='1';

else r1<='0';m<='0';

end if;

if (sin3=0) and (sin4=6) then r2<='1'; r1<='1';h<='1';

else r2<='0';h<='0';

end if;

if (sin5=4) and (sin6=2) then r3<='1';

else r3<='0';

end if;

end if;

end process;

etiq1 : COMP port map(r1,s,c1,sin1);

etiq2 : COMP port map(r1,c1,c2,sin2);

etiq3 : septseg port map(sin1,s1);

etiq4 : septseg port map(sin2,s2);

etiq5 : COMP port map(r2,m,c3,sin3);

etiq6 : COMP port map(r2,c3,c4,sin4);

etiq7 : septseg port map(sin3,s3);

etiq8 : septseg port map(sin4,s4);

etiq9 : COMP port map(r3,h,c5,sin5);

etiq10 : COMP port map(r3,c5,c6,sin6);

etiq11 : septseg port map(sin5,s5);

etiq12 : septseg port map(sin6,s6);

end rtl;