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I. Introduction
Le but de ce projet est d’exploiter Xilinx ISE pour réaliser un controlleur d’affichage VGA
II. Architectures
Dans cette partie, nous allons représenter et décrire les architectures des unités que nous avons
conçues et exploiter les démarches que nous avons adopttées pour y parvenir.
1.Module multiplexeur
Ce module permet de selectionner une entrée parmi 8 chacune codée sur 4 bits qui permet
d’adresser un bloc designant un caractère parmi 16 caractères.
1.1Code VhdL :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux8_1 is
Port ( U0,U1,U2,U3,U4,U5,U6,U7 : in STD_LOGIC_VECTOR (3 downto 0);
sel : in std_logic_vector (2 downto 0);
sort : out STD_LOGIC_VECTOR (3 downto 0));
end mux8_1;
architecture Behavioral of mux8_1 is
begin
process(U0,U1,U2,U3,U4,U5,U6,U7 ,sel)
begin
case sel is
when "000"=> sort<=U0;
when "001"=> sort<=U1;
when "010"=> sort<=U2;
when "011"=> sort<=U3;
when "100"=> sort<=U4;
when "101"=> sort<=U5;
when "110"=> sort<=U6;
when others=> sort<=U7;
end case;
end process;
end Behavioral;end case;
1 .3 Testbensh
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testMux IS
END testMux;
ARCHITECTURE behavior OF testMux IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux8_1
PORT(
U0 : IN std_logic_vector(3 downto 0);
U1 : IN std_logic_vector(3 downto 0);
U2 : IN std_logic_vector(3 downto 0);
U3 : IN std_logic_vector(3 downto 0);
U4 : IN std_logic_vector(3 downto 0);
U5 : IN std_logic_vector(3 downto 0);
U6 : IN std_logic_vector(3 downto 0);
U7 : IN std_logic_vector(3 downto 0);
sel : IN std_logic_vector(2 downto 0);
sort : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
signal clk:std_logic:='0';
--Inputs
signal U0 : std_logic_vector(3 downto 0) := "0000";
signal U1 : std_logic_vector(3 downto 0) := "0001";
signal U2 : std_logic_vector(3 downto 0) := "0010";
signal U3 : std_logic_vector(3 downto 0) := "0011";
signal U4 : std_logic_vector(3 downto 0) := "0100";
signal U5 : std_logic_vector(3 downto 0) := "0101";
signal U6 : std_logic_vector(3 downto 0) := "1001";
signal U7 : std_logic_vector(3 downto 0) := "1010";
signal sel : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal sort : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mux8_1 PORT MAP (
U0 => U0,
U1 => U1,
U2 => U2,
U3 => U3,
U4 => U4,
U5 => U5,
U6 => U6,
U7 => U7,
sel => sel,
sort => sort
);
-- Stimulus process
stim_proc: process
begin
sel<="000";
wait for 2 ps;
sel<="001";
wait for 2 ps;
sel<="010";
wait for 2 ps;
sel<="011";
wait for 2 ps;
end process;
END;
Fig2 :Testbensh du multiplexeur8_1
2 .Module gestion de decodage :
Ce module a pour fonction :
D’envoyer une adresse sur codée sur 3 bits qui sera utile pour le multeplexeur
menstionner au dessous pour selectionner le bloc relatif a un caractere.
Adresser l’emplacement du bit qui sera codée sur 6 bits : 3bits pour acceder à la ligne
et 3 bits pour accéder au colonne etant donnée que chaque caractère est écrit sur une
matrice de 64 bits.Cette adresse serait utile pour la ROM pour un accées en lecture soit
pour la RAM pour un accées en lecture ou en ecriture en fonction de la valeur de
WR(1 pour ecire en RAM ,0 pour lire).
Attribuer une valeur pour WR.
2.3 Testbensh
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tester_gestiondec IS
END tester_gestiondec;
ARCHITECTURE behavior OF tester_gestiondec IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gestion_decod
PORT(
B : OUT std_logic_vector(8 downto 0);
ST : IN std_logic;
WR : OUT std_logic;
sp : IN std_logic
);
END COMPONENT;
--Inputs
signal ST : std_logic := '0';
signal sp : std_logic := '0';
--Outputs
signal B : std_logic_vector(8 downto 0);
signal WR : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: gestion_decod PORT MAP (
B => B,
ST => ST,
WR => WR,
sp => sp
);
-- Stimulus process
stim_proc: process
begin
ST<='0';
for i in 1 to 100 loop
sp<='1';
wait for 10 ns;
sp<='0';
wait for 10 ns;
end loop;
ST<='1';
for i in 1 to 100 loop
sp<='1';
wait for 10 ns;
sp<='0';
wait for 10 ns;
end loop;
wait;
end process;
END;
3. Module ROM
La Rom que nous avons adopter dans ce projet est une Rom de taille 1024 bits.
L’entrée a dans notre Rom est codée sur 10bits :a(9 downto 6) permet d’adresser le bloc et a(5
downto 0) permet de selectionner le bit de la matrice des 64bits.
On fait sortir de la Rom les données bit par bits c’est pour cette raison que Data_out est codée
sur 1 seul bit.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ROM is
Port ( a : in STD_LOGIC_VECTOR (9 downto 0);
Data_out: out STD_LOGIC);
end ROM;
architecture Behavioral of ROM is
Signal i : integer range 0 to 127;
Signal j : integer range 0 to 7;
type ROM_Array is array(0 to 127) of std_logic_vector(7 downto 0);
constant police:ROM_Array:= (
0 => "01110000",
1 => "10001000",
2 => "10001000",
3 => "10001000",
4 => "10001000",
5 => "10001000",
6 => "10001000",
7 => "01110000",
8 => "00100000" , ------------code de 1
9 => "00100000",
10 => "00100000",
11 => "00100000",
12 => "00100000",
13 => "00100000",
14 => "00100000",
15 => "01110000",
16 => "11110000", --------code de 2
17 => "10001000",
18 => "00001000",
19 => "11111000",
20 => "10000000",
21 => "10000000",
22 => "10000000",
23 => "11111000",
24 => "11111000" , ----code de 3
25 => "00001000",
26 => "00001000",
27 => "00001000" ,
28 => "11111000",
29 => "00001000",
30 => "00001000",
31 => "11111000",
32 => "00010000", -----------code de 4
33 => "00110000",
34 => "01010000",
35 => "10010000",
36 => "10010000",
37 => "11111000",
38 => "00010000",
39 => "00111000",
40 => "11111000",---code de 5
41 => "10000000",
42 => "10000000",
43 => "10000000",
44 => "11111000",
45 => "00001000",
46 => "00001000",
47 => "11111000",
48 =>"00001000",---code de 6
49 =>"00100000",
50 =>"01000000",
51 =>"10000000",
52 =>"11111000",
53 =>"10001000",
54 =>"01001000",
55 =>"00110000",
56 =>"11111000",-----code de 7
57 =>"10001000",
58 =>"00001000",
59 =>"00010000",
60 =>"00100000",
61 =>"00100000",
62 =>"00100000",
63 =>"00100000",
64 =>"01110000",----code de 8
65 =>"10001000",
66 =>"10001000",
67 =>"01110000",
68 =>"10001000",
69 =>"10001000",
70 =>"10001000",
71 =>"01110000",
72 =>"01110000",---code de 9
73 =>"10001000",
74 =>"10001000",
75 =>"11111000",
76 =>"00001000",
77 =>"00001000",
78 =>"00010000",
79 =>"01100000",
80 =>"00100000",----code de A
81 =>"01010000",
82 =>"10001000",
83 =>"10001000",
84 =>"11111000",
85 =>"10001000",
86 =>"10001000",
87 =>"10001000",
88 =>"11111000",----code de B
89 =>"10001000",
90 =>"10001000",
91 =>"10001000",
92 =>"11111000",
93 =>"10001000",
94 =>"10001000",
95 =>"11111000",
96 =>"00111000",---code de C
97 =>"01000000",
98 =>"10000000",
99 =>"10000000",
100 =>"10000000",
101 =>"10000000",
102 =>"01000000",
103 =>"00111000",
104 =>"11100000",--code de D
105 =>"10010000",
106 =>"10001000",
107 =>"10001000",
108 =>"10001000",
109 =>"10001000",
110 =>"10010000",
111 =>"11100000",
112 =>"11111000",---code de E
113 =>"10000000",
114 =>"10000000",
115 =>"10000000",
116 =>"11110000",
117 =>"10000000",
118 =>"10000000",
119 =>"11111000",
120 =>"11111000",--code de F
121 =>"10000000",
122 =>"10000000",
123 =>"10000000",
124 =>"11100000",
125 =>"10000000",
126 =>"10000000",
127 =>"10000000");
begin
process(i,j)
begin
Data_out<=police(i)(j);
end process;
i <= conv_integer(a(9 downto 3));
j <= conv_integer(a(2 downto 0));
end Behavioral;
3.3 Testbensh
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tester1_rom IS
END tester1_rom;
ARCHITECTURE behavior OF tester1_rom IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ROM
PORT(
a : IN std_logic_vector(9 downto 0);
Data_out : OUT std_logic);
END COMPONENT;
--Inputs
signal clk:std_logic:='0';
signal a : std_logic_vector(9 downto 0) :="0000000000";
--Outputs
signal Data_out : std_logic;
begin
-- Instantiate the Unit Under Test (UUT)
uut: ROM PORT MAP (
a => a,
Data_out => Data_out
);
stim_proc: process
begin
--wait for 2 ps;
a<="0011000000";
wait for 2 ps;
a<="0001000010";
wait for 2 ps;
a<="0000110000";
wait;
end process;
END;
Fig6 :Testbensh de la ROM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity RAM is
Port ( clock : in STD_LOGIC;
WR : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (8 downto 0);
address:in STD_LOGIC_VECTOR (8 downto 0);
datain : in STD_LOGIC;
dataout : out STD_LOGIC);
end RAM;
architecture Behavioral of RAM is
signal ram :std_logic_vector(511 downto 0);
begin
RamProc: process(clock,WR) is
begin
if rising_edge(clock) then
if WR = '1' then
ram(to_integer(unsigned(A))) <= datain;
else
dataout <= ram(to_integer(unsigned(address)));
end if;
end if;
end process RamProc;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tester_ram IS
END tester_ram;
ARCHITECTURE behavior OF tester_ram IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RAM
PORT(
clock : IN std_logic;
WR : IN std_logic;
A : IN std_logic_vector(8 downto 0);
address : IN std_logic_vector(8 downto 0);
datain : IN std_logic;
dataout : OUT std_logic
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal WR : std_logic := '0';
signal A : std_logic_vector(8 downto 0) := (others => '0');
signal address : std_logic_vector(8 downto 0) := (others => '0');
signal datain : std_logic := '0';
--Outputs
signal dataout : std_logic;
-- Clock period definitions
constant clock_period : time := 2 ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RAM PORT MAP (
clock => clock,
WR => WR,
A => A,
address => address,
datain => datain,
dataout => dataout
);
Fig8 :Testbensh de la RAM
end case;
end if;
end process;
sl<=syn_sl;
fl<=F_ligne;
process(s)
begin
if rising_edge(s) then
case etat1 is
when repotSt=> n1<=0;
etat1<=topSt;
when topSt=>n1<=n1+1;
syn_st<='0';
fentr<='0';
if (n1=10) then etat1<=debutft ;
end if;
when debutft=>
n1<=n1+1;
syn_st<='1';
fentr<='0';
if (n1=15) then etat1<=finft ;
end if;
when finft =>
n1<= n1+1;
syn_st<='1';
fentr<='1';
if (n1=495) then etat1<=fin_trame ;
end if;
when others=>
n1<= n1+1;
syn_st<='0';
fentr<='0';
if (n1=525) then etat1<=repotSt;
end if;
end case;
end if;
end process;
st<=syn_st;
ft<=fentr;
end Behavioral;
6 .3 Testbensh
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tester_gen_synch IS
END tester_gen_synch;
ARCHITECTURE behavior OF tester_gen_synch IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT generateur_de_synchro
PORT(
sp : IN std_logic;
ft : OUT std_logic;
fl : OUT std_logic;
sl : INOUT std_logic;
st : OUT std_logic
);
END COMPONENT;
--Inputs
signal sp : std_logic := '0';
--BiDirs
signal sl : std_logic;
--Outputs
signal ft : std_logic;
signal fl : std_logic;
signal st : std_logic;
signal sp_period : time := 4 ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: generateur_de_synchro PORT MAP (
sp => sp,
ft => ft,
fl => fl,
sl => sl,
st => st
);
clock_process :process
begin
sp <= '0';
wait for sp_period/2;
sp<= '1';
wait for sp_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
sl<='0';
wait for 2 ps;
sl<='1';
wait for 2 ps;
sl<='0';
wait for 2 ps;
sl<='1';
wait;
end process;
END;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_signed.all;
entity gestion_affichage is
Port (
SP : in STD_LOGIC;
clk:in std_logic;
NL : out std_logic_vector(2 downto 0);
NC : out std_logic_vector(5 downto 0);
FT:in std_logic;
FL:in std_logic;
affich:out std_logic);
end gestion_affichage;
architecture Behavioral of gestion_affichage is
type state is(repot,attendre_FL,afficher_ligne,incrementer,fin_ligne,fin_trame);
signal etat:state:=repot;
signal noir: std_logic;
signal ligne :integer range 0 to 7;
signal colonne :integer range 0 to 7;
signal bloc :integer range 0 to 7;
signal numc:std_logic_vector(2 downto 0);
signal numb:std_logic_vector(2 downto 0);
begin
process(clk)
begin
if rising_edge(clk)then
case etat is
when repot=> noir<='0';
ligne<=0;
colonne<=0;
bloc<=0;
if SP='1' then
if FT='1' then
etat<=attendre_FL;
end if;
end if;
when attendre_FL=> noir<='0';
colonne<=0;
bloc<=0;
if FL='1' then etat<=afficher_ligne;
end if;
when afficher_ligne=> noir<='1';
colonne<=colonne+1;
if colonne=7 then
bloc<=bloc+1;
if bloc=7 then
etat<=incrementer;
end if;
end if;
when incrementer=> noir<='0';
ligne<=ligne+1;
if ligne<=7 then
if FL='0' then etat<=attendre_FL;
end if;
else etat<=fin_trame;
end if;
when others=> etat<=fin_trame ;
if FT='0' then etat<=repot;
end if;
end case;
end if;
end process;
NL<=std_logic_vector(to_unsigned(ligne,3));
numb<=std_logic_vector(to_unsigned(bloc,3));
numc<=std_logic_vector(to_unsigned(colonne,3));
NC<=(numb(2),numb(1),numb(0),numc(2),numc(1),numc(0));
affich<=noir;
end Behavioral;
7.3 Testbensh
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY gestio_affich IS
END gestio_affich;
ARCHITECTURE behavior OF gestio_affich IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gestion_affichage
PORT(
SP : IN std_logic;
clk : IN std_logic;
NL : OUT std_logic_vector(2 downto 0);
NC : OUT std_logic_vector(5 downto 0);
FT : IN std_logic;
FL : IN std_logic;
affich : OUT std_logic
);
END COMPONENT;
--Inputs
signal SP : std_logic := '0';
signal clk : std_logic := '0';
signal FT : std_logic := '0';
signal FL : std_logic := '0';
--Outputs
signal NL : std_logic_vector(2 downto 0);
signal NC : std_logic_vector(5 downto 0);
signal affich : std_logic;
BEGIN
-- Stimulus process
stim_proc: process
begin
wait for 2 ps;
sp<='1';
clk<='1';
FL<='0';
FT<='1';
wait for 2 ps;
sp<='1';
clk<='1';
FL<='1';
FT<='1';
wait for 2 ps;
sp<='0';
clk<='1';
FL<='1';
FT<='1';
wait for 2 ps;
sp<='0';
clk<='1';
FL<='1';
FT<='0';
wait;
end process;
END;
8. IP_topLevel :
Code VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity IP_topLevel is port(
U0 : IN std_logic_vector(3 downto 0);
U1 : IN std_logic_vector(3 downto 0);
U2 : IN std_logic_vector(3 downto 0);
U3 : IN std_logic_vector(3 downto 0);
U4 : IN std_logic_vector(3 downto 0);
U5 : IN std_logic_vector(3 downto 0);
U6 : IN std_logic_vector(3 downto 0);
U7 : IN std_logic_vector(3 downto 0);
clk :in std_logic;
sl:out std_logic;
st:out std_logic;
RVB :out std_logic );
end IP_topLevel ;
COMPONENT ROM
PORT(
a : IN std_logic_vector(9 downto 0);
data_out : OUT std_logic
);
END COMPONENT;
COMPONENT RAM
PORT(
A : IN std_logic_vector(8 downto 0);
address : IN std_logic_vector(8 downto 0);
clock : IN std_logic;
WR : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT gestion_decod
PORT(
sp : IN std_logic;
ST : IN std_logic;
B : OUT std_logic_vector(8 downto 0);
WR : OUT std_logic
);
END COMPONENT;
COMPONENT gestion_affichage
PORT(
sp: IN std_logic;
clk : IN std_logic;
NL : buffer std_logic_vector (2 downto 0);
NC : buffer std_logic_vector (5 downto 0);
FT : IN std_logic;
FL : IN std_logic;
affich : OUT std_logic
);
END COMPONENT;
COMPONENT generateur_de_synchro
PORT(
sp : IN std_logic;
ft : out std_logic;
fl : OUT std_logic;
sl : INOUT std_logic;
st:out std_logic
);
END COMPONENT;
signal str,slx,ftx,flx,wre,doutx,srom,noirx,spix:std_logic;
signal out_mux : std_logic_vector(3 downto 0);
signal adr_dec,iram:std_logic_vector(8 downto 0);
signal arom:std_logic_vector(9 downto 0);
signal sl1 :std_logic ;
begin