CC & Système sur plateforme

reconfigurable

Travaux pratiques :

Réalise par : -Jesser Kramti

- Souhayl Tlili
 ❖ Définition de logiciel :
ModelSim est un outil développé par Mentor Graphics, maintenant une partie de Siemens. Il
fournit un environnement complet de simulation et de débogage pour les designs complexes en
ASIC et en FPGA. ModelSim supporte plusieurs langages de description, dont le Verilog, le
SystemVerilog, le VHDL et le SystemC1. Il offre également un environnement complet et facile à
utiliser pour l’analyse de la couverture de code, une condition indispensable pour les
certifications dans les industries critiques. Avec la vérification basée sur les assertions,
ModelSim aide à combler le fossé entre la productivité de la conception et celle de la vérification.
I. Port AND :
1. Schéma et table de vérité :

a b y

0 0 0

0 1 0

1 0 0

1 1 1

2. Code :
a) Code de composant

library IEEE;
use IEEE.std_logic_1164.all;
entity and_port is
port (
a,b : IN std_logic;
y : OUT std_logic
);
end and_port;

architecture dataflow of and_port is

begin
y <= a and b;
end dataflow;
 b) Code test Bench

library IEEE; process

use IEEE.std_logic_1164.all; begin
wait for 10 ns;
entity and_port_tb is a <= '0';
end and_port_tb; b <= '0';
wait for 10 ns;
architecture Behavioral of and_port_tb is a <= '0';
component and_port is b <= '1';
port ( wait for 10 ns;
a : in std_logic; a <= '1';
b : in std_logic; b <= '0';
y : out std_logic wait for 10 ns;
); a <= '1';
end component; b <= '1';
wait for 10 ns;
signal a: std_logic := '0'; end process;
signal b: std_logic := '0'; end Behavioral;
signal y: std_logic;

c) Simulation

II. Port OR :
1.
2. Schéma et table de vérité :

a b y

0 0 0

0 1 1
a b y

1 0 1

1 1 1

3. Code :
a) Code de composant
library IEEE;
use IEEE.std_logic_1164.all;

entity or_port is
port (
a,b : IN std_logic;
y : OUT std_logic
);
end or_port;

architecture dataflow of or_port is

begin
y <= a or b;
end dataflow;

b) Code test Bench

library IEEE; process
use IEEE.std_logic_1164.all; begin
wait for 10 ns;
entity or_port_tb is a <= '0';
end or_port_tb; b <= '0';
wait for 10 ns;
architecture Behavioral of or_port_tb is a <= '0';
component or_port is b <= '1';
port ( wait for 10 ns;
a : in std_logic; a <= '1';
b : in std_logic; b <= '0';
y : out std_logic ); wait for 10 ns;
end component; a <= '1';
b <= '1';
 signal a: std_logic := '0'; wait for 10 ns;
signal b: std_logic := '0'; end process;
signal y: std_logic; end Behavioral;

begin
uut : or_port port map ( a => a, b => b,
y => y );

c) Simulation

III. Port XOR :

1. Schéma et table de vérité :

a b y

0 0 0

0 1 1

1 0 1

1 1 0

2. Code :
a) Code de composant
library IEEE;
use IEEE.std_logic_1164.all;
entity xor_port is
port ( a,b : IN std_logic;
y : OUT std_logic);
end xor_port;
architecture dataflow of xor_port is
begin
y <= a xor b;
end dataflow;
 b) Code test Bench
library IEEE; process
use IEEE.std_logic_1164.all; begin
entity xor_port_tb is wait for 10 ns;
end xor_port_tb; a <= '0';
architecture Behavioral of xor_port_tb is b <= '0';
component xor_port is wait for 10 ns;
port ( a <= '0';
a : in std_logic; b <= '1';
b : in std_logic; wait for 10 ns;
y : out std_logic ); a <= '1';
end component; b <= '0';
wait for 10 ns;
signal a: std_logic := '0'; a <= '1';
signal b: std_logic := '0'; b <= '1';
signal y: std_logic; wait for 10 ns;
end process;
begin end Behavioral;
uut : xor_port
port map (a => a, b => b, y => y);

c) Simulation
IV. Port mux 4-1 :
1. Schéma et table de vérité :

s1 s0 a3 a2 a1 a0 y

0 0 0 0 0 0 0

0 1 0 0 0 1 1

1 0 0 0 1 0 0

1 1 0 1 0 0 0

0 1 0 0 1 0 1

2. Code :
a) Code de composant

library IEEE;
use IEEE.std_logic_1164.all;

entity mux_4_1 is
port (
a0, a1, a2, a3 : IN std_logic;
s0, s1 : IN std_logic;
y : OUT std_logic
);
end mux_4_1;

architecture Behavioral of mux_4_1 is

begin
y <= a0 when (s1 = '0' and s0 = '0') else
a1 when (s1 = '0' and s0 = '1') else
a2 when (s1 = '1' and s0 = '0') else
a3;
end Behavioral;
 b) Code test Bench
library IEEE; process
use IEEE.std_logic_1164.all; begin
wait for 10 ns;
entity mux_4_1_tb is a0 <= '0';
end mux_4_1_tb; a1 <= '0';
a2 <= '0';
architecture Behavioral of mux_4_1_tb is a3 <= '0';
component mux_4_1 is s0 <= '0';
port ( s1 <= '0';
a0, a1, a2, a3 : IN std_logic; wait for 10 ns;
s0, s1 : IN std_logic; a0 <= '1';
y : OUT std_logic a1 <= '0';
); a2 <= '0';
end component; a3 <= '0';
s0 <= '0';
signal a0: std_logic := '0'; s1 <= '1';
signal a1: std_logic := '0'; wait for 10 ns;
signal a2: std_logic := '0'; a0 <= '0';
signal a3: std_logic := '0'; a1 <= '1';
signal s0: std_logic := '0'; a2 <= '0';
signal s1: std_logic := '0'; a3 <= '0';
signal y: std_logic; s0 <= '1';
s1 <= '0';
begin wait for 10 ns;
uut : mux_4_1 a0 <= '0';
port map ( a1 <= '0';
a0 => a0, a2 <= '1';
a1 => a1, a3 <= '0';
a2 => a2, s0 <= '1';
a3 => a3, s1 <= '1';
s0 => s0, wait for 10 ns;
s1 => s1, a0 <= '0';
y => y a1 <= '0';
); a2 <= '0';
a3 <= '1';
s0 <= '0';
s1 <= '1';
wait for 10 ns;
end process;
end Behavioral;
 c) Simulation

V. Port demi-add :
1. Schéma et table de vérité :

a b sum carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

2. Code :
a) Code de composant
library IEEE;
use IEEE.std_logic_1164.all;

entity half_adder is
port (
a, b : IN std_logic;
sum, carry : OUT std_logic
);
end half_adder;
architecture dataflow of half_adder is
begin
sum <= a xor b;
carry <= a and b;
end dataflow;

b) Code test Bench

library IEEE; process
use IEEE.std_logic_1164.all; begin
wait for 10 ns;
entity half_adder_tb is a <= '0';
end half_adder_tb; b <= '0';
wait for 10 ns;
architecture Behavioral of half_adder_tb is a <= '0';
component half_adder is b <= '1';
port ( a,b : in std_logic; wait for 10 ns;
sum : out std_logic; a <= '1';
carry : out std_logic ); b <= '0';
end component; wait for 10 ns;
a <= '1';
signal a: std_logic := '0'; b <= '1';
signal b: std_logic := '0'; wait for 10 ns;
signal sum: std_logic; end process;
signal carry : std_logic; end Behavioral;
begin
uut : half_adder
port map (a => a, b => b, sum => sum,
carry => carry );

c) Simulation
VI. Port Full add :
1. Schéma et table de vérité :

a b c_in sum c_out

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
 2. Code :
a) Code de composant
library IEEE;
use IEEE.std_logic_1164.all;

entity full_adder is
port (
a, b, c_in : IN std_logic;
sum, c_out : OUT std_logic
);
end full_adder;

architecture dataflow of full_adder is

begin
sum <= a xor b xor c_in;
c_out <= (a and b) or (c_in and b) or (a and c_in);
end dataflow;

b) Code test Bench

library IEEE; process
use IEEE.std_logic_1164.all; begin
entity full_adder_tb is wait for 10 ns;
end full_adder_tb; a <= '0';
b <= '0';
architecture Behavioral of full_adder_tb is c_in <= '0';
component full_adder is wait for 10 ns;
port ( a <= '0';
a : in std_logic; b <= '0';
b : in std_logic; c_in <= '1';
c_in : in std_logic; wait for 10 ns;
sum : out std_logic; a <= '0';
c_out : out std_logic b <= '1';
); c_in <= '0';
end component; wait for 10 ns;
a <= '0';
signal a: std_logic := '0'; b <= '1';
signal b: std_logic := '0'; c_in <= '1';
signal c_in: std_logic := '0'; wait for 10 ns;
signal sum: std_logic; a <= '1';
signal c_out: std_logic; b <= '0';
c_in <= '0';
 begin wait for 10 ns;
uut : full_adder a <= '1';
port map ( a => a, b => b, c_in => c_in, b <= '0';
sum => sum, c_out => c_out ); c_in <= '1';
wait for 10 ns;
a <= '1';
b <= '1';
c_in <= '0';
wait for 10 ns;
a <= '1';
b <= '1';
c_in <= '1';
wait for 10 ns;
end process;
end Behavioral;

c) Simulation

VII. Exercice :
 1. Code :
a) Code de composant
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity div_freq is
generic (
DIV_FR: integer := 20;
TAILLE_PULSE: integer := 10;
N: integer := 45);
port (
clk, reset: in std_logic;
start_fb: in std_logic;
clk_bit: out std_logic
);
end div_freq;

architecture Behavioral of div_freq is

signal cnt: integer range 0 to DIV_FR ;

begin
process (clk, reset)
begin
if (reset = '1') then
cnt <= 0;
clk_bit <= '0';
elsif rising_edge(clk) then
if start_fb = '1' then
cnt <= cnt + 1;
if cnt = TAILLE_PULSE-1 then
clk_bit <= '1';
elsif cnt = DIV_FR-1 then
clk_bit <= '0';
cnt <= 0;
end if;
end if;
end if;
end process;
end Behavioral;
 b) Code test Bench
library IEEE; begin
use IEEE.STD_LOGIC_1164.ALL; process (clk, reset)
use IEEE.numeric_std.ALL; begin
if (reset = '1') then
entity div_freq is cnt <= 0;
generic ( clk_bit <= '0';
DIV_FR: integer := 20; elsif rising_edge(clk) then
TAILLE_PULSE: integer := 10; if start_fb = '1' then
N: integer := 45 cnt <= cnt + 1;
); if cnt = TAILLE_PULSE-1 then
port ( clk_bit <= '1';
clk, reset: in std_logic; elsif cnt = DIV_FR-1 then
start_fb: in std_logic; clk_bit <= '0';
clk_bit: out std_logic cnt <= 0;
); end if;
end div_freq; end if;
end if;
architecture Behavioral of div_freq is end process;
signal cnt: integer range 0 to DIV_FR ; end Behavioral;

c) Simulation