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Module GE4.2 :
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Applications des DSP
n Automatisation n Biomédical
Ø Commande de Ø Équipements de monitoring
machines Ø Signaux biophysiques
Ø Contrôle de moteurs Ø ElectroEncéphaloGramme (EEG)
Ø Robots Ø ElectroCardioGramme (ECG)
Ø Radiographie
n Electronique Automobile
Ø Contrôle du moteur n Instrumentation
Ø Assistance au freinage Ø Analyseurs de spectre
Ø Aide à la navigation Ø Générations de fonctions
Ø Commandes vocales Ø Analyseurs de régimes
transitoires
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TABLE 1-1. Common DSP Algorithms and Typical Applications
Speech encryption and Digital cellular telephones, personal communications systems, digital cordless
decryption telephones, secure communications
Hi-fi audio encoding Consumer audio, consumer video, digital audio broadcast, professional audio,
and decoding multimedia computers
Modem algorithms Digital cellular telephones, personal communications systems, digital cordless
telephones, digital audio broadcast, digital signaling on cable TV, multimedia comput-
ers, wireless computing, navigation, data/facsimile modems, secure communications
Audio equalization Consumer audio, professional audio, advanced vehicular audio, music
Ambient acoustics
Consumer audio, professional audio, advanced vehicular audio, music
emulation
Audio mixing and
Professional audio, music, multimedia computers
editing
Sound synthesis Professional audio, music, multimedia computers, advanced user interfaces
Image compositing Multimedia computers, consumer video, advanced user interfaces, navigation
Algorithm Equation
M
Finite Impulse Response Filter ∑a
y ( n) =
k =0
k x( n − k )
M N
Infinite Impulse Response Filter ∑a
y ( n) =
k =0
k x ( n − k )+ ∑ b y (n − k )
k =1
k
N
Convolution ∑ x ( k ) h( n − k )
y ( n) =
k =0
N −1
Discrete Fourier Transform X (k ) = ∑ x(n) exp[− j(2π / N )nk ]
n =0
N −1
⎡π ⎤
Discrete Cosine Transform F (u ) = ∑ c(u ). f ( x).cos ⎢ u(2 x + 1)⎥
x =0 ⎣ 2N ⎦
rchitecture and instruction set optimized for power efficient performance9. For signal
Lesa common
processing intensive systems, algorithmes de(Figure
choice is a DSP TNS 1.14).
Figure 1.14 Many of today’s complex algorithms are composed from basic function signal processing
locks that DSPs are very efficient at computing
Many of today’s complex algorithms are composed from
As an example of afunction
basic low power DSPprocessing
signal solution, consider a solid-state
blocks that DSPs are audio
veryplayer
ike the one shown in Figure
efficient 1.15. This system requires a number of DSP-centric
at computing
lgorithms to perform the signal processing necessary to produce high fidelity music
quality sound. Figure 1.16 shows some of the important algorithms required in this
Implémentation d’algorithmes
LE DOMAINE
Circuits
Models Algorithmes Architectures Électroniques
mathématiques Technologies
Adéquation
Implémentation
Application
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Utilisation prototype
reducing system costs and affording higher levels of system integration. Recently, FPGA
been gaining considerable attention in high-performance DSP applications, and are emerg
Digital Signal Processing Hardware
coprocessors [14] for standard digital signal processors that need specific accelerators. In
cases, FPGAs work in conjunction with digital signal processors for integrating pre- and
processing functions. These devices are hardware reconfigurable, and thus allow s
designers to optimize the hardware architecture for implementing algorithms that require
1.performance
Special-purpose
and lower(custom)
productionchips
cost. such as application-specific
In addition, designers can implement high-perfor
integrated
complex DSP circuit (ASICs).
functions using a fraction of the device, and use the rest of the device to imp
2.system
Field-programmable gate arrays
logic or interface functions, (FPGAs).
resulting in both lower costs and higher system integ
3. General-purpose microprocessors or microcontrollers (mP/mC).
4. Digital Signal Processors.
Table 1.1 Summary of DSP hardware implementations
ASIC FPGA mP/mC Digital signal Digital
processor processo
HW acce
Flexibility None Limited High High Medium
Design time Long Medium Short Short Short
Power consumption Low Low–medium Medium–high Low–medium Low–med
Performance High High Low–medium Medium–high High
Development cost High Medium Low Low Low
Production cost Low Low–medium Medium–high Low–medium Medium
The main trade-offs in the programmable vs. fixed-
function decision; flexibility and power.
xvi Introduction
µP
Power
Consumption DSP
FPGA
ASIC
Application Flexibility
Waiting Time
Processing Time
n n+1
Sample Time
Waiting Time ≥ 0
I. Introduction
Besoins en TNS
Real-time processing
! Contraintes de temps réel :
# Exemple : taux d’échantillonnage 48kHz
Théorème de Shannon
& Te = 20.833 µs
Arrivée de Arrivée de
l’échantillon x(n) l’échantillon x(n+1)
t
t0 t0+Te
Temps de traitement T
doit être <Te
Spécificités des DSP
a 24-bit, fixed-point
Yl
processor).
56
Accumulators ---
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Caractéristiques classiques des DSP
n Codage de données (virgule fixe / virgule flottante)
n Architecture
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Caractéristiques classiques des DSP III. Architecture des DSP
Format
Représentation de
des données
nombres
Les valeurs traitées (coefficients, échantillons...) sont
représentées
! sous(coefficients,
Les valeurs traitées les deuxéchantillons…)
formes suivantes :
sont représentées sous
les deux formes suivantes :
DSP à
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Le codage des nombres entiers
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Entiers signés : Format complément à 2
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Représentation de Nombres Réels
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Représentation en Virgule fixe
•Aussi appelée représentation à “format fixe”
Propriétés:
Le format d’une donnée ne varie pas au cours du temps
Partie fractionnaire codée sur k bits
format Qk
Partie entière codée sur N-k bits en C2
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Représentation en Virgule Fixe
• Exemple: Q5 sur 8 bits
0 0 0 0 0 0 0 0 0
3.9375 0 1 1 1 1 1 1 0
3.96875 0 1 1 1 1 1 1 1
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Représentation en Virgule Fixe
Format Q15:
sur 16 bits, le format Q15 permet de représenter tous les
réels entre -1 et 1 avec une précision q=2-15
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Représentation des nombres : Virgule fixe
Exercices
! Codage des entiers
" Format Qk :
$ +0.5
$ +1.0
$ -1.0
$ +1/3 = 0.3333
$ -1/3 = -0.3333
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