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101 E San Fernando St, Apt 428, San Jose, CA 95112, US.


Tel: +1 (408) 859 4549. Email: shaunak.jani@students.sjsu.edu Website: shaunakjani.blogspot.com


Seeking an internship opportunity in the field of ASIC / FPGA design, testing, and verification which offers me professional growth and challenges while fulfilling corporate objectives of delivering a successful product.


MS Electrical Engineering (VLSI Design) San Jose State University

B.E. Electronics and Telecommunications Engineering University of Mumbai India


August 2011 May 2013 (Expected)

August 2006 – July 2010

GPA 3.3

Hands on Experience in RTL synthesis, gate level simulation as well as STA, using various EDA tool sets.

Expertise with Digital Circuit Design, Debug and formal Verification using Verilog HDL.

Good basic understanding of CMOS transistor circuit design fundamentals.

Good in Designing & Analyzing power, performance, and area tradeoffs in digital circuits .

Worked on Floor planning and place & route using Cadence Encounter.

Good basic understanding on ASIC / IC design flow and, CMOS physical design.

Ability to learn new technologies, team player, goal oriented and highly motivated

Languages: Verilog HDL, C, C++, learning Perl.

Tools: Synopsys VCS, Synopsys Design Vision, Modelsim , Turbo C, PCB Express, Cadence Encounter, NCverilog, Icarus Verilog.

Microprocessors & Microcontrollers: 8085, 8086, 8051 and 80196 Microcontrollers

Productivity suite: MS Office, Adobe Photoshop, Notepad++.

Operating System: Windows XP/Vista/Seven, Mac OS, Fedora, Unix.


Digital System Design using Verilog HDL


Semiconductor Devices

Probabilities, Random Variables & StochastiProcesses Linear System Theory

8051 microcontroller 8085 & 8086 Microprocessors

Digital Time Signal Processing

Computer Networking

Engineering Devices and Circuit


>>Design of TokenRing interface for I2C Bus (Ongoing)

May 2012 (Expected)

Implementing Token Ring interface for I2C Bus working for various modes of operation.

Using concept of Finite State Machine (FSM).

Implementing FIFO.

>>Design to calculate circle coordinates

February 2012

Designed a multiplier and a square root calculator in order to calculate Y in the circle equation Y^2+X^2=R^2.

Implemented a synchronous design using the concept of pipelining and flags.

Optimized the circuit to work at 200 MHz and 300 MHz.

Explored concepts of Timing closure Setup and Hold time violation.

Implemented FIFO.

Place and Route using Encounter.


>> Design and Analysis of AreaDelay and Power Delay Tradeoffs in Addition Circuits

December 2011

Designed adders using Verilog HDL at RTL level used simple ripple carry algorithm and other used carrylooked ahead algorithm.

Performed testing and verification for 16 , 32 , 48 and 64 bit adders. Simulated the designs in Synopsys VCS and synthesized and optimized using Toshiba Library in Synopsys Design Vision.

Simulated netlist to check for shortest, medium, and longest delay by passing various data inputs in the testbench, and generated the summation and carry outputs.

Performed post synthesis on the design using netlist.

Optimized the design logic until the results ensured that the slack was not violated.

>> Touchscreen based Electronic Voting Machine

May 2010

Designed and implemented a novel touch screen based voting machine, as a proposal to improve the current electoral voting mechanism in India. Project and implementation was chosen as the 3 rd best idea amongst a total of 30 class projects.

Rectified the problems occurring in current voting mechanism by exploring modern hardware circuit design techniques and implementing efficient and user friendly software.

Enabled data security and backup of the votes by building a four digit password verification and protection system. Implemented PC interface with the device using RS232 to allow timely data backups.

Programmed the microcontroller using Embedded C.


Creative head of KJSIEIT student council’s annual sports festival SCORE’2KX and KJSIEITIETE student council


Won 2nd Price at MVLU college Intra collegiate quiz contest held in August 2004.

Won 3rd Price at Royal college Inter collegiate science quiz QUEST 2004.

Member of chief organizing committee of KJSIEIT student council’s and IEEE KJSIEIT student chapter.