Ideapad 320 15IKB DG421 DG521 DG721 NM B241 NM B242 Rev 1 0 DIS

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com
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Vinafix.com
5 4 3 2 1
?
SKL_ULT
UC1B
AU53
17 DDRA_DQ[0..63] DDRA_DQ0 AL71 DDR0_CKN[0] AT53 DDRA_CLK0# 17
DDRA_DQ1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDRA_CLK0 17
DDRA_DQ2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55
DDRA_DQ3 AN69 DDR0_DQ[2] DDR0_CKP[1]
DDRA_DQ4 AL70 DDR0_DQ[3] BA56
DDRA_DQ5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDRA_CKE0 17
D DDRA_DQ6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 D
DDRA_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
DDRA_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[3]
DDRA_DQ9 AR68 DDR0_DQ[8] AU45
DDRA_DQ10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDRA_CS0# 17
DDRA_DQ11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45
DDRA_DQ12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDRA_ODT0 17
DDRA_DQ13 AR69 DDR0_DQ[12] DDR0_ODT[1]
DDRA_DQ14 AU70 DDR0_DQ[13] BA51
DDRA_DQ15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDRA_MA5 17
DDRA_DQ16 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDRA_MA9 17
DDRA_DQ17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDRA_MA6 17
DDRA_DQ18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDRA_MA8 17
DDRA_DQ19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDRA_MA7 17
DDRA_DQ20 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDRA_BG0 17
DDRA_DQ21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDRA_MA12 17
DDRA_DQ22 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDRA_MA11 17
DDRA_DQ23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDRA_ACT# 17
DDRA_DQ24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDRA_DQ25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46
DDRA_DQ26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDRA_MA13 17
DDRA_DQ27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDRA_MA15_CAS# 17
DDRA_DQ28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDRA_MA14_WE# 17
DDRA_DQ29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDRA_MA16_RAS# 17
DDRA_DQ30 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDRA_BS0# 17
DDRA_DQ31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDRA_MA2 17
DDRA_DQ32 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDRA_BS1# 17
DDRA_DQ33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDRA_MA10 17
DDRA_DQ34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDRA_MA1 17
DDRA_DQ35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDRA_MA0 17
DDRA_DQ36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDRA_MA3 17
DDRA_DQ37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDRA_MA4 17
C DDRA_DQ38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDRA_DQS#0 C
DDRA_DQ39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDRA_DQS0
DDRA_DQ40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDRA_DQS#1
DDRA_DQ41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDRA_DQS1
DDRA_DQ42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDRA_DQS#2
DDRA_DQ43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDRA_DQS2 DDRA_DQS#[0..7]
DDRA_DQ44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDRA_DQS#3 DDRA_DQS#[0..7] 17
DDRA_DQ45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDRA_DQS3 DDRA_DQS[0..7]
DDRA_DQ46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDRA_DQS#4 DDRA_DQS[0..7] 17
DDRA_DQ47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDRA_DQS4
DDRA_DQ48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDRA_DQS#5
DDRA_DQ49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDRA_DQS5
DDRA_DQ50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDRA_DQS#6
DDRA_DQ51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDRA_DQS6
DDRA_DQ52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDRA_DQS#7
DDRA_DQ53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDRA_DQS7
DDRA_DQ54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
DDRA_DQ55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50
DDRA_DQ56 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 DDRA_ALERT# 17
DDRA_DQ57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDRA_PAR 17
DDRA_DQ58 DDR0_DQ[57]/DDR1_DQ[41] SMVREF
AY25 AY67 WIDTH:20MIL
DDRA_DQ59 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA AY68 DDR_SA_VREFCA 17
DDRA_DQ60 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ SPACING: 20MIL
BB27 DDR CH - A BA67
DDRA_DQ61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ DDR_SB_VREFCA 18
DDRA_DQ62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL
DDRA_DQ63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL
DDR0_DQ[63]/DDR1_DQ[47]
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
B B
Vinafix.com +3VALW
RC30
100K_0402_5%
2
CPU_DRAMPG_CNTL 55
+1.2V
1
C
RC3 1 2 2 QC18
1K_0402_5% B
E
3
MMBT3904WH_SOT323-3
DDR_VTT_CNTL
2
RC29 @
10K_0402_5%
1
A A
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
DG421 1.0
Date: Sunday, January 22, 2017 Sheet 5 of 60

5 4 3 2 1
5 4 3 2 1
?
SKL_ULT
UC1C
18 DDRB_DQ[0..63]
DDRB_DQ0 AF65 AN45

DDRB_DQ1 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] DDRB_CLK0# 18
AF64 AN46
DDRB_DQ2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDRB_CLK1# 18
AK65 AP45
DDRB_DQ3 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] DDRB_CLK0 18
AK64 AP46
DDRB_DQ4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDRB_CLK1 18
AF66
D DDRB_DQ5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 D
DDRB_DQ6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDRB_CKE0 18
AK67 AP55
DDRB_DQ7 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] DDRB_CKE1 18
AK66 AN55
DDRB_DQ8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDRB_DQ9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDRB_DQ10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDRB_DQ11 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDRB_CS0# 18
AH68 AY42
DDRB_DQ12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDRB_CS1# 18
AF71 BA42
DDRB_DQ13 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDRB_ODT0 18
AF69 AW42
DDRB_DQ14 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDRB_ODT1 18
AH70
DDRB_DQ15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48
DDRB_DQ16 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDRB_MA5 18
AT66 AP50
AU66 BA48
AP65 BB48
AN65 AP48
AN66 AP52
DDRB_DQ21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDRB_BG0 18
AP66 AN50
AT65 AN48
AU65 AN53
DDRB_DQ24 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDRB_ACT# 18
AT61 AN52
DDRB_DQ25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDRB_BG1 18
AU61
DDRB_DQ26 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43
DDRB_DQ27 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDRB_MA13 18
AN60 AY43
DDRB_DQ28 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDRB_MA15_CAS# 18
AN61 AY44
DDRB_DQ29 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDRB_MA14_WE# 18
AP61 AW44
DDRB_DQ30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDRB_MA16_RAS# 18
AT60 BB44
DDRB_DQ31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDRB_BS0# 18
AU60 AY47
AU40 BA44
DDRB_DQ33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDRB_BS1# 18
AT40 AW46
AT37 AY46
AU37 BA46
AR40 BB46
DDRB_DQ37 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] DDRB_MA3 18
C AP40 BA47 C
DDRB_DQ38 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDRB_MA4 18
AP37
DDRB_DQ39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDRB_DQS#0
DDRB_DQ40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDRB_DQS0
DDRB_DQ41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDRB_DQS#1
DDRB_DQ42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDRB_DQS1
DDRB_DQ43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDRB_DQS#2
DDRB_DQ44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDRB_DQS2
DDRB_DQ45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDRB_DQS#3 DDRB_DQS#[0..7]
DDRB_DQ46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] DDRB_DQS3 DDRB_DQS#[0..7] 18
AR30 AR60
DDRB_DQ47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDRB_DQS#4 DDRB_DQS[0..7]
DDRB_DQ48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] DDRB_DQS4 DDRB_DQS[0..7] 18
AU27 AR38
DDRB_DQ49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDRB_DQS#5
DDRB_DQ50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDRB_DQS5
DDRB_DQ51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDRB_DQS#6
DDRB_DQ52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDRB_DQS6
DDRB_DQ53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDRB_DQS#7
DDRB_DQ54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDRB_DQS7
DDRB_DQ55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDRB_DQ56 AT22 DDR1_DQ[55] AN43
DDRB_DQ57 DDR1_DQ[56] DDR1_ALERT# DDRB_ALERT# 18
AU22 AP43
DDRB_DQ58 DDR1_DQ[57] DDR1_PAR CPU_DRAMRST#_R DDRB_PAR 18
AU21 AT13
DDRB_DQ59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP_0 RC24 1 2 121_0402_1%
DDRB_DQ60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP_1 RC25 1 2 80.6_0402_1%
DDRB_DQ61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2 RC26 1 2 100_0402_1%
DDRB_DQ62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDRB_DQ63 AN21 DDR1_DQ[62] DDR CH - B
DDR1_DQ[63]
B
Vinafix.com SKYLAKE-U_BGA1356
REV = 1
@
+1.2V
1
2
RC22
1 OF 20
470_0402_5%
?
B
RC23 1 @ 2 0_0402_5% CPU_DRAMRST#_R

17,18 CPU_DRAMRST#
1
CC1
1000P_0201_50V7-K
EMC@
2
A A
Security Classification LC Future Center Secret Data

Vinafix.com
Title
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)

Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG421
5 4 3 2 1
5 4 3 2 1
+3VALW_PCH +3VS +3VS

?
SKL_ ULT
UC1E
SPI - FLASH
3
4
4
3
SMBUS, SMLINK
SPI_CLK_R AV2 R7 PCH_SMB_CLK RPC20 RPC24
D SPI_CLK SPI_CLK_R SPI_SO_R SPI0_CLK GPP_C0/SMBCLK PCH_SMB_DATA D
2
RC1539 1 2 15_0402_5% AW3 R8 DIMM, NGFF 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%
G
44 SPI_CLK SPI_SI_R AV3 SPI0_MISO GPP_C1/SMBDATA R10 SMB_ALERT#
SPI_WP#_R AW2 SPI0_MOSI GPP_C2/SMBALERT#
SPI0_IO2
2
1
1
2
SPI_SO RC53 1 2 15_0402_5% SPI_SO_R SPI_HOLD#_R AU4 R9 SML0_CLK
44 SPI_SO SPI_CS0#_R AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SML0_DATA PCH_SMB_CLK 6 1
QC2A
SPI0_CS0# GPP_C4/SML0DATA SMB_CLK_S3 18,40
S
AU2 W1 SML0_ALERT#
D
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R AU1 SPI0_CS1# GPP_C5/SML0ALERT# 2N7002KDWH_SOT363-6
44 SPI_SI SPI0_CS2# PCH_SML1_CLK
5
W3
G
GPP_C6/SML1CLK V3 PCH_SML1_DAT
SPI_CS0# SPI_CS0#_R SPI - TOUCH GPP_C7/SML1DATA SML1_ALERT# GPU, EC, Thermal Sensor
RC51 1 @ 2 0_0402_5% AM7
44 SPI_CS0# M2 GPP_B23/SML1ALERT#/PCHHOT#
M3 GPP_D1/SPI1_CLK PCH_SMB_DATA QC2B 3 4
GPP_D2/SPI1_MISO SMB_DATA_S3 18,40
S
J4
D
V1 GPP_D3/SPI1_MOSI 2N7002KDWH_SOT363-6
V2 GPP_D21/SPI1_IO2
BOARD_ID4 M1 GPP_D22/SPI1_IO3 AY13
LPC
8 BOARD_ID4 GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 BA13 LPC_AD0 32,44
GPP_A2/LAD1/ESPI_IO1 BB13 LPC_AD1 32,44
C LINK GPP_A3/LAD2/ESPI_IO2 AY12 LPC_AD2 32,44
G3 GPP_A4/LAD3/ESPI_IO3 BA12 LPC_AD3 32,44
G2 CL_CLK GPP_A5/LFRAME#/ESPI_CS# BA11 SUS_STAT# LPC_FRAME# 32,44 1
G1 CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET# TC81@
CL_RST#
AW9 CLK_PCI_EC_R RC173 2 1 22_0402_5%
AW13 GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 CLK_PCI_TPM_R CLK_PCI_EC 44
KBRST# RC1541 2 TPM@ 1 22_0402_5%
44 KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 AW11 PM_CLKRUN# CLK_PCI_TPM 32
AY11 GPP_A8/CLKRUN# PM_CLKRUN# 32
SERIRQ
32,44 SERIRQ GPP_A6/SERIRQ
1 OF 20
SKYLAKE-U_BGA1356
REV = 1
?
@
+3V_SPI
C C
+3VS +3VALW_PCH
check CLKRUN# / SUS_STAT# signal if need to connect +3VS
RC171 1 @ 2 0_0402_5% +3VALW_PCH
RC172 1 @ 2 0_0402_5%
PM_CLKRUN# RC11 1 2 8.2K_0402_5% SMB_ALERT# 2 1 RC1562
+3V_SPI 2.2K_0402_5%
1. If support DS3, connect to +3VS and don't support EC mirror code; SERIRQ RC12 1 2 10K_0402_5%
* 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.

KBRST# RC10 1 2 10K_0402_5%
+3VALW_PCH
RPC23
SML0_CLK 4 1
KBRST# CC1255 1 2 1000P_0201_50V7-K SML0_DATA 3 2
EMC_NS@ 2.2K_0404_4P2R_5%
+3V_SPI
+3VALW_PCH
1
RC60 RC61
1K_0402_5% 1K_0402_5% SML0_ALERT# RC1564 2 @ 1 2.2K_0402_5%
Check with BIOS, SPI is Dual mode or quad mode
2
SPI_WP#_R SPI_WP#
This signal has a weak internal pull-down.
RC54 1 @ 2 15_0402_5% +3VALW_PCH +3VS 0 = LPC Is selected for EC. (Default)
Vinafix.com 1 = eSPI Is selected for EC.
SPI_HOLD#_R RC55 1 @ 2 15_0402_5% SPI_HOLD# Notes:
1. The internal pull-down is disabled after RSMRST#
de-asserts.
4
3
RPC25 2. This signal is in the primary wel

B B
Rising edge of RSMRST#
2
2.2K_0404_4P2R_5%
G
+3VALW_PCH
1
2
+3V_SPI PCH_SML1_CLK QC10A 6 1 @ SML1_ALERT# RC1569 1 @ 2 150K_0402_5% +3VS

EC_SMB_CK2 20,39,44
S
D
UC3 2N7002KDWH_SOT363-6 RC1655 1 2 150K_0402_5%

SPI_CS0#
5
1 8
G
/CS VCC
SPI_SO 2 7 SPI_HOLD#
DO (IO1) IO3 1
SPI_WP# SPI_CLK
CC8
PCH_SML1_DAT
To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be
3 6 0.1u_0201_10V6K QC10B 3 4 @ added to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#.
IO2 CLK EC_SMB_DA2 20,39,44
S
D
SPI_SI 2 (Refer to WW52_MOW)

4 5 2N7002KDWH_SOT363-6
GND DI (IO0)
W25Q64JVSSIQ_SO8
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (MISC,JTAG,SPI,LPC,SMB)

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
+3VS
+3VS
@DIS For NV and AMD GPU SKU @OPT&GC6 Only for NV GPU SKU @UMA SKU
+3VS RC1558 1 UMA@ 2 10K_0402_5% DGPU_PWROK
RC1559 2 DIS@ 1 10K_0402_5% PXS_PWREN_R 1K_0402_5% 2 DIS@ 1 RC7

PXS_PWREN 22,58 FB_GC6_EN_R
1 RC1615 2
1 RC1613 2
1 RC1611 2
1 RC1609 2
1 RC1606 2
RC1629 1 @ 2 10K_0402_5% @ 15@ @ DIS@ PX@ @
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
RC1641 1 @ 2 10K_0402_5% PXS_RST#_R RC8 1 @ 2 0_0402_5%
RC1608
PXS_RST# 20 GPU_EVENT#
RC1630 1 GC6@ 2 10K_0402_5%
GPU_EVENT# 20
Reserve for GPU sequence
RC1557 1 DIS@ 2 10K_0402_5% PXS_RST#_R RC1637 1 OPT@ 2 10K_0402_5% FB_GC6_EN_R
FB_GC6_EN_R 20
1
CC1259 1 2 0.01U_0201_10V6K PXS_RST# RC1638 1 @ 2 10K_0402_5% GPU_EVENT# BOARD_ID0
DIS@ BOARD_ID1
BOARD_ID2
D 9 BOARD_ID2 BOARD_ID3 D
DGPU_PWROK BOARD_ID4
DGPU_PWROK 24,55,57,58 7 BOARD_ID4 BOARD_ID5
10K_0402_5%
1 RC1616 2
1 RC1614 2
1 RC1612 2
1 RC1610 2
1 RC1607 2
1 RC123 2
14@ @ UMA@ OPT@ @
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
SKL_ ULT ?
UC1F
LPSS ISH
AN8 P2 BOARD_ID0
AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 BOARD_ID1
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4
RC1561 1 @ 2 2.2K_0402_5% GPP_B18 AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 BOARD_ID3
+3VS +3VS GPP_B18/GSPI0_MOSI GPP_D12
AM5 M4 BOARD_ID6
RPC28 PCH_CMOS_ON# AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3 BOARD_ID5
1 4 PCH_I2C_SDA0 33 PCH_CMOS_ON# AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
2 3 PCH_I2C_SCL0 RC1563 1 @ 2 2.2K_0402_5% GPP_B22 AN5 GPP_B21/GSPI1_MISO N1 BOARD_ID7 Board ID Description Stuff R
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2 BOARD_ID8
2.2K_0404_4P2R_5% AB1 GPP_D8/ISH_I2C1_SCL 00 14" RC1616 RC1614
40 UART_RX_DEBUG AB2 GPP_C8/UART0_RXD AD11
Board_ID[0:1] 01 15" RC1616 RC1613
PCH_TP_INT# 40 UART_TX_DEBUG GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
RC1658 2 1 10K_0402_5% W4 AD12
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C11/UART0_CTS# 10 17" RC1615 RC1614
10/ 25 SIT For I2C T/ P Function wei TC206 1 @ PXS_PWREN_R AD1 U1
TC207 1 @ PXS_RST#_R AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 11 Reserved RC1615 RC1613
+3VS TC208 1 @ DGPU_PWROK AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
1 FB_GC6_EN_R AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 0 Reserved RC1612
TC204 @
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
Board_ID2
AC1 1 Reserved RC1611
RC1656 1 @ 2 0_0402_5% PCH_I2C_SDA0 U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2
45 TP_I2C_SDA0
RC1657 1 2 0_0402_5% PCH_I2C_SCL0 U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 GPU_EVENT# @1 0 UMA RC1610
PCH_CMOS_ON# 45 TP_I2C_SCL0
@
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS#
TC205 Board_ID3
RC1595 2 @ 1 10K_0402_5% AB4
RC1596 2 1 10K_0402_5% PCH_WLAN_OFF# PCH_WLAN_OFF# U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS# PCH_TP_INT# 45 1 DIS RC1609
PCH_BT_OFF# 40 PCH_WLAN_OFF# PCH_BT_OFF# GPP_C18/I2C1_SDA
C RC1597 2 1 10K_0402_5% U9 AY8 C
40 PCH_BT_OFF# GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 0 NV GPU RC1607
GPP_A19/ISH_GP1
Board_ID4
double check if need the pull up resisor AH9 BB7
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7 1 AMD GPU RC1608
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7
AH11 GPP_A22/ISH_GP4 AW7 0 Reserved RC123
GPP_F6/I2C3_SDA GPP_A23/ISH_GP5
Board_ID5
AH12 AP13
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6 1 Reserved RC1606
+3VALW_PCH +3VS AF11
AF12 GPP_F8/I2C4_SDA
RC1600 1 @ 2 1K_0402_5% GPP_F9/I2C4_SCL +3VS
RC47 1 @ 2 1K_0402_5% HDA_SDOUT SKYLAKE-U_BGA1356 1 OF 20
* REV = 1
@
?
DIMM_ONLY@ DIMM_ONLY@ 520Z@ @ @
HDA_SDO This signal has a weak internal pull-down.
2 RC1631 1
2 RC1632 1
2 RC1633 1
2 RC1639 1
2 RC1651 1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This strap
should only be asserted high during external pull-up in
manufacturing/debug environments ONLY.
BOARD_ID6
BOARD_ID7
BOARD_ID8
BOARD_ID9
BOARD_ID10
UC1G SKL_ ULT ?
@ @ 320G@ @ @
AUDIO
HDA_SDIN0
2 RC1634 1
2 RC1635 1
2 RC1636 1
2 RC1640 1
2 RC1652 1
For EMI
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
RC43 1 2 33_0402_5% HDA_SYNC BA22
1 30 HDA_SYNC_AUDIO HDA_BCLK HDA_SYNC/I2S0_SFRM
CC7 Vinafix.com RC42 1 2 33_0402_5% AY22
10P_0201_50V8F 30 HDA_BITCLK_AUDIO HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
SDIO/SDXC
EMC_NS@ HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
2 30 HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
RC44 1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
30 HDA_RST_AUDIO# J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
B
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12 B
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11

I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
HDA_SDOUT GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7
Board ID Description Stuff R
RC45 1 2 33_0402_5% BB9
30 HDA_SDOUT_AUDIO GPP_A16/SD_1P8_SEL
RC46 1 @ 2 0_0402_5% Samsung 8Gb
44 ME_FLASH BOARD_ID10 H5 AB7 SD_RCOMP
BOARD_ID9 GPP_D19/DMIC_CLK0 SD_RCOMP
00 2400 MT/s RC1634 RC1635
D7
GPP_D20/DMIC_DATA0
Hynix 8Gb
1
D8 AF13 01 2400 MT/s RC1634 RC1632
C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
RC49 Board_ID
PCH_BEEP
200_0402_1% [6,7] Micron 8Gb
+3VS AW5 10 2400 MT/s RC1631 RC1635
30 PCH_BEEP GPP_B14/SPKR
2
1 2 2.2K_0402_5% PCH_BEEP
RC14 @
1 OF 20
11 SO-DIMM Only RC1631 RC1632
SKYLAKE-U_BGA1356
REV = 1 ?
@ 0 320G RC1636
Board_ID8
Default When 1 520Z RC1633
Pin Name Strap Description Configuration Value Sampled
Internal PD 0 Reserved RC1640
0 = Disable “ Top Swap” Board_ID9
SPKR /
GPP_B14
Top Swap
Override
mode. (Default)
1 = Enable “ Top Swap”
* 0 Rising edge
of PCH_PWROK 1 Reserved RC1639
mode.
Internal PD 0 Reserved RC1652
GSPI0_MOSI 0 = Disable “ No Reboot” Rising edge Board_ID10
/GPP_B18 No Reboot mode. (Default)
1 = Enable “ No Reboot”
* 0 of PCH_PWROK
1 Reserved RC1651
A A
mode
GSPI1_MOSIBoot BIOS Internal PD Rising edge

/GPP_B22 Strap Bit
BBS
0 = SPI (Default)
1 = LPC
* 0 of PCH_PWROK
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (LPSS,ISH,AUDIO,SDIO)

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
@DIS For NV and AMD GPU SKU

20 PCIE_CRX_GTX_N[0..3]
D D
20 PCIE_CRX_GTX_P[0..3]
?
UC1H SKL_ULT
20 PCIE_CTX_C_GRX_N[0..3]
20 PCIE_CTX_C_GRX_P[0..3] SSIC / USB3

PCIE/USB3/SATA
H8 USB30_RX_N1
USB3_1_RXN USB30_RX_P1 USB30_RX_N1 41
G8
PCIE_CRX_GTX_N0 H13
PCIE1_RXN/USB3_5_RXN
USB3_1_RXP
USB3_1_TXN
C13 USB30_TX_N1 USB30_RX_P1
USB30_TX_N1
41
41
LEFT USB3.0
PCIE_CRX_GTX_P0 G13 D13 USB30_TX_P1
PCIE_CTX_C_GRX_N0 PCIE_CTX_GRX_N0 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB30_TX_P1 41
0.22U_0201_6.3V6-K DIS@ 1 2 CC16 B17
PCIE_CTX_C_GRX_P0 0.22U_0201_6.3V6-K DIS@ 1 2 CC14 PCIE_CTX_GRX_P0 A17 PCIE1_TXN/USB3_5_TXN J6 USB30_RX_N2
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB30_RX_P2 USB30_RX_N2 43
H6
PCIE_CRX_GTX_N1 USB3_2_RXP/SSIC_1_RXP USB30_TX_N2 USB30_RX_P2 43
G11 B13
PCIE_CRX_GTX_P1 F11 PCIE2_RXN/USB3_6_RXN
PCIE2_RXP/USB3_6_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
A13 USB30_TX_P2 USB30_TX_N2
USB30_TX_P2
43
43
Type-C
PCIE_CTX_C_GRX_N1 0.22U_0201_6.3V6-K DIS@ 1 2 CC15 PCIE_CTX_GRX_N1 D16
PCIE_CTX_C_GRX_P1 0.22U_0201_6.3V6-K DIS@ 1 2 CC17 PCIE_CTX_GRX_P1 C16 PCIE2_TXN/USB3_6_TXN J10 USB30_RX_N3
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN USB30_RX_P3 USB30_RX_N3 41
H10
DGPU PCIE_CRX_GTX_N2 H16 USB3_3_RXP/SSIC_2_RXP B15 USB30_TX_N3 USB30_RX_P3 41
PCIE_CRX_GTX_P2 G16 PCIE3_RXN
PCIE3_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
A15 USB30_TX_P3 USB30_TX_N3
USB30_TX_P3
41
41
LEFT USB3.0
PCIE_CTX_C_GRX_N2 0.22U_0201_6.3V6-K DIS@ 1 2 CC18 PCIE_CTX_GRX_N2 D17
PCIE_CTX_C_GRX_P2 0.22U_0201_6.3V6-K DIS@ 1 2 CC19 PCIE_CTX_GRX_P2 C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
PCIE_CRX_GTX_N3 G15 USB3_4_RXP C15
PCIE_CRX_GTX_P3 F15 PCIE4_RXN USB3_4_TXN D15
PCIE_CTX_C_GRX_N3 0.22U_0201_6.3V6-K DIS@ 1 2 CC20 PCIE_CTX_GRX_N3 B19 PCIE4_RXP USB3_4_TXP
PCIE_CTX_C_GRX_P3 0.22U_0201_6.3V6-K DIS@ 1 2 CC21 PCIE_CTX_GRX_P3 A19 PCIE4_TXN AB9 USB20_N1
PCIE4_TXP USB2N_1 USB20_P1 USB20_N1 41
AB10
37 PCIE_PRX_DTX_N5
PCIE_PRX_DTX_N5 F16
PCIE5_RXN
USB2P_1 USB20_P1 41 LEFT USB3.0
PCIE_PRX_DTX_P5 E16 AD6 USB20_N2
37 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE5_RXP USB2N_2 USB20_P2 USB20_N2 43
CC1262 1 2 0.1u_0201_10V6K C19 AD7
LAN 37
37
PCIE_PTX_C_DRX_N5
PCIE_PTX_C_DRX_P5
CC1261 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_P5 D19 PCIE5_TXN USB2P_2 USB20_P2 43 Type-C
C PCIE5_TXP AH3 USB20_N3 C
PCIE_PRX_DTX_N6 USB2N_3 USB20_P3 USB20_N3 41
G18 AJ3
40
40
PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6
PCIE_PRX_DTX_P6 F18 PCIE6_RXN
PCIE6_RXP
USB2P_3 USB20_P3 41 LEFT USB3.0
CC1264 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_N6 D20 AD9 USB20_N4
WLAN 40 PCIE_PTX_C_DRX_N6
CC1263 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_P6 C20 PCIE6_TXN USB2N_4 AD10 USB20_P4 USB20_N4 45
40 PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 45 Finger Print
SATA_PRX_DTX_N0 F20 AJ1 USB20_N5
42 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 30
E20 AJ2
42 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 B21 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 30 Card reader
SATA HDD 42 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 A21 PCIE7_TXN/SATA0_TXN
PCIE7_TXP/SATA0_TXP
USB2
USB2N_6
AF6 USB20_N6
USB20_N6 33
42 SATA_PTX_DRX_P0 AF7 USB20_P6
SATA_PRX_DTX_N1 G21
PCIE8_RXN/SATA1A_RXN
USB2P_6 USB20_P6 33 Touch panel
42 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 F21 AH1 USB20_N7
42 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_P7 USB20_N7 40
D21 AH2
SATA ODD 42 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 C21 PCIE8_TXN/SATA1A_TXN
PCIE8_TXP/SATA1A_TXP
USB2P_7 USB20_P7 40 BT
42 SATA_PTX_DRX_P1 AF8 USB20_N8
USB2N_8 USB20_P8 USB20_N8 33
E22 AF9
E23 PCIE9_RXN
PCIE9_RXP
USB2P_8 USB20_P8 33 Camera
B23 AG1
A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
D23 PCIE10_RXP USB2P_10
C23 PCIE10_TXN AB6 USB2_COMP RC118 2 1 113_0402_1%
PCIE10_TXP USB2_COMP USB2_ID
USBRBIAS
AG3 RC1626 1 @ 2 0_0402_5% Width 20Mil
RC119 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC1627 1 2 1K_0402_5%
PCIE_RCOMPP PCIE_RCOMPN USB2_VBUSSENSE Space 15Mil
E5 Length 500Mil
PCIE_RCOMPP A9 USB_OC0#
Optane Memory
B
Vinafix.com PCIE_RCOMPN and PCIE_RCOMPP
Trace Width: 12-15mil
Differential between RCOMPP/RCOMPN
PAD @
PAD @
TC20
TC19
1
1
XDP_PRDY#
XDP_PREQ#
PIRQA#
D56
D61
BB11
E28
E27
D24
C24
E30
F30
A25
B25
PROC_PRDY#
PROC_PREQ#
GPP_A7/PIRQA#
PCIE11_RXN/SATA1B_RXN
PCIE11_RXP/SATA1B_RXP
PCIE11_TXN/SATA1B_TXN
PCIE11_TXP/SATA1B_TXP
PCIE12_RXN/SATA2_RXN
PCIE12_RXP/SATA2_RXP
PCIE12_TXN/SATA2_TXN
PCIE12_TXP/SATA2_TXP
SKYLAKE-U_BGA1356 1 OF 20
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E8/SATALED#
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
USB_OC1#
USB_OC2#
USB_OC3#
GPP_E4
GPP_E5
SATA0GP
ODD_DETECT#
SATA2GP
BOARD_ID2
1
USB_OC1#
@ PAD
BOARD_ID2
TC202
41
8
RC1628 1 @ 2 0_0402_5%
2016/05/03: Implement as Power Button

function for Windows RedStone support
EC_SMI# 44
B
REV = 1 ?
@
+3VS
+3VALW_PCH
+3VS GPP_E4 RC1617 2 @ 1 10K_0402_5%

RPC2 RPC17
1 8 ODD_DETECT# USB_OC0# 8 1
2 7 SATA0GP USB_OC1# 7 2
3 6 SATA2GP USB_OC3# 6 3
4 5 PIRQA# USB_OC2# 5 4 USB_OC2# RC1654 1 @ 2 0_0402_5%
TYPE_C_OCP# 43
10K_0804_8P4R_5% 10K_0804_8P4R_5%
8/ 24 Reserve TYPE_C_OCP# to CPU USB_OC2# wei
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCIE,SATA,USB3,USB2)

Custom 1.0
5 4 3 2 1
5 4 3 2 1
UC1I
SKL_ULT ?
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D D36 CSI2_DN2 CSI2_CLKN2 D29 D
A38 CSI2_DP2 CSI2_CLKP2 B26
check the Pull up resistor CSI2_DN3 CSI2_CLKN3
B38 A26
CSI2_DP3 CSI2_CLKP3
+3VS C31 E13 CSI2_COMP RC73 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
RPC4 D33 CSI2_DN5
1 8 LAN_CLKREQ# A31 CSI2_DP5 EMMC
2 7 WLAN_CLKREQ# B31 CSI2_DN6 AP2

3 6 A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
4 5 GPU_CLKREQ# B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
10K_0804_8P4R_5% A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP RC50 1 2 200_0402_1%
EMMC_RCOMP
REV = 1 ?
@
@DIS For NV and AMD GPU SKU UC1J SKL_ULT ?

SUSCLK RC95 1 @ 2 1K_0402_5%
C CLOCK SIGNALS C
CLK_PCIE_GPU# D42 DIFFCLK_BIASREF RC1555 1 2 60.4_0402_1%

20 CLK_PCIE_GPU# CLK_PCIE_GPU CLKOUT_PCIE_N0
PCIE CLK0 DGPU C42 Cannonlake@
20 CLK_PCIE_GPU GPU_CLKREQ# CLKOUT_PCIE_P0
AR10
20 GPU_CLKREQ# GPP_B5/SRCCLKREQ0#
B42
A42 CLKOUT_PCIE_N1 F43 CLK_PCIE_XDP# 1 TC85 @
Optane memory CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N CLK_PCIE_XDP
AT7 E43 1 TC87 @
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
CLK_PCIE_WLAN# D41 BA17 SUSCLK
40 CLK_PCIE_WLAN# CLK_PCIE_WLAN CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK 40
PCIE CLK5 WLAN C41
40 CLK_PCIE_WLAN WLAN_CLKREQ# CLKOUT_PCIE_P2 XTAL24_IN
AT8 E37
40 WLAN_CLKREQ# GPP_B7/SRCCLKREQ2# XTAL24_IN XTAL24_OUT
E35 +VCCCLK5
D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 DIFFCLK_BIASREF RC72 1 2 2.7K_0402_1%
AT10 CLKOUT_PCIE_P3 XCLK_BIASREF
GPP_B8/SRCCLKREQ3# AM18 RTC_X1
CLK_PCIE_LAN# B40 RTCX1 AM20 RTC_X2
37 CLK_PCIE_LAN# CLK_PCIE_LAN CLKOUT_PCIE_N4 RTCX2
PCIE CLK4 LAN A40
37 CLK_PCIE_LAN LAN_CLKREQ# CLKOUT_PCIE_P4 SRTC_RST#
AU8 AN18
37 LAN_CLKREQ# GPP_B9/SRCCLKREQ4# SRTCRST# RTC_RST#
AM16
E40 RTCRST#
E38 CLKOUT_PCIE_N5
AU7 CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#
Vinafix.com 1 OF 20 1
SKYLAKE-U_BGA1356 CC3
REV = 1 ? VCCRTC 1U_0402_6.3V6K
@
B 2 B
RC33 1 2 20K_0402_1% SRTC_RST#
RC34 1 2 20K_0402_1% RTC_RST# RC1624 1 @ 2 0_0402_5%
EC_RTC_RST# 44
1
CC6 JCMOS1
1U_0402_6.3V6K SHORT PADS
@
2
2
RC71 2 1 1M_0402_5% RTC_X1
YC2
RC32 2 1 10M_0402_5% RTC_X2
2 3 RC240 1 2 0_0201_5% XTAL24_OUT
GND1 OSC2 YC1
XTAL24_IN RC241 1 2 0_0201_5% 1 4 1 2
OSC1 GND2
2 32.768KHZ_9PF_X1A0001410002 2
1 24MHZ_6PF_7V24000032 1
CC12 CC11 CC4 CC5
3.3P_0402_50V8-C 2.7P_0402_50V9-B 7P_0402_50V8J 7P_0402_50V8J
1 1
2 2
when single end external clock generator used,
this pin should be grounded
need to use 38.4MHz (30ohm) for Cannonlake-u

A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CSI2,EMMC,CLOCK)

Custom 1.0
5 4 3 2 1
5 4 3 2 1
?
UC1K SKL_ULT
SYSTEM POWER MANAGEMENT

AT11
GPP_B12/SLP_S0# AP15 PM_SLP_S3#_R RC96 1 @ 2 0_0402_5%
PLT_RST#_R GPD4/SLP_S3# PM_SLP_S4#_R PM_SLP_S3# 13,44
RC84 1 @ 2 0_0402_5% AN10 BA16 RC97 1 @ 2 0_0402_5%
20,32,37,40,44 PLT_RST# SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S4# 44
B5 AY16
D RC85 1 @ 2 0_0402_5% PCH_RSMRST#_R AY17 SYS_RESET# GPD10/SLP_S5# D
44 EC_RSMRST# RSMRST# PM_SLP_SUS#_R
PAD @ TC21 AN15 RC89 1 @ 2 0_0402_5%
CPU_PROCPWRGD SLP_SUS# PM_SLP_SUS# 44
1 A68 AW15
VCCST_PWRGD_R RC93 1 2 60.4_0402_1% VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17 Reserve for DS3
VCCST_PWRGD GPD9/SLP_WLAN# AN16
RC139 1 @ 2 0_0402_5% SYS_PWROK_R B6 GPD6/SLP_A#
44 SYS_PWROK PCH_PWROK_R SYS_PWROK PBTN_OUT#_R
RC126 1 @ 2 0_0402_5% BA20 BA15 RC87 1 @ 2 0_0402_5%
44 PCH_PWROK PCH_DPWROK_R PCH_PWROK GPD3/PWRBTN# AC_PRESENT_R PBTN_OUT# 44
BB20 AY15
DSW_PWROK GPD1/ACPRESENT AU13 BATLOW#
RC86 1 @ 2 0_0402_5% SUSWARN#_R AR13 GPD0/BATLOW#
44 SUSWARN# SUSACK#_R GPP_A13/SUSWARN#/SUSPWRDNACK
RC79 1 @ 2 0_0402_5% AP11 VCCRTC
44 SUSACK# GPP_A15/SUSACK#
Reserve for DS3 AU11 PME# @1 TC89
RC91 1 @ 2 0_0402_5% WAKE# BB15 GPP_A11/PME# AP16 INTVRMEN RC41 2 1 330K_0402_5%
37,40,44 PCIE_WAKE# PCH_LAN_WAKE# AM15 WAKE# INTRUDER#
AW17 GPD2/LAN_WAKE# AM10
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11
GPD7/RSVD GPP_B2/VRALERT#
REV = 1 ?
@
RC88 1 @ 2 0_0402_5% AC_PRESENT_R

44 AC_PRESENT
+3VALW
AC_PRESENT_R
1
RC74 1 2 10K_0402_5% D
2 QC8
44 ACIN#
RC75 1 2 8.2K_0402_5% BATLOW# G 2N7002KW_SOT323-3
C @ C
RC76 2 1 1K_0402_5% WAKE# Follow CRB change to 1kohm S
3
RC90 1 2 10K_0402_5% PCH_LAN_WAKE#
+3VALW_PCH +3VALW +VCCST_CPU +VCCSTG
SUSWARN#_R
2
RC78 1 @ 2 10K_0402_5%
2
RC137 RC1554
RC136 1K_0402_5% 1K_0402_5%
10K_0402_5% @
+3VS @
1
VCCST_PWRGD_R
1
RC80 1 2 10K_0402_5% SYS_RESET#
3
D
6
D 5 QC6B 2
RC138 1 @ 2 0_0402_5% 2 QC6A G 2N7002KDWH_SOT363-6 CC140
44 EC_VCCST_PWRGD G 2N7002KDWH_SOT363-6 @ 1000P_0201_50V7-K
@ S EMC_NS@
1 1
4
1000P_0201_50V7-K 1 2 CC1254 PCH_RSMRST#_R CC46 S
1
EMC_NS@ 0.01U_0201_25V6-K
Stuff to fix Reset&PWRGD test fail issue EMC_NS@
0.01U_0201_10V6K 1 2 CC104 PCH_PWROK 2
B
Vinafix.com
1000P_0201_50V7-K 1
47P_0201_25V8-J
0.01U_0201_10V6K
1
1
2 CC103
EMC_NS@
2 CC101
2 CC1260
PCH_DPWROK_R
SYS_PWROK
EC_RSMRST#
Add to fix Reset&PWRGD test fail issue
1
2
RPC21
8
7
PCH_RSMRST#_R
PCH_PWROK
SYS_PWROK
PM_SLP_S3#
RC1599 1
DC4 1
@
RB751V-40_SOD323-2
2 0_0402_5%
2 @
B
3 6
4 5
10K_0804_8P4R_5%
RC182 1 @ 2 0_0402_5% EC_RSMRST#
PCH_DPWROK_R RC81 1 @ 2 0_0402_5% DPWROK_EC 44

100K_0402_5% 2 1 RC92 PLT_RST#_R Reserve for DS3
100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R
A A
100P_0201_25V8J 1 2 CC1294 PLT_RST#
10/ 25 SIT Add to fix PLT_RST# glitch issue wei Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (SYSTEM PWR MANAGEMENT)
Custom 1.0
5 4 3 2 1
5 4 3 2 1
+CPU_CORE ? +CPU_CORE +CPU_CORE +VCC_GT +VCC_GT

SKL_ULT SKL_ULT ?
UC1L +VCC_GT UC1M
CPU POWER 1 OF 4 VCORE_VCC_SEN VCCGT_VCC_SEN
RC77 1 2 100_0402_1% RC83 1 2 100_0402_1% CPU POWER 2 OF 4
32000mA A30 G32 N70
A34 VCC_A30 VCC_G32 G33 31000mA A48 VCCGT_N70 N71
A39 VCC_A34 VCC_G33 G35 VCORE_VSS_SEN RC82 1 2 100_0402_1% VCCGT_VSS_SEN RC98 1 2 100_0402_1% A53 VCCGT_A48 VCCGT_N71 R63
A44 VCC_A39 VCC_G35 G37 A58 VCCGT_A53 VCCGT_R63 R64
AK33 VCC_A44 VCC_G37 G38 A62 VCCGT_A58 VCCGT_R64 R65
AK35 VCC_AK33 VCC_G38 G40 A66 VCCGT_A62 VCCGT_R65 R66
AK37 VCC_AK35 VCC_G40 G42 AA63 VCCGT_A66 VCCGT_R66 R67
AK38 VCC_AK37 VCC_G42 J30 AA64 VCCGT_AA63 VCCGT_R67 R68
AK40 VCC_AK38 VCC_J30 J33 AA66 VCCGT_AA64 VCCGT_R68 R69
AL33 VCC_AK40 VCC_J33 J37 AA67 VCCGT_AA66 VCCGT_R69 R70
AL37 VCC_AL33 VCC_J37 J40 AA69 VCCGT_AA67 VCCGT_R70 R71
AL40 VCC_AL37 VCC_J40 K33 AA70 VCCGT_AA69 VCCGT_R71 T62
D VCC_AL40 VCC_K33 VCCGT_AA70 VCCGT_T62 D
AM32 K35 SVID +VCCST_CPU AA71 U65
AM33 VCC_AM32 VCC_K35 K37 AC64 VCCGT_AA71 VCCGT_U65 U68
AM35 VCC_AM33 VCC_K37 K38 AC65 VCCGT_AC64 VCCGT_U68 U71
AM37 VCC_AM35 VCC_K38 K40 AC66 VCCGT_AC65 VCCGT_U71 W63
AM38 VCC_AM37 VCC_K40 K42 AC67 VCCGT_AC66 VCCGT_W63 W64
G30 VCC_AM38 VCC_K42 K43 AC68 VCCGT_AC67 VCCGT_W64 W65
VCC_G30 VCC_K43 AC69 VCCGT_AC68 VCCGT_W65 W66
VCORE_VCC_SEN 1 VCCGT_AC69 VCCGT_W66
@ TC90 1 K32 E32 CC42 AC70 W67
RSVD_K32 VCC_SENSE E33 VCORE_VSS_SEN VCORE_VCC_SEN 59 0.1u_0201_10V6K AC71 VCCGT_AC70 VCCGT_W67 W68
VSS_SENSE VCORE_VSS_SEN 59 VCCGT_AC71 VCCGT_W68
1
AK32 J43 W69
56_0402_5%
100_0402_1%
100_0402_1%
@
RSVD_AK32 B63 CPU_SVID_ALERT#_R 2 J45 VCCGT_J43 VCCGT_W69 W70
RC131
RC1544
RC132
AB62 VIDALERT# A63 CPU_SVID_CLK_R J46 VCCGT_J45 VCCGT_W70 W71
P62 VCCOPC_AB62 VIDSCK D64 CPU_SVID_DAT_R J48 VCCGT_J46 VCCGT_W71 Y62
@ TC92 1 +VCCOPC_1.0V V62 VCCOPC_P62 VIDSOUT J50 VCCGT_J48 VCCGT_Y62 +VCC_GT
VCCOPC_V62 VCCGT_J50
2
G20 J52
VCCSTG_G20 +VCCSTG VCCGT_J52
H63 @ J53 AK42
VCC_OPC_1P8_H63 J55 VCCGT_J53 VCCGTX_AK42 AK43
@ TC94 1 +V1.8S_EDRAM G61 J56 VCCGT_J55 VCCGTX_AK43 AK45
VCC_OPC_1P8_G61 1 2 220_0402_1% CPU_SVID_ALERT#_R J58 VCCGT_J56 VCCGTX_AK45 AK46
@ TC95 1 VCCOPC_SENSE AC63
59 VR_SVID_ALRT# RC133
J60 VCCGT_J58 VCCGTX_AK46 AK48 For UMA 2+3e
@ TC97 1 VSSOPC_SENSE AE63 VCCOPC_SENSE K48 VCCGT_J60 VCCGTX_AK48 AK50
VSSOPC_SENSE RC134 1 @ 2 0_0402_5% CPU_SVID_CLK_R K50 VCCGT_K48 VCCGTX_AK50 AK52
AE62 59 VR_SVID_CLK K52 VCCGT_K50 VCCGTX_AK52 AK53
@ TC99 1 +VCCEOPIO AG62 VCCEOPIO_AE62 K53 VCCGT_K52 VCCGTX_AK53 AK55
VCCEOPIO_AG62 RC1545 1 @ 2 0_0402_5% CPU_SVID_DAT_R K55 VCCGT_K53 VCCGTX_AK55 AK56
1 VCCEOPIO_SENSE AL63 59 VR_SVID_DAT K56 VCCGT_K55 VCCGTX_AK56 AK58
@ TC100
1 VSSEOPIO_SENSE AJ62 VCCEOPIO_SENSE K58 VCCGT_K56 VCCGTX_AK58 AK60
@ TC101
VSSEOPIO_SENSE
1, Alert# Route Between CLK and Data VCCGT_K58 VCCGTX_AK60
K60 AK70
L62 VCCGT_K60 VCCGTX_AK70 AL43
For UMA 2+3e SKYLAKE-U_BGA1356 1 OF 20 L63 VCCGT_L62 VCCGTX_AL43 AL46
REV = 1 ? L64 VCCGT_L63 VCCGTX_AL46 AL50
@ L65 VCCGT_L64 VCCGTX_AL50 AL53
L66 VCCGT_L65 VCCGTX_AL53 AL56
L67 VCCGT_L66 VCCGTX_AL56 AL60
L68 VCCGT_L67 VCCGTX_AL60 AM48
+CPU_CORE L69 VCCGT_L68 VCCGTX_AM48 AM50
L70 VCCGT_L69 VCCGTX_AM50 AM52
C +VCC_GT Backside Cap 8x10uF 0402, SIT update VCCGT_L70 VCCGTX_AM52 C
13x10uF 0402, SIT update to 0603 package L71 AM53
M62 VCCGT_L71 VCCGTX_AM53 AM56
N63 VCCGT_M62 VCCGTX_AM56 AM58
N64 VCCGT_N63 VCCGTX_AM58 AU58
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
N66 VCCGT_N64 VCCGTX_AU58 AU63
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCCGT_N66 VCCGTX_AU63
N67 BB57
CC1086
CC1085
CC1080
CC1236
CC1237
CC1093
CC1092
CC1091
CC1089
CC1238
CC1122
CC1123
CC1124
CC1125
CC1126
CC1127
CC1128
CC1129
N69 VCCGT_N67 VCCGTX_BB57 BB66
VCCGT_N69 VCCGTX_BB66
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VCCGT_VCC_SEN J70 AK62 VCCGTX_SENSE 1 TC133 @
59 VCCGT_VCC_SEN VCCGT_VSS_SEN J69 VCCGT_SENSE VCCGTX_SENSE AL61 VSSGTX_SENSE 1 TC134 @
59 VCCGT_VSS_SEN VSSGT_SENSE VSSGTX_SENSE
@ CD@ @ @ @ @ CD@ CD@
REV = 1 ?
@
+CPU_CORE +VCC_GT
15x1uF 0201, SIT update to 0402 package Backside Cap 12x1uF 0201, SIT update
1U_0201_6.3V6-M
1U_0201_6.3V6-M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC1095
CC1096
CC1097
CC1098
CC1099
CC1100
CC1101
CC1102
CC1104
CC1105
CC1108
CC1109
CC1111
CC1114
CC1115
CC1116
CC1118
CC1119
CC1240
CC1241
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@ @
B
Vinafix.com B
A A

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CPU PWR1)
Custom
DG421 1.0

5 4 3 2 1
5 4 3 2 1
+VCCIO
3.1A 2x10uF, 4x1uF
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6-M
1U_0201_6.3V6-M
1U_0201_6.3V6-M
1U_0201_6.3V6-M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1
+VCCIO
CC1152
CC1153
CC1158
CC1159
CC1160
CC1161
CC1218
CC1230
CC1231
CC1232
?
+1.2V UC1N SKL_ULT
CPU POWER 3 OF 4 2 2 2 2 2 2 2 2 2 2
2800mA AU23 AK28 3100mA
AU28 VDDQ_AU23 VCCIO_AK28 AK30
AU35 VDDQ_AU28 VCCIO_AK30 AL30 @ @ @ @ @
AU42 VDDQ_AU35 VCCIO_AL30 AL42
BB23 VDDQ_AU42 VCCIO_AL42 AM28
+1.2V 2A , 3x22uF, 6x10uF, 4x1uF, SIT update VDDQ_BB23 VCCIO_AM28
BB32 AM30 +VCCSA
BB41 VDDQ_BB32 VCCIO_AM30 AM42
BB47 VDDQ_BB41 VCCIO_AM42
D VDDQ_BB47 D
BB51 AK23
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
10U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6-M
1U_0201_6.3V6-M
1U_0201_6.3V6-M
1U_0201_6.3V6-M
5100mA +VCCSA
VDDQ_BB51 VCCSA_AK23 AK25
1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCCSA_AK25 G23 4.5A 10x10uF, 7x1uF, SIT update
CC1256
CC1257
CC1258
CC1168
CC1169
CC1171
CC1222
CC1223
CC1243
CC1244
CC1224
CC1225
CC1226
CC1227
AM40 VCCSA_G23 G25
+VDDQ_CPU_CLK VDDQC VCCSA_G25 G27
2 2 2 2 2 2 2 2 2 2 2 2 2 2 A18 VCCSA_G27 G28
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6-M
1U_0201_6.3V6-M
1U_0201_6.3V6-M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+VCCST_CPU VCCST VCCSA_G28 J22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD@ CD@ @ @ CD@ @ CD@ @ A22 VCCSA_J22 J23
CC1133
CC1134
CC1135
CC1136
CC1137
CC1251
CC1252
CC1253
CC1139
CC1140
CC1142
CC1145
CC1141
CC1143
CC1144
+VCCSTG VCCSTG_A22 VCCSA_J23 J27
CC1132
AL23 VCCSA_J27 K23
+VCCSFR_OC VCCPLL_OC VCCSA_K23 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
K25
K20 VCCSA_K25 K27
130mA K21 VCCPLL_K20 VCCSA_K27 K28
+VCCPLL_CPU VCCPLL_K21 VCCSA_K28 K30 @ @ @ @ CD@ CD@ CD@
VCCSA_K30
AM23 VCCIO_SENSE 1 TC136 @
VCCIO_SENSE AM22 VSSIO_SENSE 1 TC137 @
VSSIO_SENSE
H21 VCCSA_VSS_SEN
VSSSA_SENSE H20 VCCSA_VCC_SEN VCCSA_VSS_SEN 59
VCCSA_SENSE VCCSA_VCC_SEN 59
SKYLAKE-U_BGA13561 OF 20
REV = 1 ?
@
+VCCSTG +VCCST_CPU
+VDDQ_CPU_CLK
120mA
RC1497 1 @ 2 0_0402_5% RC103 1 @ 2 0_0402_5%
1U_0402_6.3V6K
+1.2V +VCCIO
1U_0201_6.3V6-M
10U_0402_6.3V6M
1
RC1604 1 @ 2 0_0402_5%
1U_0402_6.3V6K
CC86
1 1 +VCCST_CPU
+VCCSA
CC1229
CC1228
1
+1.0VALW +VCCST_CPU
CC87
C C
2
2 2 Reserved for VCCST/VCCSTG/VCCPLL
@ power optimized 2
RC1605 1 @ 2 0_0402_5%
VCCSA_VCC_SEN RC101 1 2 100_0402_1%
Reserved for VCCST/VCCSTG/VCCPLL power optimized
+VCCSFR_OC VCCSA_VSS_SEN RC102 1 2 100_0402_1%
+VCCPLL_CPU
RC104 1 @ 2 0_0402_5%
1U_0201_6.3V6-M
1 120mA
RC105 1 @ 2 0_0402_5%
CC85
+VCCST_CPU
0.1u_0201_10V6K
1U_0402_6.3V6K
1 1
2
CC1249
CC84
2 2
+VCCIO
+1.0VALW
22U_0603_6.3V6-M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6-M
Vinafix.com 44 EC_VCCIO_EN
RC128 1 @ 2 0_0402_5% VCCIO_EN
1 1 1 1
CC1250
C1102
CC71
CC72
B B
DC1 1 2 @
11,44 PM_SLP_S3#
1 0.01U_0201_6.3V7-K
RB751V-40_SOD323-2 2 2 2 2
CC77 UC4 @
@ 1 14
2 2 IN1_1 OUT1_2 13
@ IN1_2 OUT1_1
VCCIO_EN 3 12 CC1293 1 2 1000P_0201_50V7-K
EN1 CT1
4 11
+5VALW VBIAS GND
VCCST_EN 5 10 CC1292 1 2 1000P_0201_50V7-K
+1.0VALW EN2 CT2 +VCCST_CPU
6 9
7 IN2_1 OUT2_2 8
10U_0603_6.3V6M
IN2_2 OUT2_1
10U_0603_6.3V6M
VCCST_EN 1
RC142 1 @ 2 0_0402_5% 15
CC80
44 EC_VCCST_EN GPAD
1
G5016KD1U_TDFN14_2X3
CC79
1 0.01U_0201_6.3V7-K
2
CC81 @
2
2
@
Follow DG470 change to Dual Switch 8/ 24 wei
A A

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CPU PWR2)
Custom
DG421 1.0

5 4 3 2 1
5 4 3 2 1
+1.0VALW RC1503 1 @ 2 0_0603_5% +VCCAMPHY
+1.0VALW RC1504 1 @ 2 0_0402_5% +VCCAPLL_1P0 +3VALW_PCH +VCCPGPPG
+VCCHDA
RC1622 1 @ 2 0_0402_5%
D D
+3VALW_PCH RC1586 1 @ 2 0_0402_5%
RC1620 1 @ 2 0_0402_5% VCCMPHYON_1P0_L1

+1.0VALW
1U_0402_6.3V6K
1
CC144
2
+3VALW_PCH
0.696A
+1.0VALW
Near AB19
1U_0402_6.3V6K
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC141
1 1 1 1 1
22mA 2.574A +VCCPGPPG
CC156
CC164
CC172
CC173
CC174
+1.0VALW +1.0VALW ?
1 1
22U_0603_6.3V6-M
1U_0402_6.3V6K
SKL_ULT
2 UC1O
CC158
@ 2 2 2 2 2
CC153
CPU POWER 4 OF 4
@ @ @ @
1U_0402_6.3V6K
+VCCDSW_1P0 2 2 AB19 1
1U_0402_6.3V6K
AB20 VCCPRIM_1P0_AB19 AK15
@ 20mA Near Y15
CC175
1 VCCPRIM_1P0_AB20 VCCPGPPA +3VALW_PCH
P18 AG15 4mA
CC145
1U_0402_6.3V6K
VCCPRIM_1P0_P18 VCCPGPPB Y16
+1.0VALW
1.5A Near AF18 VCCPGPPC
6mA
2
1
AF18 Y15 8mA
CC176
2 AF19 VCCPRIM_CORE_AF18 VCCPGPPD T16 6mA @
VCCPRIM_CORE_AF19 VCCPGPPE +1.8VALW
C V20 AF16 161mA C
47U_0805_4V6-M
1U_0201_6.3V6-M
1U_0402_6.3V6K
VCCPRIM_CORE_V20 VCCPGPPF +1.8VALW 2
1 1 PCH Internal VRM V21 AD15 61mA
1
VCCPRIM_CORE_V21 VCCPGPPG @
CC148
CC147
CC142
+3VALW_PCH
Near N15 AL1 V19
0.1u_0201_10V6K
1U_0402_6.3V6K
DCPDSW_1P0 VCCPRIM_3P3_V19
1 1
2 2 K17 T1 2
CC149
CC143
VCCMPHYON_1P0_L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1 +1.0VALW
88mA L1
+VCCAMPHY VCCMPHYAON_1P0_L1
@ AA1 6mA
22U_0603_6.3V6-M
1U_0402_6.3V6K
N15 VCCATS_1P8 2 2
1 1 VCCMPHYGT_1P0_N15
N16 AK17 1mA
C1096
CC151
N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3

P15 VCCMPHYGT_1P0_N17 AK19 1mA
2 2 VCCMPHYGT_1P0_P15 VCCRTC_AK19 VCCRTC
Near K15 P16 BB14
0.1u_0201_10V6K
1U_0402_6.3V6K
@ VCCMPHYGT_1P0_P16 VCCRTC_BB14
1 1
K15 BB10 VCCRTCEXT
CC146
CC1242
L15 VCCAMPHYPLL_1P0_K15 DCPRTC
VCCAMPHYPLL_1P0_L15 A14 35mA
0.1u_0201_10V6K
VCCCLK1 +1.0VALW 2 2
+VCCAPLL_1P0
22mA V15 1
VCCAPLL_1P0 K19 29mA RC1587 1 @ 2 0_0603_5%
CC55
0.1u_0201_10V6K
1U_0402_6.3V6K
VCCCLK2 +1.0VALW
1 1 AB17
1U_0402_6.3V6K
+1.0VALW VCCPRIM_1P0_AB17
Y18 L21 24mA
C1097
CC154
1 1
22U_0603_6.3V6-M
VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW 2
C1098
CC56
+VCCHDA
0.118A AD17 N20 33mA
0.1u_0201_10V6K
2 2 +3VALW VCCDSW_3P3_AD17 VCCCLK4 +VCCCLK4

1 AD18
AJ17 VCCDSW_3P3_AD18 L19 4mA 2 2
CC165
VCCDSW_3P3_AJ17 VCCCLK5 +VCCCLK5

@
68mA AJ19 A10 10mA
2 VCCHDA VCCCLK6 +1.0VALW
1U_0402_6.3V6K
11mA AJ16 AN11 1
+3VALW_PCH VCCSPI GPP_B0/CORE_VID0 AN13
CC57
0.642A AF20 GPP_B1/CORE_VID1
+1.0VALW VCCSRAM_1P0_AF20
AF21
1U_0402_6.3V6K
T19 VCCSRAM_1P0_AF21 2
1 Near AF20 VCCSRAM_1P0_T19
T20
CC159
VCCSRAM_1P0_T20
Vinafix.com +3VALW_PCH
75mA AJ21
2 VCCPRIM_3P3_AJ21
1U_0402_6.3V6K
CD@ 1 +1.0VALW AK20

VCCPRIM_1P0_AK20
CC171
33mA N18 RC1588 1 @ 2 0_0603_5%

B +1.0VALW VCCAPLLEBB +VCCCLK4 +1.0VALW B
22U_0603_6.3V6-M
2
1
1U_0402_6.3V6K
C1099
1
CD@ REV = 1
CC169
?
@
2
2 @
RC1589 1 @ 2 0_0603_5%
+VCCCLK5 +1.0VALW
Near A18
22U_0603_6.3V6-M
1
C1100
2
@
A A

Vinafix.com
Title
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCH PWR)

Custom
DG421 1.0

5 4 3 2 1
5 4 3 2 1
UC1Q
SKL_ULT ?
SKL_ULT
UC1P ?
D GND 2 OF 3 D
GND 1 OF 3
AT63 BA49
A5 AL65 AT68 VSS_AT63 VSS_BA49 BA53
A67 VSS_A5 VSS_AL65 AL66 AT71 VSS_AT68 VSS_BA53 BA57
A70 VSS_A67 VSS_AL66 AM13 AU10 VSS_AT71 VSS_BA57 BA6
AA2 VSS_A70 VSS_AM13 AM21 AU15 VSS_AU10 VSS_BA6 BA62
AA4 VSS_AA2 VSS_AM21 AM25 AU20 VSS_AU15 VSS_BA62 BA66
AA65 VSS_AA4 VSS_AM25 AM27 AU32 VSS_AU20 VSS_BA66 BA71
AA68 VSS_AA65 VSS_AM27 AM43 AU38 VSS_AU32 VSS_BA71 BB18
AB15 VSS_AA68 VSS_AM43 AM45 AV1 VSS_AU38 VSS_BB18 BB26
AB16 VSS_AB15 VSS_AM45 AM46 AV68 VSS_AV1 VSS_BB26 BB30
VSS_AB21 VSS_AM60 VSS_AV70 VSS_BB38 SKL_ULT ?
AB8 AM61 AV71 BB43 UC1R
AD13 VSS_AB8 VSS_AM61 AM68 AW10 VSS_AV71 VSS_BB43 BB55
AD16 VSS_AD13 VSS_AM68 AM71 AW12 VSS_AW10 VSS_BB55 BB6 GND 3 OF 3
AD19 VSS_AD16 VSS_AM71 AM8 AW14 VSS_AW12 VSS_BB6 BB60 F8 L18
AD20 VSS_AD19 VSS_AM8 AN20 AW16 VSS_AW14 VSS_BB60 BB64 G10 VSS_F8 VSS_L18 L2
AD21 VSS_AD20 VSS_AN20 AN23 AW18 VSS_AW16 VSS_BB64 BB67 G22 VSS_G10 VSS_L2 L20
AD62 VSS_AD21 VSS_AN23 AN28 AW21 VSS_AW18 VSS_BB67 BB70 G43 VSS_G22 VSS_L20 L4
AD8 VSS_AD62 VSS_AN28 AN30 AW23 VSS_AW21 VSS_BB70 C1 G45 VSS_G43 VSS_L4 L8
AE64 VSS_AD8 VSS_AN30 AN32 AW26 VSS_AW23 VSS_C1 C25 G48 VSS_G45 VSS_L8 N10
AE65 VSS_AE64 VSS_AN32 AN33 AW28 VSS_AW26 VSS_C25 C5 G5 VSS_G48 VSS_N10 N13
AE66 VSS_AE65 VSS_AN33 AN35 AW30 VSS_AW28 VSS_C5 D10 G52 VSS_G5 VSS_N13 N19
AE67 VSS_AE66 VSS_AN35 AN37 AW32 VSS_AW30 VSS_D10 D11 G55 VSS_G52 VSS_N19 N21
AF1 VSS_AE69 VSS_AN40 AN42 AW38 VSS_AW36 VSS_D18 D22 G60 VSS_G6 VSS_N65 N68
AF10 VSS_AF1 VSS_AN42 AN58 AW41 VSS_AW38 VSS_D22 D25 G63 VSS_G60 VSS_N68 P17
AF15 VSS_AF10 VSS_AN58 AN63 AW43 VSS_AW41 VSS_D25 D26 G66 VSS_G63 VSS_P17 P19
AF17 VSS_AF15 VSS_AN63 AP10 AW45 VSS_AW43 VSS_D26 D30 H15 VSS_G66 VSS_P19 P20
C AF2 VSS_AF17 VSS_AP10 AP18 AW47 VSS_AW45 VSS_D30 D34 H18 VSS_H15 VSS_P20 P21 C
AF4 VSS_AF2 VSS_AP18 AP20 AW49 VSS_AW47 VSS_D34 D39 H71 VSS_H18 VSS_P21 R13
AF63 VSS_AF4 VSS_AP20 AP23 AW51 VSS_AW49 VSS_D39 D44 J11 VSS_H71 VSS_R13 R6
AG16 VSS_AF63 VSS_AP23 AP28 AW53 VSS_AW51 VSS_D44 D45 J13 VSS_J11 VSS_R6 T15
AG17 VSS_AG16 VSS_AP28 AP32 AW55 VSS_AW53 VSS_D45 D47 J25 VSS_J13 VSS_T15 T17
AG71 VSS_AG21 VSS_AP58 AP63 AW64 VSS_AW62 VSS_D6 D62 J42 VSS_J38 VSS_T4 U10
AH13 VSS_AG71 VSS_AP63 AP68 AW66 VSS_AW64 VSS_D62 D66 J8 VSS_J42 VSS_U10 U63
AH6 VSS_AH13 VSS_AP68 AP70 AW8 VSS_AW66 VSS_D66 D69 K16 VSS_J8 VSS_U63 U64
AH63 VSS_AH6 VSS_AP70 AR11 AY66 VSS_AW8 VSS_D69 E11 K18 VSS_K16 VSS_U64 U66
AH64 VSS_AH63 VSS_AR11 AR15 B10 VSS_AY66 VSS_E11 E15 K22 VSS_K18 VSS_U66 U67
AH67 VSS_AH64 VSS_AR15 AR16 B14 VSS_B10 VSS_E15 E18 K61 VSS_K22 VSS_U67 U69
AJ15 VSS_AH67 VSS_AR16 AR20 B18 VSS_B14 VSS_E18 E21 K63 VSS_K61 VSS_U69 U70
AJ18 VSS_AJ15 VSS_AR20 AR23 B22 VSS_B18 VSS_E21 E46 K64 VSS_K63 VSS_U70 V16
AJ20 VSS_AJ18 VSS_AR23 AR28 B30 VSS_B22 VSS_E46 E50 K65 VSS_K64 VSS_V16 V17
AJ4 VSS_AJ20 VSS_AR28 AR35 B34 VSS_B30 VSS_E50 E53 K66 VSS_K65 VSS_V17 V18
AK11 VSS_AJ4 VSS_AR35 AR42 B39 VSS_B34 VSS_E53 E56 K67 VSS_K66 VSS_V18 W13
AK16 VSS_AK11 VSS_AR42 AR43 B44 VSS_B39 VSS_E56 E6 K68 VSS_K67 VSS_W13 W6
AK18 VSS_AK16 VSS_AR43 AR45 B48 VSS_B44 VSS_E6 E65 K70 VSS_K68 VSS_W6 W9
AK21 VSS_AK18 VSS_AR45 AR46 B53 VSS_B48 VSS_E65 E71 K71 VSS_K70 VSS_W9 Y17
AK22 VSS_AK21 VSS_AR46 AR48 B58 VSS_B53 VSS_E71 F1 L11 VSS_K71 VSS_Y17 Y19
AK27 VSS_AK22 VSS_AR48 AR5 B62 VSS_B58 VSS_F1 F13 L16 VSS_L11 VSS_Y19 Y20
AK63 VSS_AK27 VSS_AR5 AR50 B66 VSS_B62 VSS_F13 F2 L17 VSS_L16 VSS_Y20 Y21
AK68 VSS_AK63 VSS_AR50 AR52 B71 VSS_B66 VSS_F2 F22 VSS_L17 VSS_Y21
AK69 VSS_AK68 VSS_AR52 AR53 BA1 VSS_B71 VSS_F22 F23
AK8
Vinafix.comVSS_AK69 VSS_AR53 AR55 BA10 VSS_BA1 VSS_F23 F27
AL2 VSS_AK8 VSS_AR55 AR58 BA14 VSS_BA10 VSS_F27 F28
AL28 VSS_AL2 VSS_AR58 AR63 BA18 VSS_BA14 VSS_F28 F32 1 OF 20
SKYLAKE-U_BGA1356
AL32 VSS_AL28 VSS_AR63 AR8 BA2 VSS_BA18 VSS_F32 F33 REV = 1
VSS_AL32 VSS_AR8 VSS_BA2 VSS_F33 ?
B AL35 AT2 BA23 F35 @ B
AL38 VSS_AL35 VSS_AT2 AT20 BA28 VSS_BA23 VSS_F35 F37
AL48 VSS_AL45 VSS_AT28 AT35 F68 VSS_BA36 VSS_F4 F40
AL52 VSS_AL48 VSS_AT35 AT4 BA45 VSS_F68 VSS_F40 F42
AL55 VSS_AL52 VSS_AT4 AT42 VSS_BA45 VSS_F42 BA41
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA41
AL64 VSS_AL58 VSS_AT56 AT58
VSS_AL64 VSS_AT58
1 OF 20
SKYLAKE-U_BGA1356
1 OF 20
SKYLAKE-U_BGA1356 REV = 1 ?
REV = 1 ? @
@
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (VSS)

Custom 1.0
5 4 3 2 1
5 4 3 2 1
?
SKL_ULT
UC1S
RESERVED SIGNALS-1
CPU_CFG0 E68 BB68 1 TC173 @ PAD

D PAD @ TC142 1 CPU_CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 1 TC174 @ PAD D
PAD @ TC143 1 CPU_CFG2 D65 CFG[1] RSVD_TP_BB69
PAD @ TC144 1 XDP_CPU_CFG3 D67 CFG[2] AK13 1 TC175 @ PAD
CPU_CFG4 CFG[3] RSVD_TP_AK13
2
E70 AK12 1 TC176 @ PAD

RC1618 PAD @ TC146 1 CPU_CFG5 C68 CFG[4] RSVD_TP_AK12 +VCCST_CPU
1K_0402_5% PAD @ TC147 1 CPU_CFG6 D68 CFG[5] BB2 UC1T SKL_ULT ?
@ PAD @ TC148 1 CPU_CFG7 C67 CFG[6] RSVD_BB2 BA3
CPU_CFG8 CFG[7] RSVD_BA3
2
PAD @ TC153 1 F71 SPARE
CFG[8]
1
RC106 PAD @ TC150 1 CPU_CFG9 G69 +1.8VALW

CPU_CFG10 CFG[9]
1
1K_0402_5% PAD @ TC151 1 F70 AU5 AW69 F6
PAD @ TC152 1 CPU_CFG11 G68 CFG[10] TP5 AT5 AW68 RSVD_AW69 RSVD_F6 E3 RC1619
PAD @ TC157 1 CPU_CFG12 H70 CFG[11] TP6 AU56 RSVD_AW68 RSVD_E3 C11 150_0402_5%
CFG[12] RSVD_AU56 RSVD_C11
1
PAD @ TC154 1 CPU_CFG13 G71 AW48 B11 @

PAD @ TC155 1 CPU_CFG14 H69 CFG[13] D5 Cannonlake@ C7 RSVD_AW48 RSVD_B11 A11
CFG[14] RSVD_D5 RSVD_C7 RSVD_A11
2
PAD @ TC156 1 CPU_CFG15 G70 D4 RC1582 2 1 0_0402_5% RSVD_U12 U12 D12
CFG[15] RSVD_D4 B2 1 TC183 @ PAD RC1583 2 1 0_0402_5% RSVD_U11 U11 RSVD_U12 RSVD_D12 C12
PAD @ TC159 1 CPU_CFG16 E63 RSVD_B2 C2 1 TC185 @ PAD Cannonlake@ H11 RSVD_U11 RSVD_C12 F52 RSVD_F52
PAD @ TC158 1 CPU_CFG17 F63 CFG[16] RSVD_C2 RSVD_H11 RSVD_F52
CFG[17] B3 1 TC184 @ PAD
PAD @ TC161 1 CPU_CFG18 E66 RSVD_B3 A3 1 TC181 @ PAD
CPU_CFG19 CFG[18] RSVD_A3 1 OF 20
PAD @ TC160 1 F66 SKYLAKE-U_BGA1356
CFG[19] AW1 REV = 1 ?
C CFG_RCOMP E60 RSVD_AW1 @ C
CFG_RCOMP E1 1 TC187 @ PAD
PAD @ TC166 1 XDP_ITP_PMODE E8 RSVD_E1 E2
ITP_PMODE RSVD_E2
2
RC162 AY2 BA4

AY1 RSVD_AY2 RSVD_BA4 BB4
49.9_0402_1% RSVD_AY1 RSVD_BB4
PAD @ TC186 1 D1 A4 1 TC182 @ PAD
RSVD_D1 RSVD_A4
1
D3 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45 A69 1 TC188 @ PAD
AL25 RSVD_A69 B69 1 TC193 @ PAD
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 RSVD_AY3 need to check with Intel
PAD @ TC189 1 C71 RSVD_AY3
RSVD_C71
2
PAD @ TC191 1 B70 D71 1 TC190 @ PAD
RSVD_B70 RSVD_D71 C70 1 TC192 @ PAD RC107
F60 RSVD_C70 @
RSVD_F60 0_0402_5%
C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
1
B B
PAD @ TC171 1 BA70 AY4
PAD @ TC172 1 BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2
J71 AY71 VSS_AY71 need to check with Intel
J68 RSVD_J71 VSS_AY71 AR56 1 TC167 @ PAD
RSVD_J68 ZVM#
2
PAD @ TC169 1 F65 AW71 1 TC177 @ PAD
PAD @ TC170 1 G65 VSS_F65 RSVD_TP_AW71 AW70 1 TC178 @ PAD RC108
VSS_G65 RSVD_TP_AW70 @ 0_0402_5%
F61 AP56 1 TC168 @ PAD
E61 RSVD_F61 MSM# C64 PROC_SELECT# 1 2
RSVD_E61 PROC_SELECT# +VCCST_CPU
1
100K_0402_5% Cannonlake@ R22
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
Vinafix.com @
Default
Pin Name Strap Description Configuration Value
A A
CFG[4] Display Port — 1 = eDP Disabled 1
Presence strap — 0 = eDP Enabled
* Security Classification LC Future Center Secret Data Title
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CFG,RESERVED)

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
5 4 3 2 1
5 4 3 2 1
DDRA_DQ[0..63]
DDRA_DQ[0..63] 5
DDRA_DQS#[0..7]
UD1 @ UD2 @
DDRA_DQS#[0..7] 5
DDRA_MA0 DDRA_DQ2 DDRA_MA0 DDRA_DQ18 +1.2V DDRA_DQS[0..7]
P3 G2 P3 G2
DDRA_MA1 A0 DQ0 DDRA_DQ3 DDRA_MA1 A0 DQ0 DDRA_DQ19 DDRA_DQS[0..7] 5
P7 F7 P7 F7
DDRA_MA2 A1 DQ1 DDRA_DQ7 DDRA_MA2 A1 DQ1 DDRA_DQ16 DDRA_MA[0..13]
R3 H3 R3 H3
DDRA_MA3 A2 DQ2 DDRA_DQ1 DDRA_MA3 A2 DQ2 DDRA_DQ21 DDRA_MA[0..13] 5
N7 H7 N7 H7
DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ4 DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ22
DDRA_MA5 A4 DQ4 DDRA_DQ0 DDRA_MA5 A4 DQ4 DDRA_DQ17 1
1
P8 H8 P8 H8 MD@ MD@ +0.6VS
DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ6 DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ23
CD119 RD45
DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ5 DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ20
0.1u_0201_10V6K 1.8K_0402_1%
DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ11 DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ30 2 DDRA_CLK0# 1 MD@ 2
RD49 36_0402_1%
DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ8 DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ28 DDRA_CLK0 1 MD@ 2
RD50 36_0402_1%
DDRA_MA10 A9 DQ9 DDRA_DQ14 DDRA_MA10 A9 DQ9 DDRA_DQ26
2
M3 C3 M3 C3
DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ13 DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ25 DDRA_CS0# 1 MD@ 2
RD51 34.8_0402_1%
DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ15 DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ31 +VREF_CA_MD DDRA_ODT0
RD46 1 2 MD@ RD52 1 MD@ 2 34.8_0402_1%
DDRA_MA13 A12/BC_N DQ12 DDRA_DQ12 DDRA_MA13 A12/BC_N DQ12 DDRA_DQ29 5 DDR_SA_VREFCA
T8 C8 T8 C8 2.7_0402_1%
A13 DQ13 D3 DDRA_DQ10 A13 DQ13 D3 DDRA_DQ27 DDRA_CKE0 1 MD@ 2
1 RD53 34.8_0402_1%
DDRA_MA14_WE# DQ14 DDRA_DQ9 DDRA_MA14_WE# DQ14 DDRA_DQ24
1
D 5 DDRA_MA14_WE# L2 D7 L2 D7 MD@ 1 D
DDRA_MA15_CAS# M8 WE_N/A14 DQ15 DDRA_MA15_CAS# M8 WE_N/A14 DQ15 DDRA_MA0 1 MD@ 2
CD111 RD47 MD@ RD54 34.8_0402_1%
5 DDRA_MA15_CAS# DDRA_MA16_RAS# CAS_N/A15 +1.2V DDRA_MA16_RAS# CAS_N/A15 +1.2V DDRA_MA1
L8 L8 0.022U_0201_6.3V6-K MD@ 1.8K_0402_1% CD112 RD55 1 MD@ 2 34.8_0402_1%
5 DDRA_MA16_RAS# RAS_N/A16 RAS_N/A16 2 DDRA_MA2
D1 D1 0.1u_0201_10V6K RD56 1 MD@ 2 34.8_0402_1%
DDRA_CLK0# K8 VDD1 J1 DDRA_CLK0# K8 VDD1 J1 2 DDRA_MA3 1 MD@ 2
5 DDRA_CLK0# RD57 34.8_0402_1%
DDRA_CLK0 CK_C VDD2 DDRA_CLK0 CK_C VDD2
2
1
5 DDRA_CLK0 K7 L1 K7 L1
CK_T VDD3 R1 CK_T VDD3 R1 DDRA_MA4 1 MD@ 2
RD48 RD58 34.8_0402_1%
DDRA_CKE0 K2 VDD4 B3 DDRA_CKE0 K2 VDD4 B3 DDRA_MA5 1 MD@ 2
5 DDRA_CKE0 24.9_0402_1% MD@ RD59 34.8_0402_1%
CKE VDD5 G7 CKE VDD5 G7 DDRA_MA6 1 MD@ 2
RD60 34.8_0402_1%
DDRA_DQS#0 F3 VDD6 B9 DDRA_DQS#2 F3 VDD6 B9 DDRA_MA7 1 MD@ 2
RD61 34.8_0402_1%
DDRA_DQS0 LDQS_C VDD7 DDRA_DQS2 LDQS_C VDD7
2
G3 J9 G3 J9
DDRA_DQS#1 A7 LDQS_T VDD8 L9 DDRA_DQS#3 A7 LDQS_T VDD8 L9 DDRA_MA8 1 MD@ 2
RD62 34.8_0402_1%
+1.2V DDRA_DQS1 B7 UDQS_C VDD9 T9 +1.2V DDRA_DQS3 B7 UDQS_C VDD9 T9 DDRA_MA9 1 MD@ 2
RD63 34.8_0402_1%
UDQS_T VDD10 UDQS_T VDD10 DDRA_MA10 1 MD@ 2
RD64 34.8_0402_1%
DDRA_DM1 DDRA_DM3 DDRA_MA11
RD65 1 @ 2 0_0402_5% E2 A1 RD66 1 @ 2 0_0402_5% E2 A1 RD67 1 MD@ 2 34.8_0402_1%
RD68 1 @ 2 0_0402_5% DDRA_DM0 E7 NF/UDM_N/UDBI_N VDDQ1 C1 RD69 1 @ 2 0_0402_5% DDRA_DM2 E7 NF/UDM_N/UDBI_N VDDQ1 C1
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 DDRA_MA12 1 MD@ 2
RD70 34.8_0402_1%
DDRA_BS0# N2 VDDQ3 F2 DDRA_BS0# N2 VDDQ3 F2 DDRA_MA13 1 MD@ 2
5 DDRA_BS0# RD71 34.8_0402_1%
DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_MA14_WE# 1 MD@ 2
5 DDRA_BS1# RD72 34.8_0402_1%
BA1 VDDQ5 F8 BA1 VDDQ5 F8 DDRA_MA15_CAS# 1 MD@ 2
RD73 34.8_0402_1%
DDRA_ACT# L3 VDDQ6 J8 DDRA_ACT# L3 VDDQ6 J8
5 DDRA_ACT# DDRA_CS0# ACT_N VDDQ7 DDRA_CS0# ACT_N VDDQ7
L7 A9 L7 A9
5 DDRA_CS0# DDRA_ALERT# CS_N VDDQ8 DDRA_ALERT# CS_N VDDQ8 DDRA_MA16_RAS#
P9 D9 P9 D9 RD74 1 MD@ 2 34.8_0402_1%
5 DDRA_ALERT# ALERT_N VDDQ9 +2.5V_DDR ALERT_N VDDQ9 +2.5V_DDR DDRA_BG0
G9 G9 RD75 1 MD@ 2 34.8_0402_1%
DDRA_BG0 M2 VDDQ10 DDRA_BG0 M2 VDDQ10 DDRA_BS0# 1 MD@ 2
5 DDRA_BG0 RD76 34.8_0402_1%
BG0 B1 BG0 B1 DDRA_BS1# RD77 1 MD@ 2 34.8_0402_1%
DDRA_ODT0 K3 VPP1 R9 DDRA_ODT0 K3 VPP1 R9
5 DDRA_ODT0 ODT VPP2 ODT VPP2 DDRA_ACT#
RD78 1 MD@ 2 34.8_0402_1%
DDRA_PAR T3 M1 +VREF_CA_MD DDRA_PAR T3 M1 +VREF_CA_MD DDRA_PAR 1 MD@ 2
RD79 34.8_0402_1%
5 DDRA_PAR PAR VREFCA PAR VREFCA
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
RD94 1 MD@ 2 10K_0402_5% TEN_UD1 N9 E1 MD@ CD@ RD95 1 MD@ 2 10K_0402_5% TEN_UD2 N9 E1 MD@ MD@
TEN VSS1 TEN VSS1
0.1u_0201_10V6K
0.1u_0201_10V6K
.047U_0201_6.3V6K
.047U_0201_6.3V6K
K1 1 1 K1 1 1
CPU_DRAMRST# P1 VSS2 N1 CPU_DRAMRST# P1 VSS2 N1
MD@ MD@ MD@ MD@
6,18 CPU_DRAMRST# RESET_N VSS3 2 2 RESET_N VSS3 2 2
T1 T1
@ F1 VSS4 B2 @ F1 VSS4 B2
CD121
CD123
CD124
CD125
VSSQ1 VSS5 2 2 VSSQ1 VSS5 2 2
0.1u_0201_10V6K
0.1u_0201_10V6K
1 H1 G8 1 H1 G8
A2 VSSQ2 VSS6 E9 A2 VSSQ2 VSS6 E9 +1.2V
CD114
CD113
CD120
CD122
D2 VSSQ3 VSS7 K9 D2 VSSQ3 VSS7 K9
E3 VSSQ4 VSS8 M9 E3 VSSQ4 VSS8 M9
2 A8 VSSQ5 VSS9 2 A8 VSSQ5 VSS9 DDRA_ALERT# 1 MD@ 2 49.9_0402_1%
RD86
CD47
CD48
D8 VSSQ6 T7 D8 VSSQ6 T7
E8 VSSQ7 NC E8 VSSQ7 NC
C9 VSSQ8 C9 VSSQ8
H9 VSSQ9 H9 VSSQ9
VSSQ10 VSSQ10
C F9 F9 C
ZQ ZQ
1
1
MD@ RD39 MT40A512M16HA083EA_FBGA96 RD40 MT40A512M16HA083EA_FBGA96
240_0402_1% MD@ 240_0402_1%
2
2
+1.2V (1uF_0402_6.3V) *16
Place 4 near each DRAM
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
UD3 @ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
UD4 @ MD@ MD@ MD@ CD@ CD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@
DDRA_MA0 P3 G2 DDRA_DQ43
DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ44 DDRA_MA0 P3 G2 DDRA_DQ59
DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ46 DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ60 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ40 DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ62
CD129
CD126
CD127
CD128
CD130
CD131
CD132
CD133
CD134
CD135
CD136
CD137
CD138
CD139
CD140
CD141
DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ47 DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ56
DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ45 DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ63
CD@ CD@ CD@ CD@
DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ42 DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ61
DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ41 DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ58
DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ34 DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ57
DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ37 DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ54
DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ39 DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ52
DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ32 DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ51
DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ35 DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ49 +1.2V +1.2V
DDRA_MA13 A12/BC_N DQ12 DDRA_DQ33 DDRA_MA12 A11 DQ11 DDRA_DQ50
(1OuF_0603_6.3V) *5
T8 C8 M7 C2 Place around the DRAMs
A13 DQ13 D3 DDRA_DQ38 DDRA_MA13 T8 A12/BC_N DQ12 C8 DDRA_DQ53
DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ36 A13 DQ13 D3 DDRA_DQ55
DDRA_MA15_CAS# M8 WE_N/A14 DQ15 DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ48
DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA15_CAS# M8 WE_N/A14 DQ15
RAS_N/A16 D1 DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V
DDRA_CLK0# K8 VDD1 J1 RAS_N/A16 D1
DDRA_CLK0 CK_C VDD2 DDRA_CLK0# VDD1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
K7 L1 K8 J1 1 1 1 1 1 1 1
CK_T VDD3 R1 DDRA_CLK0 K7 CK_C VDD2 L1
B CD@ CD@ MD@ MD@ CD109 CD110 B
DDRA_CKE0 K2 VDD4 B3 CK_T VDD3 R1 22P_0402_50V8-J 22P_0402_50V8-J
CKE VDD5 G7 DDRA_CKE0 K2 VDD4 B3 RF@ RF@
DDRA_DQS#5 F3 VDD6 B9 CKE VDD5 G7 2 2 2 2 2 2 2
DDRA_DQS5 G3 LDQS_C VDD7 J9 DDRA_DQS#7 F3 VDD6 B9
CD142
CD143
CD144
CD145
CD146
DDRA_DQS#4 A7 LDQS_T VDD8 L9 DDRA_DQS7 G3 LDQS_C VDD7 J9
+1.2V DDRA_DQS4 B7 UDQS_C VDD9 T9 DDRA_DQS#6 A7 LDQS_T VDD8 L9 CD@
UDQS_T VDD10 +1.2V DDRA_DQS6 B7 UDQS_C VDD9 T9
DDRA_DM4 UDQS_T VDD10
RD87 1 @ 2 0_0402_5% E2 A1
DDRA_DM5 NF/UDM_N/UDBI_N VDDQ1 DDRA_DM6
RD88 1 @ 2 0_0402_5% E7 C1 RD89 1 @ 2 0_0402_5% E2 A1
NF/LDM_N/LDBI_N VDDQ2 G1 DDRA_DM7 NF/UDM_N/UDBI_N VDDQ1
RD90 1 @ 2 0_0402_5% E7 C1
DDRA_BS0# N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1
Vinafix.com DDRA_BS1#
DDRA_ACT#
DDRA_CS0#
DDRA_ALERT#
DDRA_BG0
DDRA_ODT0
DDRA_PAR
N8
L3
L7
P9
M2
K3
BA0
BA1
ACT_N
CS_N
ALERT_N
BG0
ODT
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VPP1
VPP2
J2
F8
J8
A9
D9
G9
B1
R9
+VREF_CA_MD
+2.5V_DDR
DDRA_BS0#
DDRA_BS1#
DDRA_ACT#
DDRA_CS0#
DDRA_ALERT#
DDRA_BG0
DDRA_ODT0
N2
N8
L3
L7
P9
M2
K3
BA0
BA1
ACT_N
CS_N
ALERT_N
BG0
ODT
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VPP1
VPP2
F2
J2
F8
J8
A9
D9
G9
B1
R9
+2.5V_DDR
+2.5V_DDR
(1OuF_0603_6.3V) *3
Place around the DRAMs +2.5V_DDR
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
T3 M1 1 1 1 1 1
PAR VREFCA DDRA_PAR +VREF_CA_MD
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 T3 M1 MD@ MD@ CD@ CD157 CD148

2 10K_0402_5% TEN_UD3 PAR VREFCA
1U_0402_6.3V6K
1U_0402_6.3V6K
RD96 1 MD@ N9 E1 CD@ 1 1 22P_0402_50V8-J 22P_0402_50V8-J
TEN VSS1 TEN_UD4
0.1u_0201_10V6K
K1 RD97 1 MD@ 2 10K_0402_5% N9 E1

.047U_0201_6.3V6K
1 1 MD@ RF@ RF@

CPU_DRAMRST# VSS2 TEN VSS1 2 2 2 2 2
0.1u_0201_10V6K
.047U_0201_6.3V6K
P1 N1 MD@ MD@ K1 1 1
RESET_N VSS3 T1 2 2 CPU_DRAMRST# P1 VSS2 N1 MD@ MD@
CD152
CD156
CD147
@ F1 VSS4 B2 RESET_N VSS3 T1 2 2
CD150
CD151
VSSQ1 VSS5 VSS4

0.1u_0201_10V6K
H1 G8 2 2 @ F1 B2
1
CD154
CD155
VSSQ2 VSS6 VSSQ1 VSS5 2 2
0.1u_0201_10V6K
A2 E9 CD@ 1 H1 G8
CD115
CD149
D2 VSSQ3 VSS7 K9 A2 VSSQ2 VSS6 E9 CD@
CD116
CD153
E3 VSSQ4 VSS8 M9 D2 VSSQ3 VSS7 K9
2 A8 VSSQ5 VSS9 E3 VSSQ4 VSS8 M9
CD107
D8 VSSQ6 T7 2 A8 VSSQ5 VSS9

CD108
E8 VSSQ7 NC D8 VSSQ6 T7
C9 VSSQ8 E8 VSSQ7 NC
H9 VSSQ9 C9 VSSQ8 +0.6VS +0.6VS
VSSQ10 VSSQ9
(1uF_0402_6.3V) *8 (1OuF_0603_6.3V) *2
H9 Place 2 near each DRAM Place around the DRAMs
F9 VSSQ10
ZQ F9
ZQ
1
RD43 MT40A512M16HA083EA_FBGA96
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
MD@ 240_0402_1% RD44 MT40A512M16HA083EA_FBGA96 1 1 1 1 1 1 1 1 1 1 1 1
MD@ 240_0402_1% MD@ MD@ CD@ CD@ MD@ MD@ MD@ CD168 CD169
A A
22P_0402_50V8-J 22P_0402_50V8-J
2
RF@ RF@
2
2 2 2 2 2 2 2 2 2 2 2 2
CD158
CD159
CD160
CD161
CD162
CD163
CD164
CD165
CD166
CD167
CD@ CD@ CD@

Issued Date 2015/08/20 Deciphered Date 2016/08/20 DDR4 Memory Down
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.0
Date : Sunday, January 22, 2017 Sheet 17 of 60
5 4 3 2 1
5 4 3 2 1
+1.2V
DDR4 SO-DIMM DDRB_DQ[0..63]

DDRB_DQ[0..63] 6
1
DDRB_DQS#[0..7]
RD91
DDRB_DQS#[0..7] 6
+1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V 240_0402_1%
DDRB_DQS[0..7]
JDDR1A JDDR1B @
DDRB_DQS[0..7] 6
2
1 2 DDRB_MA3 131 132 DDRB_MA2
DDRB_DQ12 VSS_1 VSS_2 DDRB_DQ9 6 DDRB_MA3 DDRB_MA1 A3 A2 DDRB_EVENT# DDRB_MA2 6
3 4 133 134
5 DQ5 DQ4 6 6 DDRB_MA1 135 A1 EVENT_n 136
DDRB_DQ13 7 VSS_3 VSS_4 8 DDRB_DQ8 DDRB_CLK0 137 VDD_9 VDD_10 138 DDRB_CLK1
9 DQ1 DQ0 10 6 DDRB_CLK0 DDRB_CLK0# 139 CK0_t CK1_t 140 DDRB_CLK1# DDRB_CLK1 6
DDRB_DQS#1 11 VSS_5 VSS_6 12 6 DDRB_CLK0# 141 CK0_c CK1_c 142 DDRB_CLK1# 6
DDRB_DQS1 13 DQS0_C DM0_n/DBIO_n/NC 14 DDRB_PAR 143 VDD_11 VDD_12 144 DDRB_MA0
15 DQS0_t VSS_7 16 DDRB_DQ11 6 DDRB_PAR Parity A0 DDRB_MA0 6
DDRB_DQ10 17 VSS_8 DQ6 18
19 DQ7 VSS_9 20 DDRB_DQ15 DDRB_BS1# 145 146 DDRB_MA10
D D
DDRB_DQ14 21 VSS_10 DQ2 22 6 DDRB_BS1# 147 BA1 A10/AP 148 DDRB_MA10 6
23 DQ3 VSS_11 24 DDRB_DQ5 DDRB_CS0# 149 VDD_13 VDD_14 150 DDRB_BS0#
DDRB_DQ0 25 VSS_12 DQ12 26 6 DDRB_CS0# DDRB_MA14_WE# 151 CS0_n BA0 152 DDRB_MA16_RAS# DDRB_BS0# 6
27 DQ13 VSS_13 28 DDRB_DQ4 6 DDRB_MA14_WE# 153 WE_n/A14 RAS_n/A16 154 DDRB_MA16_RAS# 6
DDRB_DQ6 29 VSS_14 DQ8 30 DDRB_ODT0 155 VDD_15 VDD_16 156 DDRB_MA15_CAS#
31 DQ9 VSS_15 32 DDRB_DQS#0 6 DDRB_ODT0 DDRB_CS1# 157 ODT0 CAS_n/A15 158 DDRB_MA13 DDRB_MA15_CAS# 6
VSS_16 DQS1_c DDRB_DQS0 6 DDRB_CS1# CS1_n A13 DDRB_MA13 6
33 34 159 160
35 DM1_n/DBl1_n/NC DQS1_t 36 DDRB_ODT1 161 VDD_17 VDD_18 162
DDRB_DQ7 37 VSS_17 VSS_18 38 DDRB_DQ1 6 DDRB_ODT1 163 ODT1 C0/CS2_n/NC 164 +VREF_CA_DIMM
39 DQ15 DQ14 40 165 VDD_19 VREFCA 166 DDRB_SA2
DDRB_DQ3 41 VSS_19 VSS_20 42 DDRB_DQ2 167 C1/CS3_n/NC SA2 168 @
0.1u_0201_10V6K
2.2U_0402_6.3V6M
43 DQ10 DQ11 44 DDRB_DQ32 169 VSS_53 VSS_54 170 DDRB_DQ36
DDRB_DQ18 VSS_21 VSS_22 DDRB_DQ20 DQ37 DQ36 1 1
45 46 171 172
DDRB_DQ16 49 VSS_23 VSS_24 50 DDRB_DQ21 175 DQ33 DQ32 176
51 DQ17 DQ16 52 DDRB_DQS#4 177 VSS_57 VSS_58 178 2 2
DDRB_DQS#2 53 VSS_25 VSS_26 54 DDRB_DQS4 179 DQS4_c DM4_n/DBl4_n/NC 180
CD1
CD2
DDRB_DQS2 55 DQS2_c DM2_n/DBl2_n/NC 56 181 DQS4_t VSS_59 182 DDRB_DQ34
57 DQS2_t VSS_27 58 DDRB_DQ17 DDRB_DQ39 183 VSS_60 DQ39 184
DDRB_DQ22 59 VSS_28 DQ22 60 185 DQ38 VSS_61 186 DDRB_DQ35
61 DQ23 VSS_29 62 DDRB_DQ19 DDRB_DQ38 187 VSS_62 DQ35 188
DDRB_DQ28 71 VSS_34 DQ24 72 197 DQ40 VSS_67 198 DDRB_DQS#5
73 DQ25 VSS_35 74 DDRB_DQS#3 199 VSS_68 DQS5_c 200 DDRB_DQS5
+1.2V 75 VSS_36 DQS3_c 76 DDRB_DQS3 201 DM5_n/DBl5_n/NC DQS5_t 202
77 DM3_n/DBl3_n/NC DQS3_t 78 DDRB_DQ47 203 VSS_69 VSS_70 204 DDRB_DQ46
DQ26 DQ27 DDRB_DQ53 VSS_73 VSS_74 DDRB_DQ52
1
85 86 211 212
RD92 RD93 87 VSS_41 VSS_42 88 213 DQ52 DQ53 214
240_0402_1% 240_0402_1% 89 CB5/NC CB4/NC 90 DDRB_DQ48 215 VSS_75 VSS_76 216 DDRB_DQ49
91 VSS_43 VSS_44 92 217 DQ49 DQ48 218
93 CB1/NC CB0/NC 94 DDRB_DQS#6 219 VSS_77 VSS_78 220
DDRB_DQS#8 VSS_45 VSS_46 DDRB_DQS6 DQS6_c DM6_n/DBl6_n/NC
2
95 96 221 222
DDRB_DQS8 97 DQS8_c DM8_n/DBI8_n/NC 98 223 DQS6_t VSS_79 224 DDRB_DQ55
99 DQS8_t VSS_47 100 DDRB_DQ54 225 VSS_80 DQ54 226
C 101 VSS_48 CB6/NC 102 227 DQ55 VSS_81 228 DDRB_DQ51 C
103 CB2/NC VSS_49 104 DDRB_DQ50 229 VSS_82 DQ50 230
105 VSS_50 CB7/NC 106 231 DQ51 VSS_83 232 DDRB_DQ56
107 CB3/NC VSS_51 108 CPU_DRAMRST# DDRB_DQ60 233 VSS_84 DQ60 234
DDRB_CKE0 109 VSS_52 RESET_n 110 DDRB_CKE1 CPU_DRAMRST# 6,17 235 DQ61 VSS_85 236 DDRB_DQ61
6 DDRB_CKE0 111 CKE0 CKE1 112 DDRB_CKE1 6 DDRB_DQ57 237 VSS_86 DQ57 238
DDRB_BG1 VDD_1 VDD_2 DDRB_ACT# 1 DQ56 VSS_87 DDRB_DQS#7
113 114 CD3 239 240
6 DDRB_BG1 DDRB_BG0 115 BG1 ACT_n 116 DDRB_ALERT# DDRB_ACT# 6 241 VSS_88 DQS7_c 242 DDRB_DQS7
0.1u_0201_10V6K
6 DDRB_BG0 117 BG0 ALERT_n 118 DDRB_ALERT# 6 243 DM7_n/DBl7_n/NC DQS7_t 244
@
DDRB_MA12 119 VDD_3 VDD_4 120 DDRB_MA11 2 DDRB_DQ59 245 VSS_89 VSS_90 246 DDRB_DQ62
6 DDRB_MA12 DDRB_MA9 121 A12 A11 122 DDRB_MA7 DDRB_MA11 6 247 DQ62 DQ63 248
6 DDRB_MA9 A9 A7 DDRB_MA7 6 DDRB_DQ58 VSS_91 VSS_92 DDRB_DQ63
123 124 249 250
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 251 DQ58 DQ59 252
6 DDRB_MA8 DDRB_MA6 127 A8 A5 128 DDRB_MA4 DDRB_MA5 6 SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
6 DDRB_MA6 129 A6 A4 130 DDRB_MA4 6 1 7,40 2 SMB_CLK_S3 +VDD_SPD 255 SCL SDA 256 DDRB_SA0 SMB_DATA_S3 7,40
+3VS RD1 @
VDD_7 VDD_8 0_0603_5% 257 VDDSPD SA0 258
VPP_1 Vtt DDRB_SA1 +0.6VS
1 1 259 260
VPP_2 SA1
ARGOS_D4AS0-26001-1P60 CD4 CD5 261 262
2.2U_0402_6.3V6M 0.1u_0201_10V6K GND_1 GND_2
ME@ 2 2 ARGOS_D4AS0-26001-1P60
ME@
RD2 1 @ 2 +VPP
+2.5V_DDR
0_0603_5%
+1.2V
1
CD117 Not e:
1
+0.6VS +2.5V_DDR
0.1u_0201_10V6K
2 VREF trace width:20 mils at least Layout Note:
Vinafix.com RD3
1K_0402_1% Spacing:20mils to other signal/ planes Place near DIMM
Place near DIMM scoket
@
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
B 1 1 1 1 1 1 1 1 B
RD4 1 2 +VREF_CA_DIMM CD@
5 DDR_SB_VREFCA
2_0402_5%
1 2 2 2 2 2 2 2 2
CD118
1
1
CD13
CD6
CD7
CD8
CD9
CD10
CD11
CD12
0.022U_0201_6.3V6-K RD5 CD14
2 1K_0402_1% 0.1u_0201_10V6K CD@ CD@
2
1
RD6
24.9_0402_1%
+1.2V
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CD19
CD20
CD21
CD22
CD23
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
CD32
CD33
CD34
CD@ CD@ CD@ CD@
+3VS +3VS +3VS
+1.2V
1
RD7 RD8 RD9

0_0402_5% 0_0402_5% 0_0402_5%
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
@ @ @
RF@
RF@
0.1u_0201_10V6K
0.1u_0201_10V6K
33P_0402_50V8J
33P_0402_50V8J
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
2
1 1 1 1 1 1
DDRB_SA0 DDRB_SA1 DDRB_SA2
A A
2 2 2 2 2 2
CD15
CD16
CD17
CD18
CD36
CD37
1
RD10 RD11 RD12

0_0402_5% 0_0402_5% 0_0402_5%
@ @ @
For EMC
Near JDDRL1
2

Issued Date 2015/08/20 Deciphered Date 2016/08/20 DDR4 SO-DIMM
SPD Address = 2H THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Custom 1.0
5 4 3 2 1
5 4 3 2 1
N16x GPIO
GPIO I/O ACTIVE Function Description Performance Mode P0 TDP and EDP-Continuous current (GDDR5)
GPIO0 OUT - FB Enable for GC6 2.0
FBVDDQ Other
Min FBVDD (GPU+Mem) (1.05V)
GPIO1 OUT N/A GPU Mem Core Clk NVVDD (1.35V) (1.35V) (6) (3.3V)
Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W)
D GPIO2 OUT N/A D
N16S-GMR 16 1.6 849 TBD 19 TBD 2 TBD 4.2 TBD 800 TBD 60 TBD
GPIO3 OUT N/A
N16S-GTR 18 1.7 967 26.5 2 4.2 800 60
GPIO4 OUT N/A
GPIO5 OUT N/A GPU power sequencing---3V3_MAIN_EN
GPIO6 IN - GPU wake signal for GC6 2.0
GPIO7 OUT N/A
GPIO8 I/O - System side PCIe reset Monitor
GPIO9 I/O N/A 2.2K Pull-up
GPIO10 OUT FBVREF_ALTV for GDDR5
GPIO11 OUT - GPU Core VDD PWM control signal N16x Multi-level Straps
GPIO12 IN AC Power Detect Input (10K pull High)
Physical Logical Logical Logical Logical
GPIO13 OUT - Phase Shedding Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO14 IN N/A
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
C C
GPIO15 IN N/A ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
GPIO16 N/A
STRAP1 +3VGS
GPIO17 IN N/A STRAP2 +3VGS
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VGS
GPIO18 IN N/A
STRAP4 +3VGS
GPIO19 IN N/A
GPIO20 N/A
GPIO21 OUT GPU PCIe self-reset control
OVERT OUT Active Low Thermal Catastrophic Over Temperature
N15V-GM Power Sequence

Vinafix.com
B B
+3VG_AON
+VGA_CORE
tNVVDD >0
+1.05VS_VGA
+1.35VGS
tPEX_VDD >0
1. all power rail ramp up time should be larger than 40us~4ms
Other Power rail
+3VG_AON
A A
Tpower-off <10ms

1.all GPU power rails should be turned off within 10ms
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
Issued Date 2015/08/20 Deciphered Date 2016/08/20 VGA Notes List
C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
+3VG_AON
9 PCIE_CRX_GTX_N[0..3]
9 PCIE_CRX_GTX_P[0..3]
2
RV41
9 PCIE_CTX_C_GRX_N[0..3]
10K_0402_5%
@
9 PCIE_CTX_C_GRX_P[0..3]
+3VG_AON
1
1
CV24
2
UV1A 0.1u_0201_10V6K
RV45 @
2
2
Part 1 of 6 10K_0402_5%
G
PCIE_CTX_C_GRX_P0 AG6 C6 FB_GC6_EN @
D PCIE_CTX_C_GRX_N0 PEX_RX0 GPIO0 FB_GC6_EN 24 D
AG7 B2
PCIE_CTX_C_GRX_P1 PEX_RX0_N GPIO1
1
AF7 D6
+3VG_AON +3VG_AON PCIE_CTX_C_GRX_N1 AE7 PEX_RX1 GPIO2 C7 FB_GC6_EN 3 1 FB_GC6_EN_R
PCIE_CTX_C_GRX_P2 PEX_RX1_N GPIO3 FB_GC6_EN_R 8
AE9 F9
D
PCIE_CTX_C_GRX_N2 AF9 PEX_RX2 GPIO4 A3 3VGS_PWR_EN QV6
PCIE_CTX_C_GRX_P3 PEX_RX2_N GPIO5 GPU_EVENT#_R 3VGS_PWR_EN 22,58
2
AG9 A4 2N7002KW_SOT323-3
PCIE_CTX_C_GRX_N3 PEX_RX3 GPIO6
2
AG10 B6 RV47 @
RV3 RV5 AF10 PEX_RX3_N GPIO7 E9 SYS_PEX_RST_MON# 10K_0402_5%
2.2K_0402_5% 2.2K_0402_5% 5
G AE10 NC81 GPIO8 F8 VGA_ALERT# @
@ @ QV1B AE12 NC82 GPIO9 C5 GPIO10_FBVREF_ALTV RV49 2 GC6@ 1 0_0402_5%
NC83 GPIO10 NVVDD_PWM_VID GPIO10_FBVREF_ALTV 25
1
2N7002KDWH_SOT363-6 AF12 E7 RB751V-40_SOD323-2
NC84 GPIO11 VGA_AC_DET_R NVVDD_PWM_VID 58
1
@ AG12 D7 2 1
VGA_SMB_CK2 NC85 GPIO12 PSI_VGA_R VGA_AC_DET 44
4 3 AG13 B4 DV1 OPT@
S
EC_SMB_CK2 7,39,44
GPIO
AF13 NC86 GPIO13 B3
D
AE13 NC87 GPIO14 C3 RV6 1 @ 2 0_0402_5%

NC88 GPIO15 PSI_VGA 58
AE15 D5
RV7 2 @ 1 0_0402_5% AF15 NC1 GPIO16 D4
NC2 GPIO17
2
AG15 C2
G
QV1A AG16 NC3 GPIO18 F7 +3VG_AON +3VG_AON

2N7002KDWH_SOT363-6 AF16 NC4 GPIO19 E6
@ AE16 NC5 GPIO20 C4 GPU_PEX_RST_HOLD#
VGA_SMB_DA2 1 6 AE18 NC6 GPIO21
S
EC_SMB_DA2 7,39,44 NC7
2
AF18 A6 OVERT#
D
NC8 OVERT 1
AG18 AB6 RV13 CV12
AG19 NC9 NC33 10K_0402_5% 0.1u_0201_10V6K
NC10
2
RV9 2 @ 1 0_0402_5% AF19 @ @
G
AE19 NC11 2
PU AT EC SIDE, +3VS AND 4.7K
NC12
1
AE21 AG3
AF21 NC13 NC97 AF4
AG21 NC14 NC98 AF3 GPU_EVENT#_R 3 1 GPU_EVENT#
NC15 NC99 GPU_EVENT# 8
AG22
D
NC16 QV4
2N7002KW_SOT323-3
PCIE_CRX_GTX_P0 OPT@ CV10 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P0 AC9 AE3 @
+3VS PCIE_CRX_GTX_N0 PCIE_CRX_C_GTX_N0 PEX_TX0 NC100
DACs
OPT@ CV13 1 2 0.22U_0201_6.3V6-K AB9 AE4
PCIE_CRX_GTX_P1 OPT@ CV8 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P1 AB10 PEX_TX0_N NC101
RV10 2 @ 1 PCIE_CRX_GTX_N1 OPT@ CV9 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N1 AC10 PEX_TX1 RV15 1 GC6@ 2 0_0402_5%
0_0402_5% PCIE_CRX_GTX_P2 OPT@ CV6 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P2 AD11 PEX_TX1_N
PCI EXPRESS
C C
+3VG_AON PCIE_CRX_GTX_N2 OPT@ CV7 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N2 AC11 PEX_TX2 W5
PCIE_CRX_GTX_P3 OPT@ CV4 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_P3 AC12 PEX_TX2_N NC102 AE2
+3VGARST RV12 1 @ 2 PCIE_CRX_GTX_N3 OPT@ CV5 1 2 0.22U_0201_6.3V6-K PCIE_CRX_C_GTX_N3 AB12 PEX_TX3 NC103 AF2
0_0402_5% AB13 PEX_TX3_N NC104
AC13 NC89
1 NC90 PLT_RST_VGA#
CV11 AD14 RV174 1 2 @
0.1u_0201_10V6K AC14 NC91 56_0402_5%
NC92 1
OPT@ AC15 CV218
2 NC93
5
UV2 AB15 220P_0201_25V7-K

NC94 VGA_CRT_CLK
2
AB16 B7 @
G
VCC
PLT_RST# 1 AC16 NC95 I2CA_SCL A7 VGA_CRT_DATA 2

11,32,37,40,44 PLT_RST# IN1 SYS_PEX_RST_MON# NC96 I2CA_SDA
4 AD17 I2C,if not use, can be soft grounded
2 OUT AC17 NC17 C9 I2CB_SCL
8 PXS_RST# and delete pull up resistor
GND
IN2 AC18 NC18 I2CB_SCL C8 I2CB_SDA OVERT# 3 1

NC19 I2CB_SDA ---colin WRST# 44
AB18
I2C
D
MC74VHC1G08DFT2G_SC70-5 AB19 NC20 A9 I2CC_SCL QV23
NC21 I2CC_SCL I2CC_SDA 1
3
OPT@ AC19 B9 CV221 2N7002KW_SOT323-3

AD20 NC22 I2CC_SDA 0.01U_0201_10V6K @
RV14 2 OPT@ 1 10K_0402_5% AC20 NC23 D9 VGA_SMB_CK2 @
AC21 NC24 I2CS_SCL D8 VGA_SMB_DA2 2
NC25 I2CS_SDA Internal Thermal Sensor
AB21
AD23 NC26
RV16 1 @ 2 0_0402_5% AE23 NC27
AF24 NC28 60mA
AE24 NC29 L6 +PLLVDD
AG24 NC30 CORE_PLLVDD M6 +3VG_AON +3VG_AON
AG25 NC31 SP_PLLVDD
NC32 N6
45mA RV24 1 @ 2 0_0402_5% +SP_PLLVDD
+3VGS +3VG_AON VID_PLLVDD
45mA VGA_CRT_DATA RV17 1 @ 2 2.2K_0402_5% 3VGS_PWR_EN RV18 2 OPT@ 1 10K_0402_5%
CLK_PCIE_GPU AE8
10 CLK_PCIE_GPU CLK_PCIE_GPU# PEX_REFCLK VGA_CRT_CLK
AD8 RV19 1 @ 2 2.2K_0402_5% OVERT# RV20 1 OPT@ 2 10K_0402_5%
10 CLK_PCIE_GPU# CLK_REQ_GPU# PEX_REFCLK_N
2
AC6
RV180 RV37 PEX_CLKREQ_N I2CB_SCL RV22 1 @ 2 2.2K_0402_5% VGA_ALERT# RV23 1 OPT@ 2 10K_0402_5%
2.2K_0402_5% 10K_0402_5% 1 @ 2 RV32 PEX_TSTCLK_OUT AF22
CLK
GC6@ @ 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK C11 XTAL_IN I2CB_SDA RV25 1 @ 2 2.2K_0402_5% VGA_AC_DET_R RV26 1 OPT@ 2 100K_0402_5%
PEX_TSTCLK_N XTAL_IN B10 XTAL_OUT
Differential signal
XTAL_OUT I2CC_SCL PSI_VGA
1
B B
RV28 1 @ 2 2.2K_0402_5% RV29 1 OPT@ 2 10K_0402_5%
DV6 PLT_RST_VGA# AC7 A10 XTALSSIN 1 OPT@ 2 RV34 10K_0402_5%
GPU_PEX_RST_HOLD# 2 RV35 1 OPT@ 2 PEX_TERMP AF25 PEX_RST_N XTAL_SSIN C10 XTALOUT 1 OPT@ 2 RV36 10K_0402_5% I2CC_SDA RV30 1 @ 2 2.2K_0402_5% GPU_PEX_RST_HOLD# RV31 1 OPT@ 2 10K_0402_5%
1 PLT_RST_VGA# 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF
SYS_PEX_RST_MON#
Vinafix.com 3
N15S-GT-S-A2_FCBGA595 XTALOUT RV33 1 @ 2 10K_0402_5%
BAT54AW_SOT323-3 @
GC6@
RV39 1 NGC6@ 2 0_0402_5%
Under GPU(below 150mils)

180ohms (ESR=0.2) Bead
+SP_PLLVDD 1 @ 2 LV1 +1.05VGS
0_0603_5%
1 OPT@ 2
OPT@
OPT@
OPT@
OPT@
0.1u_0201_10V6K
0.1u_0201_10V6K
22U_0603_6.3V6-M
RV38 10M_0402_5%
4.7U_0402_6.3V6M
150mA
1 1 1 1
+3VG_AON YV1
XTAL_IN 1 4 2 2 2 2
CV15
CV16
CV17
CV18
OSC1 GND2
2
RV40 2 3 XTAL_OUT
10K_0402_5% GND1 OSC2
@ 1 1
CV19 27MHZ_10PF_7V27000050 CV20
1
10P_0201_25V8G OPT@ 10P_0201_25V8G

+3VG_AON OPT@ OPT@ Under GPU Near GPU 30ohms (ESR=0.05) Bead
2 2
1
CV23 +PLLVDD 1 @ 2 LV2 +1.05VGS
2
0.1u_0201_10V6K 0_0603_5%
0.1u_0201_10V6K
@ RV44
OPT@
OPT@
22U_0603_6.3V6-M
2
2
10K_0402_5% 1 1
G
@
1
A A
1 3 CLK_REQ_GPU# 2 2
CV21
CV22
10 GPU_CLKREQ#
D
QV5
2
2N7002KW_SOT323-3
@ RV46
10K_0402_5%
@
RV48 1 @ 2
1
0_0402_5%
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_PCIE/ DAC/ GPIO

Custom 1.0
5 4 3 2 1
5 4 3 2 1
D D
UV1C
Part 3 of 6 F11
AC3 NC50 AD10
AC4 NC105 NC51 AD7
Y4 NC106 NC52
Y3 NC107 V5
AA3 NC108 FERMI_RSVD1 V6
AA2 NC109 FERMI_RSVD2 G1
AB1 NC110 NC56 G2
NC111 NC57
NC
AA1 G3
AA4 NC112 NC58 G4
AA5 NC113 NC59 G5
NC114 NC60 G6
NC61 G7
AB5 NC62 V1
AB4 NC115 NC63 V2
AB3 NC116 NC64 W1
AB2 NC117 NC65 W2
AD3 NC118 NC66 W3
AD2 NC119 NC67 W4
AE1 NC120 NC68
AD1 NC121
AD4 NC122
AD5 NC123
NC124 D11 RV50 2 @ 1 10K_0402_5%
BUFRST_N
LVDS/TMDS
T2
T3 NC125 D10
T1 NC126 PGOOD
R1 NC127 E10
R2 NC128 NC71
GENERAL
R3 NC129 F10
N2 NC130 NC72
N3 NC131 +3VG_AON
NC132 D1 STRAP0
STRAP0 D2 STRAP0 29
C STRAP1 C
STRAP1 STRAP1 29
1
V3 E4 STRAP2
V4 NC133 STRAP2 E3 STRAP3 STRAP2 29
RV181
U3 NC134 STRAP3 D3 STRAP3 29
STRAP4 10K_0402_5%
U4 NC135 STRAP4 C1 STRAP4 29
@
T4 NC136 NC73
NC137
2
T5
R4 NC138 F6 MULTI_STRAP_REF0_GND
R5 NC139 MULTI_STRAP_REF0_GND F4
NC140 MULTI_STRAP_REF1_GNDMLS_REF1 F5
MULTI_STRAP_REF2_GND
1
N1 RV51
M1 NC34 40.2K_0402_1%
M2 NC35 F12 OPT@
M3 NC36 THERMDP
NC37
2
K2 E12
K3 NC38 THERMDN
K1 NC39
J1 NC40
NC41
M4 F2 VCCSENSE_VGA
NC42 VDD_SENSE VCCSENSE_VGA 58
M5
L3 NC43
NC44
trace width: 16mils
L4 differential voltage sensing.
K4 NC45
NC46 differential signal routing.
K5
J4 NC47 F1 VSSSENSE_VGA
NC48 GND_SENSE VSSSENSE_VGA 58
J5
Vinafix.com
N4 NC49
N5 NC141 TEST
NC142
P3 AD9 TESTMODE RV52 1 OPT@ 2 10K_0402_5%
P4 NC143 TESTMODE AE5 @ 1
B NC144 JTAG_TCK AE6 1 TV1 B
@
JTAG_TDI AF6 1 TV2
@
J2 JTAG_TDO AD6 1 TV3
@
J3 NC145 JTAG_TMS AG4 TV4
RV53 1 OPT@ 2 10K_0402_5%
NC146 JTAG_TRST_N
H3
H4 NC147
NC148 SERIAL
D12 @ 1
ROM_CS_N B12 ROM_SI TV5
ROM_SI A12 ROM_SO ROM_SI 29
ROM_SO C12 ROM_SCLK ROM_SO 29
ROM_SCLK ROM_SCLK 29
N15S-GT-S-A2_FCBGA595
@
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_LVDS/ HDMI/ THERM

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
PEX_IOVVDD/Q Decouling
Under GPU
MLCC Q'ty
UV1D
2000mA Near GPU +1.05VGS
+1.35VGS Near GPU Under GPU(below 150mils) 3.5A (below 150mils)
B26
Part 4 of 6
AA10
1.0uF 1
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12
10U_0603_6.3V6M
1U_0402_6.3V6K
4.7U_0402_6.3V6M
FBVDDQ_02 PEX_IOVDDQ_2
E23 AA13
4.7uF 1
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
CD@
RF@
22U_0603_6.3V6-M
10U_0603_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
33P_0402_50V8J
E26 FBVDDQ_03 PEX_IOVDDQ_3 AA16
CD@
0.1u_0201_10V6K
0.1u_0201_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
FBVDDQ_04 PEX_IOVDDQ_4 1 1 2 1
1 2 1 1 1 1 1 1 F14 AA18
FBVDDQ_05 PEX_IOVDDQ_5
F21
G13 FBVDDQ_06 PEX_IOVDDQ_6
AA19
AA20
For RF 10uF 1
CV33
CV37
CV39
CV215
G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21 2 2 1 2
2 1 2 2 2 2 2 2 FBVDDQ_08 PEX_IOVDDQ_8
G15 AB22
22uF 1
CV25
CV26
CV27
CV28
CV29
CV30
CV31
CV32
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
D
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24 D
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25

FBVDDQ_12 PEX_IOVDDQ_12 +1.05VGS
G20 AF26 +3VG_AON
22U_0603_6.3V6-M
G21 FBVDDQ_13 PEX_IOVDDQ_13 AF27
FBVDDQ_14 PEX_IOVDDQ_14 Under Near
L22
OPT@
L24 FBVDDQ_19
4.7U_0402_6.3V6M
FBVDDQ_20 1
L26 AA22
OPT@
OPT@
OPT@
0.1u_0201_10V6K
1U_0402_6.3V6K
M21 FBVDDQ_21 PEX_IOVDD_1 AB23
FBVDDQ_22 PEX_IOVDD_2 1 1 1
N21 AC24
CV43
R21 FBVDDQ_23 PEX_IOVDD_3 AD25 2
FBVDDQ_24 PEX_IOVDD_4
POWER
T21 AE26
CV47
CV48
CV49
V21 FBVDDQ_25 PEX_IOVDD_5 AE27 2 2 2
W21 FBVDDQ_26 PEX_IOVDD_6
FBVDDQ_27
H24
H26 FBVDDQ_AON_1
J21 FBVDDQ_AON_2 G10
FBVDDQ_AON_3 3V3_AON_1 +3VG_AON
K21 G12 Near balls
FBVDDQ_AON_4 3V3_AON_2
(Under GPU) Near GPU
V7 G8 +VDD33 RV54 1 @ 2 0_0402_5%
NC149 3V3_MAIN_1 +3VGS
G9
3V3_MAIN_2
OPT@
OPT@
OPT@
OPT@
+1.35VGS
0.1u_0201_10V6K
0.1u_0201_10V6K
4.7U_0402_6.3V6M
1U_0402_6.3V6K
W7 1 1 1 1
AA6 NC150
W6 NC151 D22 RV55 1 OPT@ 2 40.2_0402_1%
Y6 NC152 FB_CAL_VDDQ
NC153 2 2 2 2
CALIBRATION PIN GDDR5
CV50
CV51
CV52
CV53
C24 RV56 1 OPT@ 2 40.2_0402_1%
FB_CAL_GND
M7 B25 RV57 1 OPT@ 2 60.4_0402_1%

FB_CAL_x_PD_VDDQ 40.2Ohm
N7 NC154 FB_CAL_TERM
NC155
T6
P6 NC156 Place near balls FB_CAL_x_PU_GND 40.2Ohm
NC157
C
Under GPU(below 150mils)
FB_CAL_xTERM_GND 60.4Ohm C
T7
NC158 +3VG_AON
R7
0.1u_0201_10V6K
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
U6 NC159
OPT@
OPT@
OPT@
R6 NC160 AA8
NC161 PEX_PLL_HVDD_1 1 1 1
AA9
PEX_PLL_HVDD_2
AB8
CV55
CV56
CV57
PEX_SVDD_3V3 2 2 2
J7
K7 NC76 120mA 120ohm (ESR=0.18) Bead
K6 NC77 AA14 +PEX_PLLVDD @ 2 1 LV3
NC78 PEX_PLLVDD_1 +1.05VGS
H6 AA15 HCB1608KF-121T30_0603
0.1u_0201_10V6K
1U_0402_6.3V6K
4.7U_0402_6.3V6M
J6 NC79 PEX_PLLVDD_2
OPT@
OPT@
OPT@
NC80
1 1 1
RV62 1 @ 2 0_0603_5%
CV58
CV59
CV60
2 2 2
@
Near balls
+3.3VS TO +3VG_AON
+1.35VGS
+3VS +3VG_AON
Vinafix.com +5VALW
LP2301ALT1G_SOT23-3 +5VALW
1
3 1
S
QV11 OPT@ RV67

1
1
470_0603_5%
B B
1
RV63 1 1 1 RV69 @
G
2
47K_0402_5% CV61 CV62 RV64 CV63 47K_0402_5%
2
OPT@ 0.1u_0201_10V6K 0.01U_0201_10V6K 470_0603_5% 10U_0603_6.3V6M @
@ @ @ OPT@
2
2
2 2 2
1
D
2
PXS_PWREN# OPT@ 1 2 RV65 FBVDDQ_PWR_EN# 2 QV15

10K_0402_5% G 2N7002KW_SOT323-3
1 @
1
D CV64 S
3
1
1
2 QV12 0.1u_0201_10V6K D D
8,58 PXS_PWREN G PXS_PWREN# 2 2
2N7002KW_SOT323-3 OPT@ QV13 QV18
2 G 24,57 FBVDDQ_PWR_EN G
OPT@ 2N7002KW_SOT323-3 2N7002KW_SOT323-3
1
S @ @
3
RV66 S S
3
3
100K_0402_5%
OPT@
2
+1.05VGS
+5VALW
+3VGS
+3.3VS TO +3VGS +3VG_AON
1
RV59
1
RV171 1 2 NGC6@ 470_0603_5%
0_0603_5% RV60 @
47K_0402_5%
2
@
LP2301ALT1G_SOT23-3
2
+5VALW
1
QV16 3 1 GC6@ D
S
1.05VGS_EN# 2 QV10
1
G 2N7002KW_SOT323-3
1
RV71 1 1 1 @
G
2
1
47K_0402_5% CV72 CV73 RV72 CV74 D S
3
A GC6@ 0.1u_0201_10V6K 0.01U_0201_10V6K 470_0603_5% 10U_0603_6.3V6M 2 QV9 A
23,55,57,58 EN_VGA G
@ GC6@ @ GC6@ 2N7002KW_SOT323-3
2
2 2 2 @
2
DGPU_PWR_EN# GC6@ 1 2 RV73 S
3
4.7K_0402_5%
1
1
D CV75
1
2 QV19 0.1u_0201_10V6K D
20,58 3VGS_PWR_EN G DGPU_PWR_EN# 2
2N7002KW_SOT323-3 GC6@ QV20
GC6@ 2 G 2N7002KW_SOT323-3
1
S @ Title
3
RV74 S
3
100K_0402_5%
GC6@
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_Power
2
C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
D D
UV1E
UV1F
A2 Part 5 of 6 K11 +VGA_CORE +VGA_CORE
A26 GND_001 GND_057 K13 Part 6 of 6
AB11 GND_002 GND_058 K15
AB14 GND_003 GND_059 K17 K10 V18
AB17 GND_004 GND_060 L10 K12 VDD_001 VDD_041 V16
AB20 GND_005 GND_061 L12 +VGA_CORE K14 VDD_002 VDD_040 V14
AB24 GND_006 GND_062 L14 K16 VDD_003 VDD_039 V12
GND_007 GND_063 Under GPU VDD_004 VDD_038
AC2 L16 K18 V10
AC22 GND_008 GND_064 L18 L11 VDD_005 VDD_037 U17
GND_009 GND_065 VDD_006 VDD_036
POWER
AC26 L2 L13 U15
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
@
CD@
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
GND_012 GND_068 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD_009 VDD_033
AD12 L5 M10 T18
AD13 GND_013 GND_069 M11 M12 VDD_010 VDD_032 T16
AD16 GND_015 GND_071 M15 2 2 2 2 2 2 2 2 2 2 2 2 2 M16 VDD_012 VDD_030 T12
CV76
CV77
CV78
CV79
CV80
CV81
CV82
CV83
CV84
CV85
CV86
CV87
CV88
AD19 GND_017 GND_073 N10 N11 VDD_014 VDD_028 R17
AE11 GND_020 GND_076 N16 N17 VDD_017 VDD_025 R11
AE14 GND_021 GND_077 N18 P10 VDD_018 VDD_024 P18
OPT@
OPT@
OPT@
OPT@
RF@
AE17 GND_022 GND_078 P11 P12 VDD_019 VDD_023 P16
33P_0402_50V8J
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AE20 GND_023 GND_079 P13 VDD_020 VDD_022 P14
GND_024 GND_080 1 1 1 1 1 VDD_021
AF1 P15
AF11 GND_025 GND_081 P17 For RF
GND
AF14 GND_026 GND_082 P2

AF17 GND_027 GND_083 P23 2 2 2 2 2
CV89
CV90
CV91
CV92
CV213
C AF20 GND_028 GND_084 P26 C
AF23 GND_029 GND_085 P5
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16 N15S-GT-S-A2_FCBGA595
B1 GND_034 GND_090 R18
GND_035 GND_091 @
B11 T11
B14 GND_036 GND_092 T13
OPT@
OPT@
OPT@
@
CD@
CD@
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
B17 GND_037 GND_093 T15
GND_038 GND_094 1 1 1 1 1 1 1 1 1 1
B20 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12
B5 GND_041 GND_097 U14 2 2 2 2 2 2 2 2 2 2
CV93
CV94
CV95
CV96
CV97
CV98
CV99
CV100
CV101
CV102
B8 GND_042 GND_098 U16
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
E20 GND_047 GND_103 U5
OPT@
OPT@
CD@
RF@
E22 GND_048 GND_104 V11
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
33P_0402_50V8J
E25 GND_049 GND_105 V13
GND_050 GND_106 1 1 1 1
E5 V15
E8 GND_051 GND_107 V17
GND_052 GND_108 For RF
H2 Y2
H23 GND_053 GND_109 Y23 2 2 2 2
CV103
CV104
CV105
CV214
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112
Vinafix.com AA7
GND_113 AB7
GND_114 Near GPU
B B
@
+VGA_CORE
+5VALW
1
RV173
2
470_0603_5%
RV172 @
47K_0402_5%
2
@
1
D
2 QV22
G 2N7002KW_SOT323-3
1
D @
2 QV21 S
22,55,57,58 EN_VGA
3
G 2N7002KW_SOT323-3
@
S
3
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_+VGA CORE, GND

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
25,26 FBA_D[0..63]
25,26 FBA_CMD[31..0]
25,26 FBA_EDC[7..0]
25,26 FBA_DBI[7..0]
UV1B
D D
Part 2 of 6
FBA_D0 E18 C27 FBA_CMD0
FBA_D1 F18 FBA_D00 FBA_CMD00 C26 FBA_CMD1 +1.35VGS
FBA_D2 E16 FBA_D01 FBA_CMD01 E24 FBA_CMD2
FBA_D3 F17 FBA_D02 FBA_CMD02 F24 FBA_CMD3
FBA_D4 D20 FBA_D03 FBA_CMD03 D27 FBA_CMD4
FBA_D5 D21 FBA_D04 FBA_CMD04 D26 FBA_CMD5
FBA_D6 F20 FBA_D05 FBA_CMD05 F25 FBA_CMD6
FBA_D7 FBA_D06 FBA_CMD06 FBA_CMD7
1
E21 F26
FBA_D8 E15 FBA_D07 FBA_CMD07 F23 FBA_CMD8 RV210 RV209
FBA_D9 D15 FBA_D08 FBA_CMD08 G22 FBA_CMD9 10K_0402_1% 10K_0402_1%
FBA_D10 F15 FBA_D09 FBA_CMD09 G23 FBA_CMD10
FBA_D11 F13 FBA_D10 FBA_CMD10 G24 FBA_CMD11
FBA_D11 FBA_CMD11
2
FBA_D12 C13 F27 FBA_CMD12
FBA_D13 B13 FBA_D12 FBA_CMD12 G25 FBA_CMD13 FBA_CMD14
FBA_D14 E13 FBA_D13 FBA_CMD13 G27 FBA_CMD14
FBA_D15 D13 FBA_D14 FBA_CMD14 G26 FBA_CMD15 FBA_CMD30
FBA_D16 B15 FBA_D15 FBA_CMD15 M24 FBA_CMD16
FBA_D17 C16 FBA_D16 FBA_CMD16 M23 FBA_CMD17
FBA_D18 A13 FBA_D17 FBA_CMD17 K24 FBA_CMD18
FBA_D19 A15 FBA_D18 FBA_CMD18 K23 FBA_CMD19 FBA_CMD13
FBA_D20 B18 FBA_D19 FBA_CMD19 M27 FBA_CMD20
FBA_D21 A18 FBA_D20 FBA_CMD20 M26 FBA_CMD21 FBA_CMD29
FBA_D22 A19 FBA_D21 FBA_CMD21 M25 FBA_CMD22
FBA_D23 C19 FBA_D22 FBA_CMD22 K26 FBA_CMD23
FBA_D24 FBA_D23 FBA_CMD23 FBA_CMD24
1
B24 K22
FBA_D25 C23 FBA_D24 FBA_CMD24 J23 FBA_CMD25 RV212 RV211
FBA_D26 A25 FBA_D25 FBA_CMD25 J25 FBA_CMD26 10K_0402_1% 10K_0402_1%
FBA_D27 A24 FBA_D26 FBA_CMD26 J24 FBA_CMD27
FBA_D28 A21 FBA_D27 FBA_CMD27 K27 FBA_CMD28
FBA_D28 FBA_CMD28
2
FBA_D29 B21 K25 FBA_CMD29
FBA_D30 C20 FBA_D29 FBA_CMD29 J27 FBA_CMD30
FBA_D31 C21 FBA_D30 FBA_CMD30 J26 FBA_CMD31
FBA_D32 R22 FBA_D31 FBA_CMD31 B19 +1.35VGS
C
FBA_D33 R24 FBA_D32 FBA_CMD32 C
FBA_D34 FBA_D33
INTERFACE A
T22 F22 RV121 2 @ 1 60.4_0402_1%
FBA_D35 R23 FBA_D34 FBA_CMD34 J22 RV122 2 @ 1 60.4_0402_1%
FBA_D36 N25 FBA_D35 FBA_CMD35
FBA_D37 N26 FBA_D36 D19 FBA_DBI0
FBA_D37 FBA_DQM0
MEMORY
FBA_D38 N23 D14 FBA_DBI1
FBA_D39 N24 FBA_D38 FBA_DQM1 C17 FBA_DBI2
FBA_D40 V23 FBA_D39 FBA_DQM2 C22 FBA_DBI3
30ohms (ESR=0.01) Bead FBA_D41 FBA_D40 FBA_DQM3 FBA_DBI4
V22 P24
+1.05VGS +FB_PLLAVDD FBA_D42 T23 FBA_D41 FBA_DQM4 W24 FBA_DBI5
FBA_D43 U22 FBA_D42 FBA_DQM5 AA25 FBA_DBI6
FBA_D44 Y24 FBA_D43 FBA_DQM6 U25 FBA_DBI7
LV4 1 2 FBA_D45 AA24 FBA_D44 FBA_DQM7
OPT@ 200mA FBA_D46 Y22 FBA_D45 F19
HCB1608KF-300T60_2P
FBA_D47 AA23 FBA_D46 FBA_DQS_RN0 C14
FBA_D48 AD27 FBA_D47 FBA_DQS_RN1 A16
Place close to BGA FBA_D48 FBA_DQS_RN2
FBA_D49 AB25 A22
FBA_D50 AD26 FBA_D49 FBA_DQS_RN3 P25
FBA_D51 AC25 FBA_D50 FBA_DQS_RN4 W22
FBA_D52 AA27 FBA_D51 FBA_DQS_RN5 AB27
Place close to BGA Place close to ball FBA_D53 AA26 FBA_D52 FBA_DQS_RN6 T27
FBA_D54 W26 FBA_D53 FBA_DQS_RN7
FBA_D55 Y25 FBA_D54 E19 FBA_EDC0
+FB_PLLAVDD FBA_D56 FBA_D55 FBA_DQS_WP0 FBA_EDC1
R26 C15
FBA_D57 T25 FBA_D56 FBA_DQS_WP1 B16 FBA_EDC2
OPT@
OPT@
OPT@
22U_0603_6.3V6-M
1U_0402_6.3V6K
0.1u_0201_10V6K
FBA_D58 N27 FBA_D57 FBA_DQS_WP2 B22 FBA_EDC3

1 1 1 FBA_D59 FBA_D58 FBA_DQS_WP3 FBA_EDC4
R27 R25
FBA_D60 V26 FBA_D59 FBA_DQS_WP4 W23 FBA_EDC5
FBA_D61 V27 FBA_D60 FBA_DQS_WP5 AB26 FBA_EDC6
2 2 2 FBA_D62 W27 FBA_D61 FBA_DQS_WP6 T26 FBA_EDC7
CV111
CV112
CV113
FBA_D63 W25 FBA_D62 FBA_DQS_WP7

FBA_D63 D24 FBA_CLK0
F16 FBA_CLK0 D25 FBA_CLK0# FBA_CLK0 25
B
Vinafix.com +FB_PLLAVDD
FB_GC6_EN
Place close to ball
OPT@
RV119 1
RV120 1
1
@
2 CV115
0.1u_0201_10V6K
2 0_0402_5%
OPT@ 2 10K_0402_5%
H22
FB_CLAMP F3
P22
D23
FB_PLLAVDD_1
FB_PLLAVDD_2
FB_VREF
FB_DLLAVDD
FB_CLAMP
@
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
N22
M22
D18
C18
D17
D16
T24
U24
V24
V25
FBA_CLK1
FBA_CLK1#
FBA_WCLK01
FBA_WCLK01#
FBA_WCLK23
FBA_WCLK23#
FBA_WCLK45
FBA_WCLK45#
FBA_WCLK67
FBA_WCLK67#
FBA_CLK0#
FBA_CLK1
FBA_CLK1#
25
26
26
FBA_WCLK01
FBA_WCLK01#
FBA_WCLK23
FBA_WCLK23#
FBA_WCLK45
FBA_WCLK45#
FBA_WCLK67
FBA_WCLK67#
25
25
25
25
26
26
26
26
B
DV4 GC6@
FB_GC6_EN 1 @ 2 RV123 GC6_EN 2
20 FB_GC6_EN
0_0402_5% 1
3 FBVDDQ_PWR_EN 22,57
1
RV124 1 2 @ BAV70W-7-F_SOT323-3
+3VGS
10K_0402_5% RV125
200K_0402_5%
RV126 1 2 NGC6@ GC6@
8,55,57,58 DGPU_PWROK
0_0402_5%
2
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_MEM Interface

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
Lower 32 bits
24,26 FBA_D[0..63]
24,26 FBA_CMD[31..0]
MF=0 No Mirror MF=1 Mirror
24,26 FBA_EDC[7..0]
24,26 FBA_DBI[7..0]
UV5 UV6
MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

D D
A4 FBA_D0 A4 FBA_D24
FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1 FBA_EDC3 C2 DQ24 DQ0 A2 FBA_D25
C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D26
FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D3 FBA_EDC1 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D27
R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D4 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D28
EDC3 EDC0 DQ28 DQ4 E2 FBA_D5 EDC3 EDC0 DQ28 DQ4 E2 FBA_D29
DQ29 DQ5 F4 FBA_D6 DQ29 DQ5 F4 FBA_D30
FBA_DBI0 D2 DQ30 DQ6 F2 FBA_D7 FBA_DBI3 D2 DQ30 DQ6 F2 FBA_D31
D13 DBI0# DBI3# DQ31 DQ7 A11 D13 DBI0# DBI3# DQ31 DQ7 A11
FBA_CLK0 FBA_DBI2 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_DBI1 P13 DBI1# DBI2# DQ16 DQ8 A13
24 FBA_CLK0 FBA_CLK0# P2 DBI2# DBI1# DQ17 DQ9 B11 P2 DBI2# DBI1# DQ17 DQ9 B11
24 FBA_CLK0# DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
FBA_CLK0 DQ19 DQ11 FBA_CLK0 DQ19 DQ11
1
1
J12 E11 J12 E11

RV194 RV193 FBA_CLK0# J11 CK DQ20 DQ12 E13 FBA_CLK0# J11 CK DQ20 DQ12 E13
40.2_0402_1% 40.2_0402_1% FBA_CMD14 J3 CK# DQ21 DQ13 F11 FBA_CMD14 J3 CK# DQ21 DQ13 F11
CKE# DQ22 DQ14 F13 CKE# DQ22 DQ14 F13
DQ23 DQ15 U11 FBA_D16 DQ23 DQ15 U11 FBA_D8
DQ8 DQ16 DQ8 DQ16
2
2
FBA_CMD2 H11 U13 FBA_D17 FBA_CMD3 H11 U13 FBA_D9

FBA_CMD4 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D18 FBA_CMD1 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D10
1 FBA_CMD3 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D19 FBA_CMD2 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D11
K11 T13 K11 T13
CV228 FBA_CMD1 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D20 FBA_CMD4 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D12
0.01U_0201_10V6K BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA_D21 BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA_D13
2 @ DQ13 DQ21 M11 FBA_D22 DQ13 DQ21 M11 FBA_D14
FBA_CMD6 K4 DQ14 DQ22 M13 FBA_D23 FBA_CMD10 K4 DQ14 DQ22 M13 FBA_D15
FBA_CMD11 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_CMD7 H5 A8/A7 A10/A0 DQ15 DQ23 U4
FBA_CMD7 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_CMD11 K5 A10/A0 A8/A7 DQ1 DQ25 T4
FBA_CMD9 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_CMD9 J5 A11/A6 A9/A1 DQ2 DQ26 T2
A12/RFU/NC DQ3 DQ27 N4 A12/RFU/NC DQ3 DQ27 N4
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
U5 VPP/NC1 DQ5 DQ29 M4 U5 VPP/NC1 DQ5 DQ29 M4
VPP/NC2 DQ6 DQ30 M2 +1.35VGS VPP/NC2 DQ6 DQ30 M2
DQ7 DQ31 DQ7 DQ31
RV182 1 2 1K_0402_1% J1 +1.35VGS RV184 1 2 1K_0402_1% J1 +1.35VGS
RV183 11K_0402_1%
2 FBA_SEN0 J10 MF FBA_SEN0 J10 MF
RV185 1 2 121_0402_1% J13 SEN B1 RV186 1 2 121_0402_1% J13 SEN B1 +1.35VGS
C
ZQ VDDQ1 D1 ZQ VDDQ1 D1 C
VDDQ2 F1 VDDQ2 F1
FBA_CMD8 J4 VDDQ3 M1 FBA_CMD8 J4 VDDQ3 M1 CV626 CV623 CV621 CV622 CV625
FBA_CMD12 G3 ABI# VDDQ4 P1 FBA_CMD15 G3 ABI# VDDQ4 P1
FBA_CMD0 G12 RAS# CAS# VDDQ5 T1 FBA_CMD5 G12 RAS# CAS# VDDQ5 T1
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
FBA_CMD15 L3 CS# WE# VDDQ6 G2 FBA_CMD12 L3 CS# WE# VDDQ6 G2
FBA_CMD5 CAS# RAS# VDDQ7 FBA_CMD0 CAS# RAS# VDDQ7 1 1 1 1 1
L12 L2 L12 L2
WE# CS# VDDQ8 B3 WE# CS# VDDQ8 B3
VDDQ9 D3 VDDQ9 D3
OPT@
OPT@
OPT@
OPT@
OPT@
VDDQ10 F3 VDDQ10 F3 2 2 2 2 2
FBA_WCLK01# D5 VDDQ11 H3 FBA_WCLK23# D5 VDDQ11 H3
24,25 FBA_WCLK01# FBA_WCLK01 D4 WCK01# WCK23# VDDQ12 K3 24,25 FBA_WCLK23# FBA_WCLK23 D4 WCK01# WCK23# VDDQ12 K3
24,25 FBA_WCLK01 WCK01 WCK23 VDDQ13 M3 24,25 FBA_WCLK23 WCK01 WCK23 VDDQ13 M3
FBA_WCLK23# P5 VDDQ14 P3 FBA_WCLK01# P5 VDDQ14 P3 CV614 CV606 CV610 CV608 CV609 CV607
24,25 FBA_WCLK23# FBA_WCLK23 P4 WCK23# WCK01# VDDQ15 T3 24,25 FBA_WCLK01# FBA_WCLK01 P4 WCK23# WCK01# VDDQ15 T3
FBA_VREFC
24,25 FBA_WCLK23 WCK23 WCK01 VDDQ16 E5 24,25 FBA_WCLK01 WCK23 WCK01 VDDQ16 E5
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
+1.35VGS
VDDQ17 N5 VDDQ17 N5
FBA_VREFD_L VDDQ18 FBA_VREFD_L VDDQ18 1 1 1 1 1 1
A10 E10 A10 E10
U10 VREFD1 VDDQ19 N10 U10 VREFD1 VDDQ19 N10
FBA_VREFC0 VREFD2 VDDQ20 FBA_VREFC0 VREFD2 VDDQ20
1
J14 B12 J14 B12
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
820P_0402_25V7
1 VREFC VDDQ21 VREFC VDDQ21 2 2 2 2 2 2

RV192 D12 D12
CV222
820P_0402_25V7
820P_0402_25V7
1 VDDQ22 1 VDDQ22
549_0402_1% F12 F12
CV224
CV226
VDDQ23 H12 VDDQ23 H12
2@ FBA_CMD13 J2 VDDQ24 K12 FBA_CMD13 J2 VDDQ24 K12
RESET# VDDQ25 RESET# VDDQ25
1 2
FBA_VREFC0 2 M12 2 M12 CV631 CV627 CV628 CV630 CV629

VDDQ26 P12 VDDQ26 P12
VDDQ27 T12 VDDQ27 T12
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
RV191
1.33K_0402_1% VDDQ28 G13 VDDQ28 G13
VDDQ29 VDDQ29 1 1 1 1 1
H1 L13 H1 L13
K1 VSS1 VDDQ30 B14 K1 VSS1 VDDQ30 B14
VSS2 VDDQ31 VSS2 VDDQ31
2
B5 D14 B5 D14
OPT@
OPT@
OPT@
OPT@
OPT@
G5 VSS3 VDDQ32 F14 G5 VSS3 VDDQ32 F14 2 2 2 2 2
L5 VSS4 VDDQ33 M14 L5 VSS4 VDDQ33 M14
Vinafix.com FBA_VREFC
T5
B10
D10
G10
L10
VSS5
VSS6
VSS7
VSS8
VSS9
VDDQ34
VDDQ35
VDDQ36
P14
T14
A1
T5
B10
D10
G10
L10
VSS5
VSS6
VSS7
VSS8
VSS9
VDDQ34
VDDQ35
VDDQ36
P14
T14
A1
CV637 CV632 CV636 CV634 CV635 CV633
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
B
P10 VSS10 VSSQ1 C1 P10 VSS10 VSSQ1 C1 B
VSS11 VSSQ2 VSS11 VSSQ2 1 1 1 1 1 1
RV190 2 1 T10 E1 T10 E1
931_0402_1% H14 VSS12 VSSQ3 N1 H14 VSS12 VSSQ3 N1
K14 VSS13 VSSQ4 R1 K14 VSS13 VSSQ4 R1
@
VSS14 VSSQ5 U1 VSS14 VSSQ5 U1 2 2 2 2 2 2
VSSQ6 H2 VSSQ6 H2
VSSQ7 VSSQ7
1
Q34 D +1.35VGS G1 K2 +1.35VGS G1 K2

2 L1 VDD1 VSSQ8 A3 L1 VDD1 VSSQ8 A3
20 GPIO10_FBVREF_ALTV G G4 VDD2 VSSQ9 C3 G4 VDD2 VSSQ9 C3
L4 VDD3 VSSQ10 E3 L4 VDD3 VSSQ10 E3
S 2N7002KW_SOT323-3 C5 VDD4 VSSQ11 N3 C5 VDD4 VSSQ11 N3
VDD5 VSSQ12 VDD5 VSSQ12
3
R5 R3 R5 R3
C10 VDD6 VSSQ13 U3 C10 VDD6 VSSQ13 U3
1
R10 C4 R10 C4
RV208 D11 VDD8 VSSQ15 R4 D11 VDD8 VSSQ15 R4
100K_0402_5% G11 VDD9 VSSQ16 F5 G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5 L11 VDD10 VSSQ17 M5
P11 VDD11 VSSQ18 F10 P11 VDD11 VSSQ18 F10
2
G14 M10 G14 M10

L14 VDD13 VSSQ20 C11 L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 R11 VDD14 VSSQ21 R11
VSSQ22 A12 VSSQ22 A12
VSSQ23 C12 VSSQ23 C12
VSSQ24 E12 VSSQ24 E12
VSSQ25 N12 VSSQ25 N12
VSSQ26 R12 VSSQ26 R12
170-BALL VSSQ27 U12 170-BALL VSSQ27 U12
VSSQ28 H13 VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13 SGRAM GDDR5 VSSQ29 K13
VSSQ35 U14 VSSQ35 U14
VSSQ36 VSSQ36
VRAM@ VRAM@
A A
H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_GDDR5_Rank0_[31:0]

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
upper 32 bits
24,25 FBA_D[0..63]
MF=1 Mirror
24,25 FBA_CMD[31..0]
24,25 FBA_EDC[7..0]
MF=0 No Mirror
24,25 FBA_DBI[7..0]
UV13 UV14
MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

D D
A4 FBA_D56 A4 FBA_D32
FBA_EDC7 C2 DQ24 DQ0 A2 FBA_D57 FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33
C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D58 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D34
FBA_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D59 FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D35
R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D60 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D36
EDC3 EDC0 DQ28 DQ4 E2 FBA_D61 EDC3 EDC0 DQ28 DQ4 E2 FBA_D37
DQ29 DQ5 F4 FBA_D62 DQ29 DQ5 F4 FBA_D38
FBA_DBI7 D2 DQ30 DQ6 F2 FBA_D63 FBA_DBI4 D2 DQ30 DQ6 F2 FBA_D39
D13 DBI0# DBI3# DQ31 DQ7 A11 D13 DBI0# DBI3# DQ31 DQ7 A11
FBA_CLK1 FBA_DBI5 P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_DBI6 P13 DBI1# DBI2# DQ16 DQ8 A13
24 FBA_CLK1 FBA_CLK1# P2 DBI2# DBI1# DQ17 DQ9 B11 P2 DBI2# DBI1# DQ17 DQ9 B11
24 FBA_CLK1# DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13
FBA_CLK1 DQ19 DQ11 FBA_CLK1 DQ19 DQ11
1
1
J12 E11 J12 E11

RV196 RV195 FBA_CLK1# J11 CK DQ20 DQ12 E13 FBA_CLK1# J11 CK DQ20 DQ12 E13
40.2_0402_1% 40.2_0402_1% FBA_CMD30 J3 CK# DQ21 DQ13 F11 FBA_CMD30 J3 CK# DQ21 DQ13 F11
CKE# DQ22 DQ14 F13 CKE# DQ22 DQ14 F13
DQ23 DQ15 U11 FBA_D40 DQ23 DQ15 U11 FBA_D48
DQ8 DQ16 DQ8 DQ16
2
2
FBA_CMD19 H11 U13 FBA_D41 FBA_CMD18 H11 U13 FBA_D49

FBA_CMD17 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D42 FBA_CMD20 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D50
1 FBA_CMD18 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D43 FBA_CMD19 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D51
K11 T13 K11 T13
CV649 FBA_CMD20 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D44 FBA_CMD17 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D52
0.01U_0201_10V6K BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA_D45 BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA_D53
2 @ DQ13 DQ21 M11 FBA_D46 DQ13 DQ21 M11 FBA_D54
FBA_CMD26 K4 DQ14 DQ22 M13 FBA_D47 FBA_CMD22 K4 DQ14 DQ22 M13 FBA_D55
FBA_CMD27 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_CMD23 K5 A10/A0 A8/A7 DQ1 DQ25 T4
FBA_CMD25 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_CMD25 J5 A11/A6 A9/A1 DQ2 DQ26 T2
A12/RFU/NC DQ3 DQ27 N4 A12/RFU/NC DQ3 DQ27 N4
A5 DQ4 DQ28 N2 A5 DQ4 DQ28 N2
U5 VPP/NC1 DQ5 DQ29 M4 U5 VPP/NC1 DQ5 DQ29 M4
+1.35VGS VPP/NC2 DQ6 DQ30 M2 VPP/NC2 DQ6 DQ30 M2
DQ7 DQ31 DQ7 DQ31
RV199 1 2 1K_0402_1% J1 +1.35VGS RV197 1 2 1K_0402_1% J1 +1.35VGS
RV198 11K_0402_1%
2 FBA_SEN1 J10 MF FBA_SEN1 J10 MF
RV200 1 2 121_0402_1% J13 SEN B1 RV201 1 2 121_0402_1% J13 SEN B1 +1.35VGS
C
ZQ VDDQ1 D1 ZQ VDDQ1 D1 C
VDDQ2 F1 VDDQ2 F1
FBA_CMD24 J4 VDDQ3 M1 FBA_CMD24 J4 VDDQ3 M1 CV654 CV650 CV651 CV653 CV652
FBA_CMD31 G3 ABI# VDDQ4 P1 FBA_CMD28 G3 ABI# VDDQ4 P1
FBA_CMD21 G12 RAS# CAS# VDDQ5 T1 FBA_CMD16 G12 RAS# CAS# VDDQ5 T1
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
FBA_CMD28 L3 CS# WE# VDDQ6 G2 FBA_CMD31 L3 CS# WE# VDDQ6 G2
FBA_CMD16 CAS# RAS# VDDQ7 FBA_CMD21 CAS# RAS# VDDQ7 1 1 1 1 1
L12 L2 L12 L2
WE# CS# VDDQ8 B3 WE# CS# VDDQ8 B3
VDDQ9 D3 VDDQ9 D3
OPT@
OPT@
OPT@
OPT@
OPT@
VDDQ10 F3 VDDQ10 F3 2 2 2 2 2
FBA_WCLK67# D5 VDDQ11 H3 FBA_WCLK45# D5 VDDQ11 H3
24 FBA_WCLK67# FBA_WCLK67 D4 WCK01# WCK23# VDDQ12 K3 FBA_WCLK45 D4 WCK01# WCK23# VDDQ12 K3
24 FBA_WCLK67 WCK01 WCK23 VDDQ13 M3 WCK01 WCK23 VDDQ13 M3
FBA_WCLK45# P5 VDDQ14 P3 FBA_WCLK67# P5 VDDQ14 P3 CV660 CV655 CV659 CV657 CV658 CV656
24 FBA_WCLK45# FBA_WCLK45 P4 WCK23# WCK01# VDDQ15 T3 FBA_WCLK67 P4 WCK23# WCK01# VDDQ15 T3
FBA_VREFC
24 FBA_WCLK45 WCK23 WCK01 VDDQ16 E5 WCK23 WCK01 VDDQ16 E5
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
VDDQ17 N5 VDDQ17 N5
FBA_VREFD_H VDDQ18 FBA_VREFD_H VDDQ18 1 1 1 1 1 1
A10 E10 A10 E10
U10 VREFD1 VDDQ19 N10 U10 VREFD1 VDDQ19 N10
FBA_VREFC1 J14 VREFD2 VDDQ20 B12 FBA_VREFC1 J14 VREFD2 VDDQ20 B12
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
820P_0402_25V7
1 VREFC VDDQ21 VREFC VDDQ21 2 2 2 2 2 2

D12 D12
CV661
820P_0402_25V7
820P_0402_25V7
1 VDDQ22 1 VDDQ22
F12 F12
CV662
CV665
VDDQ23 H12 VDDQ23 H12
2@ FBA_CMD29 J2 VDDQ24 K12 FBA_CMD29 J2 VDDQ24 K12
2 RESET# VDDQ25 M12 2 RESET# VDDQ25 M12 CV642 CV638 CV639 CV641 CV640
VDDQ26 P12 VDDQ26 P12
VDDQ27 T12 VDDQ27 T12
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDDQ28 G13 VDDQ28 G13
VDDQ29 VDDQ29 1 1 1 1 1
H1 L13 H1 L13
K1 VSS1 VDDQ30 B14 K1 VSS1 VDDQ30 B14
B5 VSS2 VDDQ31 D14 B5 VSS2 VDDQ31 D14
OPT@
OPT@
OPT@
OPT@
OPT@
G5 VSS3 VDDQ32 F14 G5 VSS3 VDDQ32 F14 2 2 2 2 2
L5 VSS4 VDDQ33 M14 L5 VSS4 VDDQ33 M14
Vinafix.com T5
B10
D10
G10
L10
VSS5
VSS6
VSS7
VSS8
VSS9
VDDQ34
VDDQ35
VDDQ36
P14
T14
A1
T5
B10
D10
G10
L10
VSS5
VSS6
VSS7
VSS8
VSS9
VDDQ34
VDDQ35
VDDQ36
P14
T14
A1
CV647 CV643 CV648 CV646 CV645 CV644
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
B
P10 VSS10 VSSQ1 C1 P10 VSS10 VSSQ1 C1 B
VSS11 VSSQ2 VSS11 VSSQ2 1 1 1 1 1 1
T10 E1 T10 E1
H14 VSS12 VSSQ3 N1 H14 VSS12 VSSQ3 N1
K14 VSS13 VSSQ4 R1 K14 VSS13 VSSQ4 R1
@
VSS14 VSSQ5 U1 VSS14 VSSQ5 U1 2 2 2 2 2 2
VSSQ6 H2 VSSQ6 H2
+1.35VGS G1 VSSQ7 K2 +1.35VGS G1 VSSQ7 K2
L1 VDD1 VSSQ8 A3 L1 VDD1 VSSQ8 A3
G4 VDD2 VSSQ9 C3 G4 VDD2 VSSQ9 C3
L4 VDD3 VSSQ10 E3 L4 VDD3 VSSQ10 E3
C5 VDD4 VSSQ11 N3 C5 VDD4 VSSQ11 N3
R5 VDD5 VSSQ12 R3 R5 VDD5 VSSQ12 R3
C10 VDD6 VSSQ13 U3 C10 VDD6 VSSQ13 U3
R10 VDD7 VSSQ14 C4 R10 VDD7 VSSQ14 C4
D11 VDD8 VSSQ15 R4 D11 VDD8 VSSQ15 R4
G11 VDD9 VSSQ16 F5 G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5 L11 VDD10 VSSQ17 M5
P11 VDD11 VSSQ18 F10 P11 VDD11 VSSQ18 F10
G14 VDD12 VSSQ19 M10 G14 VDD12 VSSQ19 M10
L14 VDD13 VSSQ20 C11 L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 R11 VDD14 VSSQ21 R11
170-BALL VSSQ27 U12 170-BALL VSSQ27 U12
VSSQ28 H13 VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13 SGRAM GDDR5 VSSQ29 K13
VSSQ35 U14 VSSQ35 U14
VSSQ36 VSSQ36
VRAM@ VRAM@
A A
H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_GDDR5_Rank0_[64:32]

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_DDR3_Rank1_[31:0]

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
D D
Vinafix.com
C C
B
Vinafix.com B
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_DDR3_Rank1_[64:32]

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
+3VG_AON
D D
ROM_SCLK +3VGS SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
ROM_SI +3VGS RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VGS DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
2
RV146 RV147 RV148 RV149 RV150 STRAP0 +3VGS Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
49.9K_0402_1% 4.99K_0402_1% 24.9K_0402_1% 4.99K_0402_1% 45.3K_0402_1%
OPT@ @ @ @ @ STRAP1 +3VGS
1
STRAP2 +3VGS
21 STRAP0 STRAP0 Reserved(keep pull-up and pull-down footprint and not stuff by default)
21 STRAP1
STRAP1 STRAP3 +3VGS
21 STRAP2 STRAP2
21 STRAP3
STRAP3 STRAP4 +3VGS
STRAP4
21 STRAP4
DEVID_SEL
2
2
Pull-up to
RV151 RV152 RV153 RV154 RV155 Resistor Values +3VGS Pull-down to Gnd
45.3K_0402_1% 4.99K_0402_1% 15K_0402_1% 4.99K_0402_1% 45.3K_0402_1% 0 (Default)
@ @ @ @ @ 4.99K 1000 0000
1
1
10K 1001 0001 1
15K 1010 0010
20K 1011 0011 PCIE_CFG
24.9K 1100 0100
0 (Default)
30.1K 1101 0101
34.8K 111 0 0110 1
+3VGS 45.3K 1111 0111
C C
SMBUS_ALT_ADDR
X76 0 0x9E (Default)
2
2
RV156 RV157 RV158
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 1 0x9C (Multi-GPU usage)
@ @ @
1
VGA_DEVICE
ROM_SI
21 ROM_SI ROM_SO
21 ROM_SO ROM_SCLK
0 3D Device (Class Code 302h)
21 ROM_SCLK
1 VGA Device (Default)

2
RV159 RV160 RV161

20K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
@ OPT@ OPT@
1
B
Vinafix.com
GPU Configuration
2G VRAM
Samsung
2500MHz
Hynix
2500MHz
FB Memory (DDR3L)
K4G41325FE-HC28
256M x 16
H5GC4H24AJR-T2C
256M x 16
ROM_SI
0x7
PD 45.3K
0x6
PD 34.8K
ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
B
EDW4032BABG-60-F 0x4
Micron
2500MHz 256M x 16 PD 24.9K
N16S-GTR PD 4.99K PD 4.99K PU 49.9K Un-stuff Un-stuff Un-stuff Un-stuff
N16V-GMR1 K4G80325FB-HC03 0x0
Samsung
2500MHz 512M x 16 PD 4.99K
H5GC8H24MJR-T2C 0x5
4G VRAM Hynix
2500MHz 512M x 16 PD 30.1K
MT51J256M32HF-60:A 0x1
Micron
2500MHz 512M x 16 PD 10K
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 N16X_MISC

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
DVDD_IO +1.8VS +1.8V_AUDIO

+3VALW
RA225 1 @ 2 0_0402_5%
RA213 1 @ 2 0_0402_5% Digital power for HDA link
+1.8VALW 8/ 29 Add +1.8VS Circuit for Audio wei
+3VS
2
RA226 1 @ 2 0_0402_5%
CA2
RA216 1 @ 2 0_0402_5% 0.1U_0201_6.3V6-K UA1
Close to1 Pin7 DMIC_DATA DMIC_DATA_R
33 DMIC_DATA RA19 1 @ 2 0_0402_5% 1 30
DMIC_CLK RA18 1 @ 2 0_0402_5% DMIC_CLK_R 2 HD-GPIO0/DMIC-DATA CR-GPIO 31 SD_CD#
33 DMIC_CLK HDA_SDOUT_AUDIO 3 HD-GPIO1/DMIC-CLK CR-SD-CD 32 SD_WP SD_CD# 31
8 HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO 4 HD-SDATA-OUT CR-SD-WP 33 SD_D1_R SD_WP 31
D 8 HDA_BITCLK_AUDIO HD-BCLK CR-SD-DAT[1] SD_D0_R SD_D1_R 31 D
CA1 1 2 2.2U_0402_6.3V6M 5 34
Analog power for mixers, & IO ports Power supply for full-bridge left/ Right channel HDA_SDIN0 RA16 1 2 33_0402_5% SDATA_IN 6 HD-LDO3-CAP CR-SD-DAT[0] 35 SD_CLK_R SD_D0_R 31
+5VS +5VA +5VS +5VD 8 HDA_SDIN0 7 HD-SDATA-IN CR-SD-CLK 36 SD_CLK_R 31
+5VA
DVDD_IO HDA_SYNC_AUDIO HD-DVDD-IO HD-AVDD1 LDO1_CAP
EMC_NS@ 8 37 CA43 1 2 2.2U_0402_6.3V6M CA48 1 2 1U_0402_6.3V6K
8 HDA_SYNC_AUDIO 2 100K_0402_1%PC_BEEP HD-SYNC HD-LDO1-CAP
LA25 1 2 BLM15PD600SN1D_2P
+3VS RA205 1 9 38 CA44 1 2 1U_0402_6.3V6K
RA7 1 @ 2 0_0603_5% PLUG_IN RA204 1 2 200K_0402_1%JSENSE 10 HD-PCBEEP HD-VREF 39 MICBIASB
RA10 1 @ 2 0_0603_5% RING2_CONN 11 HD-JD1(HP/LINE1) HD-MIC2-VREFO 40 LINE1_VREF_L +1.8V_AUDIO
RING3_CONN 12 HD-MIC2-L(RING) HD-LINE1-VREFO-L 41 HPOUT_L
VDD_STB 13 HD-MIC2-R(SLEEVE) HD-HPOUT-L 42 HPOUT_R
0.1U_0201_6.3V6-K
1U_0402_6.3V6K
2 2 HD-3V5V-STB HD-HPOUT-R
1 RA38 2 2.2K_0402_5% CA41 1 2 14 43 CA47 1 2 1U_0402_6.3V6K +1.8V_AUDIO
CA178
10U_0805_10V6K
CA18 0.1U_0201_6.3V6-K
CA19 0.1U_0201_6.3V6-K
1 2 2 2.2U_0402_6.3V6M
CA42 CA20 LINE1_R 15 HD-MIC2-CAP HD-CPVEE 44
MICBIASB 1 RA37 2 2.2K_0402_5% LINE1_L 16 HD-LINE1-R HD-CBN 45 4.7U_0603_6.3V6K 2 1 CA4
1 1 17 HD-LINE1-L HD-CPVDD 46
2 1 1 18 HD-LINE2-R HD-CBP 47 HD_LDO2 CC1671 2 10U_0402_6.3V6M @
SD_CMD_R 19 HD-LINE2-L HD-LDO2-CAP 48
31 SD_CMD_R SD_D3_R 20 CR-SD-CMD HD-AVDD2 49 +5VD
31 SD_D3_R SD_D2_R 21 CR-SD-DAT[3] HD-PVDD1 50 SPK_L+ Analog power for DACs, ADCs
31 SD_D2_R 1 2 22 CR-SD-DAT[2] HD-SPKOUT-LP 51 SPK_L-
CW1 1U_0402_6.3V6K 2
23 CR-SDREG HD-SPKOUT-LN 52 SPK_R- +3VS
CW2 1 2 1U_0402_6.3V6K 24 CR-TEST1 HD-SPKOUT-RN 53 SPK_R+ CC257
RW11 1 2 6.2K_0402_1% RREF 25 CR-V18-CAP HD-SPKOUT-RP 54 +5VD
USB20_N5 USB20_N5_R CR-RREF HD-PVDD2 SPKR_MUTE# 10U_0402_6.3V6M
+3VALW RW12 1 @ 2 0_0402_5% 26 55 1
9 USB20_N5 USB20_P5 RW13 1 @ 2 0_0402_5% USB20_P5_R 27 CR-DM HD-PDB 56 Digital power for digital I/ O circuit
+3VS +3VS_CARD 9 USB20_P5 28 CR-DP HD-DVDD
+3VS_CARD CR-3V3-IN
29
CARD_3V3 CR-SD-3V3 57 2 2
Power for card reader controller 1 1
GNDPAD
RA220 1 2 0_0402_5%
0.1U_0201_6.3V6-K
1U_0402_6.3V6K
@ CW18 CW19 RTS5199-CG_QFN56_7X7 CA180 CA179
4.7U_0402_6.3V6M 0.1u_0201_10V6K
1 1
2 2
RA219 1 @ 2 0_0402_5%
1U_0402_6.3V6K
1
C2062
C 2 C
DA4
EC_MUTE# 1 2 @ SPKR_MUTE#
44 EC_MUTE#
LINE1_L
1
LRB751V-40T1G_SOD323-2 CA45 1 2 1U_0402_6.3V6K
RA35 1 @ 2 0_0402_5% RA43
10K_0402_5% LINE1_VREF_L RA41 1 2 4.7K_0402_5%
Power for combo jack depop circuit at system HPOUT_L RA21 1 2 51_0402_1% A_HP_OUTL_R
2
HPOUT_R A_HP_OUTR_R
+3VL shutdown mode RA20 1 2 51_0402_1%
DA1 LINE1_VREF_L RA42 1 2 4.7K_0402_5%

RA203 1 @ 2 0_0402_5% VDD_STB 2
44 BEEP#
1PC_BEEP1 1 @ 2 CA40 1 2 PC_BEEP LINE1_R CA46 1 2 1U_0402_6.3V6K
8 PCH_BEEP
3 RA211 0_0402_5% 0.1U_0201_6.3V6-K
1
To solve the background noise while combojack connecting to an
active speaker and system entry into S3/ S4/ S5 without analog power. LBAT54CWT1G_SOT323-3 RA14
10K_0402_5% 11/ 8 SIT Vendor suggestion form 47 ohm change to 51om wei
2
RA217 1 @ 2 0_0402_5% @1 TC203
8 HDA_RST_AUDIO#
JSPK1 ME@
RA223 1 CD@ 2 15_0402_5% SPK_R+ RA222 1 @ 2 0_0402_5% SPK_R+_CONN 1
RA224 1 CD@ 2 15_0402_5% SPK_R- RA221 1 @ 2 0_0402_5% SPK_R-_CONN 2 1
RA1 1 2 0_0402_5% RA32 1 CD@ 2 15_0402_5% SPK_L+ RA30 1 @ 2 0_0402_5% SPK_L+_CONN 3 2
Vinafix.com RA4 1
EMC_NS@
2 0_0402_5%
EMC_NS@
RA33 1 CD@ 2 15_0402_5% SPK_L- RA34 1 @ 2 0_0402_5% SPK_L-_CONN 4
5
6
3
4
GND1
470P_0201_50V7-K
470P_0201_50V7-K
470P_0201_50V7-K
470P_0201_50V7-K
LW2
CA183
CA184
CA29
CA30
220P_0201_25V7-K
220P_0201_25V7-K
220P_0201_25V7-K
220P_0201_25V7-K
USB20_N5 1 2 USB20_N5_R GND2
CA31
CA32
CA181
CA182
B 1 2 2 2 2 2 B
RA9 1 @ 2 0_0402_5% 1 1 1 1 ACES_88231-04001
RA12 1 2 0_0402_5% USB20_P5 4 3 USB20_P5_R 11/ 8 SIT Cost down to 0ohm wei
4 3 1 1 1 1
EMC@
EMC@
EMC@
EMC@
EMC_NS@
EXC24CH900U_4P 2 2 2 2
EMC_NS@
FOR EMI CD@ CD@ CD@ CD@
GND GNDA
8/ 16 Update Audio Jack P/ N SP011509163 wei
Audio Jack JHP1 ME@

RING2_CONN 3
R3124 1 @ 2 C232 1 2 A_HP_OUTL_R 1 G/M
0_0402_5% @ 470P_0201_50V7-K L
RING3_CONN PLUG_IN 5
RING2_CONN 5
A_HP_OUTL_R DMIC_CLK HDA_SYNC_AUDIO 6
A_HP_OUTR_R HDA_SDOUT_AUDIO 6
PLUG_IN DMIC_DATA RA27 1 2 27_0402_5%HDA_BITCLK_AUDIO R3123 1 @ 2 C184 1 2 A_HP_OUTR_R 2
EMC@ HDA_SDIN0 0_0402_5% @ 470P_0201_50V7-K R
RING3_CONN 4
CA38
CA39
100P_0201_25V8J
100P_0201_25V8J
M/G
AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
EMC_NS@
CA23
CA24
CA25
CA26
1 1
7
22P_0201_258J
22P_0201_258J
33P_0201_50V8-J
33P_0201_50V8-J
MS
1
EMC_NS@
EMC_NS@
EMC_NS@
47P_0201_25V8-J
1 1 1 1
EMC@
DA5 DA6 DA7 DA8 DA9 SINGA_2SJ3095-140111F
100P_0201_25V8J
100P_0201_25V8J
1
1
C185 2 2
1 1
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
EMC_NS@
2 2 2 2 C182 C183
A 2 EMC@ EMC@ A
2 2
2
For EMI
2
8/ 16 Update Audio Jack P/ N DC021608101 wei
Issued Date 2015/08/20 Deciphered Date 2016/08/20 Codec & CR_RTS5199

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
D D
CARD_3V3
SD / MMC
0.1u_0201_10V6K
4.7U_0402_6.3V6M
1 1
SD_D0_R RW3 1 @ 2 0_0402_5% SD_D0 CW9 CW17
30 SD_D0_R
CW5 1 2 5.6P_0402_50V8-D @
2 2
EMC@
JREAD1 ME@
SD_D1_R RW4 1 @ 2 0_0402_5% SD_D1 SD_D3 1
30 SD_D1_R SD_CMD CD/DAT3
CW6 1 2 5.6P_0402_50V8-D 2
3 CMD
4 VSS1
EMC@
SD_CLK 5 VDD
6 CLK
SD_D2_R RW5 1 2 0_0402_5% SD_D2 SD_D0 7 VSS2
30 SD_D2_R
@ Close to Connector SD_D1 DAT0
CW7 1 2 5.6P_0402_50V8-D 8
C SD_D2 9 DAT1 C
DAT2
EMC@
SD_CD# 10 12
SD_D3_R SD_D3 30 SD_CD# SD_WP CARDDETECT SH1
RW6 1 @ 2 0_0402_5% 11 13
30 SD_D3_R 30 SD_WP WRITEPROTECT SH2
CW8 1 2 5.6P_0402_50V8-D 14
SH3 15
SH4
EMC@
T-SOL_5-251301001000-6_NR
SD_CMD_R SD_CMD Close to Connector
RW7 1 @ 2 0_0402_5%
30 SD_CMD_R
CW11 1 2 5.6P_0402_50V8-D
EMC@ CARD_3V3
8/ 16 Update Conn. P/ N SP07000WG00 wei

SD_CLK_R SD_CLK
1
RW8 1 @ 2 0_0402_5%
30 SD_CLK_R
CW12 1 2 5.6P_0402_50V8-D DW1
EMC_NS@
EMC@
2
2
B B
FOR ESD
Vinafix.com
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cardreader

Custom 1.0
5 4 3 2 1
5 4 3 2 1
+3VS +3VS_TPM
RTPM1 1 TPM@ 2 0_0603_5% 1A

D D
1 1
1 CTPM3
CTPM4 CTPM1 0.1u_0201_10V6K
0.1u_0201_10V6K 10U_0603_6.3V6M TPM@
TPM@ 2 TPM@ 2
2
TPM
+3VS_TPM
UTPM1 TPM@
1 24
2 NC_1 VDD3 10
C 3 NC_2 VDD1 C
NC_3 Reserve for Nationz TPM
RTPM12 1 TPM@ 2 7 28 RTPM2 1 TPM@ 2 4.7K_0402_5%
0_0402_5% PP LPCPD# 27 SERIRQ_TPM RTPM5 1 TPM@ 2 0_0402_5%
6 SERIRQ 26 LPC_AD0_TPM 1 TPM@ 2 0_0402_5% SERIRQ 7,44
RTPM6
NC_4 LAD0 LPC_AD1_TPM LPC_AD0 7,44
Reserve for Nationz TPM 9 23 RTPM7 1 TPM@ 2 0_0402_5%
NC_7 LAD1 LPC_FRAME#_TPM LPC_AD1 7,44
22 RTPM8 1 TPM@ 2 0_0402_5%
LFRAME# LPC_AD2_TPM LPC_FRAME# 7,44
4 20 RTPM9 1 TPM@ 2 0_0402_5%
GND_1 LAD2 LPC_AD3_TPM LPC_AD2 7,44
11 17 RTPM10 1 TPM@ 2 0_0402_5%
+3VALW 18 GND_2 LAD3 LPC_AD3 7,44
GND_3 25 +3VS_TPM
RTPM11 1 TPM@ 2 5 GND_4 21
NC_5 LCLK CLK_PCI_TPM 7
0_0603_5% 8 19
12 NC_6 VDD2 15 TPM_CLKRUN# RTPM13 1 @ 2
13 NC_8 CLK_RUN# PM_CLKRUN# 7
Add for Nuvoton TPM 0_0402_5%
14 NC_9 16
NC_10 LRESET# PLT_RST# 11,20,37,40,44
Reserve for Nuvoton TPM
1
Z32H320TC-LPC-T28-LT1_TSSOP28 RTPM4
0_0402_5%
TPM@
Nationz TPM Nuvoton TPM
2
B B
RTPM2 Stuff NC
RTPM12 Stuff NC
RTPM11 NC Stuff
A
Vinafix.com
5 4
Security Classification
Issued Date 2015/08/20
LC Future Center Secret Data
Deciphered Date 2016/08/20
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
3 2
Title
Custom
Date:
TPM
Size Document Number
Vinafix.com
DG421
Sunday, January 22, 2017
1
Sheet 32 of 60
R ev
1.0
A
5 4 3 2 1
LCD POWER CIRCUIT

+3VS
+LCDVDD +LCDVDD_CON
CMOS Camera +3VS Need short
J1 @
+3VS_CMOS_R
1 2
U5 1 2
5 1 R263 1 @ 2 W=60mils W=40 mils JUMP_43X39
IN OUT
RF_NS@
1 2 0_0805_5% +3VS_CMOS
GND @ LP2301ALT1G_SOT23-3
33P_0402_50V8J
0.1u_0201_10V6K
4.7U_0402_6.3V6M
C1 PCH_ENVDD 4 3
EN OCB 1 1 1 W=40mils
0.1u_0201_10V6K Q7 3 1 @ R3 1 @ 2
D
2 SY6288C20AAC_SOT23-5 0_0603_5%
0.01U_0201_10V6K
@
1 1 1 1
D 2 2 2 C5 C3 C4 D
G
U5 EN PIN VIH MIN 1.5V
2
0.1u_0201_10V6K 0.1u_0201_10V6K 10U_0603_6.3V6M
C121
C122
C123
@ CD@ @
2 2 2 2
C6
CMOS_ON# R5 1 @ 2
100K_0402_5%
For RF 1 1
C9 C10
V20B+ +LEDVDD 0.01U_0201_25V6-K 0.1u_0201_10V6K
2A 80 mil EMC_NS@ @
R17 1 @ 2 0_0805_5% 2 2
2A 80 mil
For EMI
EMC@
Close to R5
CD@
4.7U_0805_25V6-K
0.1U_0201_25V6-K
1 1
2 2
C14
C15
EMI Request
PCH_ENVDD +3VS JEDP1

4 PCH_ENVDD 1
+LEDVDD 1
1
2
R1 3 2
3
2
100K_0402_5% 4
R9 R8 CPU_EDP_TX0+ C19 1 2 0.1u_0201_10V6K EDP_TX0+ 5 4
4 CPU_EDP_TX0+ CPU_EDP_TX0- 1 2 0.1u_0201_10V6K EDP_TX0- 6 5
100K_0402_1% 100K_0402_1% C16
4 CPU_EDP_TX0- 6
2
7
@ @ CPU_EDP_TX1+ C17 1 2 0.1u_0201_10V6K EDP_TX1+ 8 7
4 CPU_EDP_TX1+ 8
1
C CPU_EDP_TX1- C18 1 2 0.1u_0201_10V6K EDP_TX1- 9 C
+3VS 4 CPU_EDP_TX1- 10 9
EDP_AUX CPU_EDP_AUX C20 1 2 0.1u_0201_10V6K EDP_AUX 11 10
EDP_AUX# 4 CPU_EDP_AUX CPU_EDP_AUX# 1 2 0.1u_0201_10V6K EDP_AUX# 12 11
C21
4 CPU_EDP_AUX# 12
2
13
R10 DISPOFF# 14 13
PCH_ENBKL 14
2
R11 1 @ 2 4.7K_0402_5% 15
0_0402_5% @ R15 R13 INVT_PWM 16 15
100K_0402_1% 100K_0402_1% 17 16
17
1
+3VS 18
R12 1 @ 2 0_0402_5% DISPOFF# @ @ 19 18
44 BKOFF# 2 4 CPU_EDP_HPD 19
1
R21 1 @ 20
0_0402_5% 21 20
1 +LCDVDD_CON 21
R14 1 @ 2 0_0402_5% ENBKL W=60mils 22
4 PCH_ENBKL ENBKL 44 23 22
EMC_NS@ C22 +3VS 23
1
680P_0402_50V7K 30 DMIC_DATA
24
R16 2 25 24
30 DMIC_CLK 25
100K_0402_5% 26
27 26
R296 1 @ 2 0_0402_5% CMOS_ON# R182 1 @ 2 0_0402_5% USB20_P8_R 28 27
8 PCH_CMOS_ON# 9 USB20_P8 28
2
R183 1 @ 2 0_0402_5% USB20_N8_R 29

9 USB20_N8 30 29
+3VS_CMOS 30
R297 1 @ 2 0_0402_5% W=40mils 31
44 EC_CMOS_ON# 32 G1
1 G2
+3VS C24
.047U_0201_6.3V6K DRAPH_FC5AF301-3181H
EMC_NS@ ME@
2
2
R18
1K_0402_5%
EMI request
Vinafix.com @
DMIC_CLK DISPOFF# INVT_PWM EMI request
1
R19 1 @ 2 0_0402_5% INVT_PWM

470P_0201_50V7-K
470P_0201_50V7-K
100P_0201_25V8J
4 PCH_EDP_PWM
EMC_NS@
EMC_NS@
B 1 1 1 B
For EMI
EMC@
1
L12 EMC_NS@
R20 USB20_N8 1 2 USB20_N8_R
100K_0402_5% 2 2 2 1 2
C11
C12
C13
USB20_P8 4 3 USB20_P8_R
4 3
2
EXC24CH900U_4P
Touch Screen
Touch Screen
USB20_P6_CONN
+5VS +5VS_TS
L15 USB20_N6_CONN
USB20_P6 1 2 USB20_P6_CONN
1 2
3
+5VS_TS R26 1 @ 2 0_0402_5%

1 JTS1 ME@
USB20_N6 4 3 USB20_N6_CONN C25 1
4 3 1
1
D2 0.1u_0201_10V6K 2 7
EXC24CH900U_4P TS@ R28 1 @ 2 0_0402_5% TS_RS 3 2 GND1
1
2 44 EC_TS_ON 4 3 8
EMC_NS@ USB20_N6_CONN 4 GND2
R23 1 @ 2 0_0402_5% 5
9 USB20_N6 1 2 0_0402_5% USB20_P6_CONN 6 5
D1 R24 @
9 USB20_P6 6
AZC199-02S.R7G_SOT23-3
2
EMC_NS@ CVILU_CI1806M2HR0-NH
A For EMI AZ5725-01F.R7GR_DFN1006P2X2
A
2
EMC_NS@
1
For ESD

Issued Date 2015/08/20 Deciphered Date 2016/08/20 eDP/CMOS/Touch screen
Custom
DG421 1.0

5 4 3 2 1
5 4 3 2 1
L2 EMC@ EMC_NS@
HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2
1 2 C26 3.3P_0402_50V8-C
EMC_NS@ +3VS
HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2
4 3 C27 3.3P_0402_50V8-C
EXC24CH900U_4P
D L3 EMC@ EMC_NS@ D3 D
HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2 HDMI_DET 1 1 HDMI_DET
10 9
1 2
5
C28 3.3P_0402_50V8-C
G
EMC_NS@ Q1B HDMIDAT_R 2 2 9 8 HDMIDAT_R
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2
4 3 C29 3.3P_0402_50V8-C HDMICLK_R 4 4 7 7 HDMICLK_R
EXC24CH900U_4P 4 3 HDMICLK_R
4 DDPB_CLK
S
+5VS_HDMI 5 5 6 +5VS_HDMI
D
6
L4 EMC@ EMC_NS@ 2N7002KDWH_SOT363-6
HDMI_TX1-_C HDMI_TX1-_CON
2
1 2 1 2 3 3
G
1 2 C30 3.3P_0402_50V8-C Q1A
EMC_NS@ 8
4 3 C31 3.3P_0402_50V8-C 1 6 HDMIDAT_R
4 DDPB_DATA
S
EXC24CH900U_4P
D
AZ1045-04F_DFN2510P10E-10-9
2N7002KDWH_SOT363-6 EMC_NS@
L5 EMC@ EMC_NS@
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2
1 2 For EMC
C32 3.3P_0402_50V8-C
EMC_NS@
4 3 C33 3.3P_0402_50V8-C
EXC24CH900U_4P
+5VS
+3VS
For EMC
2
D4
+5VS +5VS_HDMI_F +5VS_HDMI
D5
@ 2 @ F1
2
C 1 1 2 C
HDMI_CLK-_C R29 1 2 470_0402_5% BAT54S-7-F_SOT23-3 3
R35
1
2
Q12 D4 RB491D_SOT23-3 0.5A_6V_1206L050YRHF
G
HDMI_CLK+_C 1M_0402_5%
R30 1 2 470_0402_5%
1
HDMI_TX0-_C R31 1 2 470_0402_5% LP2301ALT1G_SOT23-3
HDMI_DET 1
3 1 C34
HDMI_TX0+_C 4 HDMI_HPD
R32 1 2 470_0402_5% 1 3
D
Q22 0.1u_0201_10V6K
2
1
2N7002KW_SOT323-3
HDMI_TX1-_C 2
2
R33 1 2 470_0402_5% RP1
R41 2.2K_0404_4P2R_5%
G
2
HDMI_TX1+_C R34 1 2 470_0402_5% 20K_0402_5%
46 SUSP
3
4
HDMI_TX2-_C R37 1 2 470_0402_5%
1
HDMI_TX2+_C R38 1 2 470_0402_5%
+5VS_HDMI
JHDMI1 ME@
1
D Q13
2 18 15 HDMICLK_R
+3VS +5V_Power SCL HDMIDAT_R
G 2N7002KW_SOT323-3 16
SDA
S HDMI_TX0+ C38 2 1 0.1u_0201_10V6K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7
4 HDMI_TX0+ TMDS_Data0+
3
HDMI_TX0- C37 2 1 0.1u_0201_10V6K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 13

4 HDMI_TX0- HDMI_TX1+ HDMI_TX1+_C HDMI_TX1+_CON TMDS_Data0- CEC
R42 1 @ 2 4 HDMI_TX1+ C40 2 1 0.1u_0201_10V6K R48 2 @ 1 0_0402_5% 4 17
HDMI_TX1- C39 2 1 0.1u_0201_10V6K HDMI_TX1-_C R47 2 @ 1 0_0402_5% HDMI_TX1-_CON 6 TMDS_Data1+ DDC/CEC_Ground 19 HDMI_DET
4 HDMI_TX1- HDMI_TX2+ HDMI_TX2+_C HDMI_TX2+_CON TMDS_Data1- Hot_Plug_Detect
100K_0402_5% 4 HDMI_TX2+ C42 2 1 0.1u_0201_10V6K R50 2 @ 1 0_0402_5% 1
HDMI_TX2- C41 2 1 0.1u_0201_10V6K HDMI_TX2-_C R49 2 @ 1 0_0402_5% HDMI_TX2-_CON 3 TMDS_Data2+
4 HDMI_TX2- TMDS_Data2-
B
Vinafix.com 4
4
HDMI_CLK+
HDMI_CLK-
HDMI_CLK+
HDMI_CLK-
C36
C35
2
2
1 0.1u_0201_10V6K
1 0.1u_0201_10V6K
HDMI_CLK+_C R44 2
HDMI_CLK-_C R43 2
@
@
1 0_0402_5%
1 0_0402_5%
HDMI_CLK+_CON
HDMI_CLK-_CON
8
5
2
11
10
12
TMDS_Data0_Shield
TMDS_Data1_Shield
TMDS_Data2_Shield
TMDS_Clock_Shield
TMDS_Clock+
TMDS_Clock-
ALLTO_C128S9-K1935-L
8/ 16 Update HDMIConn. P/ N DC021608081 wei

GND1
GND2
GND3
GND4
Utility
14
20
21
22
23
B
Close to JHDMI1
D6 D7
HDMI_CLK+_CON 1 1 HDMI_CLK+_CON HDMI_TX1-_CON HDMI_TX1-_CON
10 9 1 1 10 9
HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON
HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON
HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON
3 3 3 3
8 8
AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9

EMC_NS@ EMC_NS@
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDMI_CONN

Custom 1.0
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
Vinafix.com
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 P35-Blank

Custom 1.0
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank

Custom 1.0
5 4 3 2 1
5 4 3 2 1
+3VALW TO +3VALW_LAN
+3VALW_LAN rising t i me ( 10 %~90 %
):
+3VALW +3VALW_LAN
0.5ms＜spec＜ 10 0m s +3VALW_LAN +LAN_VDDREG
Need short
RL1 @
JL1 1 2 @ width : 40 mils 1 2
1 2
JUMP_43X79 0_0603_5%
D D
1 1
+3VALW LP2301ALT1G_SOT23-3 CL4 CL5 CL1 CL2
0.1u_0201_10V6K
0.1u_0201_10V6K
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1 1 CL6 1 CL7 1 4.7U_0402_6.3V6M 0.1u_0201_10V6K
Q14 3 1 @
0.01U_0201_10V6K
2 2
1
0.1u_0201_10V6K
RL2 1 CL8 CL9 1
100K_0402_5% 2 2 2 2
G
2
@
@ @
2
2 2
RL3 1 @ 2 @ @
44 LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN +3VS
+3VALW_LAN
2
@
2
RL4
G
2
RL5 manual change the Codec PN to RTL8111GUL-CG 10K_0402_5% QL1
10K_0402_5% UL1
1
@ LAN_CLKREQ#_R 1 3 @
LAN_CLKREQ# 10
S
1
2N7002KW_SOT323-3
RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R
11,40,44 PCIE_WAKE#
40,44 LAN_WAKE# RL6 1 @ 2 0_0402_5%
33 RL18 1 @ 2 0_0402_5%
C +3VALW_LAN 32 GND 16 CLK_PCIE_LAN# C
AVDD33_2 REFCLK_N CLK_PCIE_LAN CLK_PCIE_LAN# 10
RL8 1 2 RSET 31 15
+LAN_VDD10 30 RSET REFCLK_P 14 PCIE_PTX_C_DRX_N5 CLK_PCIE_LAN 10
2.49K_0402_1%
LAN_XTALO AVDD10 HSIN PCIE_PTX_C_DRX_P5 PCIE_PTX_C_DRX_N5 9
29 13
LAN_XTALI CKXTAL2 HSIP LAN_CLKREQ#_R PCIE_PTX_C_DRX_P5 9
28 12
+3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# @ LAN_DISABLE# LED0 AVDD33_1 LAN_MDI3-
RL121 2 26 10
LED1/GPIO MDIN3 LAN_MDI3+ LAN_MDI3- 38
0_0402_5% TL4 @ 1 25 9
+LAN_REGOUT LED2 MDIP3 +LAN_VDD10 LAN_MDI3+ 38
1
24 8
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
+LAN_VDD10 VDDREG MDIN2 LAN_MDI2+ LAN_MDI2- 38
1K_0402_1% 22 6
PCIE_WAKE#_R DVDD10 MDIP2 LAN_MDI1- LAN_MDI2+ 38
21 5
20 LANWAKEB MDIN1 4 LAN_MDI1+ LAN_MDI1- 38
ISOLATE#
ISOLATEB MDIP1 LAN_MDI1+ 38
2
PLT_RST# 19 3 +LAN_VDD10
11,20,32,40,44 PLT_RST# PCIE_PRX_C_DTX_N5 PERSTB AVDD10_1 LAN_MDI0-
9 PCIE_PRX_DTX_N5 CL10 1 2 0.1u_0201_10V6K 18 2
LAN_PWR_ON# PCIE_PRX_C_DTX_P5 HSON MDIN0 LAN_MDI0+ LAN_MDI0- 38
ISOLATE# RL10 1 @ 2
9 PCIE_PRX_DTX_P5 CL11 1 2 0.1u_0201_10V6K 17 1
HSOP MDIP0 LAN_MDI0+ 38
0_0402_5% CL10 close to Pin18
1
RL11 CL11 close to Pin17

15K_0402_5%
@
2
RTL8111GUL-CG QFN 32P

8111GUL@
B
Vinafix.com
CL12
1
1
2
YL1
OSC1
GND1
GND2
OSC2
25MHZ_10PF_7V25000014
4
1
LAN_XTALO_R
CL13
1 2
RL21 1K_0402_5%
LAN_XTALI
LAN_XTALO
+LAN_REGOUT
For RTL8111GUL(SWR mode, reserved)
For RTL8111H (LDO mode)
LL1
RL20
1 2 8111GUL@
2.2UH_NLC252018T-2R2J-N_5%
1 2
0_0805_5%
CL15
8111H@
1 1
CL16
+LAN_VDD10
1
CL17
1
CL18
1
CL19
1
CL20
1
CL21
1
CL22
B
12P_0402_50V8-J 15P_0402_50V8J 4.7U_0402_6.3V6M 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 1U_0402_6.3V6K 0.1u_0201_10V6K
2 2 2 2 2 2 2 2
2 2
Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)

Layout Note: LL1 must be
within 200mil to Pin24,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 LAN_RTL8111H_CG

Custom 1.0
5 4 3 2 1
5 4 3 2 1
DL1/DL2
1'S PN:SC300003M00
TL1
24 1 MCT
D MCT1 TCT1 D
LAN_MDI0+ 23 2 LAN_MDO0+
37 LAN_MDI0+ MX1+ TD1+
DL1
LAN_MDI2+ 1 10 LAN_MDI2+ LAN_MDI0- 22 3 LAN_MDO0-
LINE1IN LINE1OUT 37 LAN_MDI0- MX1- TD1-
1
EMC@
LAN_MDI2- 2 9 LAN_MDI2- 21 4 MCT RL17
LINE2IN LINE2OUT MCT2 TCT2 20_0603_5%
LAN_MDI1+ LAN_MDO1+
1
3 8 20 5
GND1 GND2 37 LAN_MDI1+ MX2+ TD2+ DL3
1
2
LAN_MDI3+ 4 7 LAN_MDI3+ LAN_MDI1- 19 6 LAN_MDO1- PDT5061_DO-214AA
LINE3IN LINE3OUT 37 LAN_MDI1- MX2- TD2- EMC@
LAN_MDI3- 5 6 LAN_MDI3- 18 7
2
MCT EMC
LINE4IN LINE4OUT MCT3 TCT3
2
11 13 LAN_MDI2+ 17 8 LAN_MDO2+
GND3 GND5 37 LAN_MDI2+ MX3+ TD3+
12 LAN_MDI2- 16 9 LAN_MDO2-
GND4 37 LAN_MDI2- MX3- TD3-
AZ3133-08F.R7G_DFN3020P10E10 15 10 MCT
EMC_NS@ MCT4 TCT4
1 1
LAN_MDI3+ 14 11 LAN_MDO3+ CL32 CL25
37 LAN_MDI3+ MX4+ TD4+ 0.022U_0603_50V7K 1000P_1206_2KV7-K
LAN_MDI3- 13 12 LAN_MDO3- EMC@ EMC@
37 LAN_MDI3- MX4- TD4- 2 2
1 EMC
DL2 CL24
C LAN_MDI1- LAN_MDI1- C
1 10 0.01U_0201_25V6-K BOTH_GST5009 LF
LINE1IN LINE1OUT EMC@
LAN_MDI1+ 2 9 LAN_MDI1+ 2
LINE2IN LINE2OUT
3 8 EMC
GND1 GND2
LAN_MDI0- 4 7 LAN_MDI0- CHASSIS1_GND
LINE3IN LINE3OUT
LAN_MDI0+ 5 6 LAN_MDI0+
LINE4IN LINE4OUT
11 13
GND3 GND5
12
GND4
AZ3133-08F.R7G_DFN3020P10E10 JRJ1 ME@
EMC_NS@ 12
GND_4
11
GND_3
Place Close to TL1
10
LAN_MDO0+ 1 GND_2
EMC TX_DA+ 9
LAN_MDO0- 2 GND_1
TX_DA-
B B
LAN_MDO1+ 3
Vinafix.com RX_DB+ CHASSIS1_GND
LAN_MDO2+ 4
BI_DC+
LAN_MDO2- 5
BI_DC-
LAN_MDO1- 6
@ RX_DB-
RL14 1 2 0_0603_5% LAN_MDO3+ 7
@ BI_DD+
RL15 1 2 0_0603_5% LAN_MDO3- 8
@ BI_DD-
RL16 1 2 0_0603_5%
ALLTO_C10235-10839-L
EMC
8/ 16 Update RJ45 P/ N DC021608091 wei
CHASSIS1_GND
A A

Issued Date 2015/08/20 Deciphered Date 2016/08/20 LAN_Transformer
B 1.0
5 4 3 2 1
5 4 3 2 1
R175 1 @ 2 0_0402_5% REMOTE1+
Close to U1 REMOTE+_R R176 1 @ 2 0_0402_5% REMOTE2+ REMOTE1+

Near GPU&VRAM REMOTE2+
Near CPU core
REMOTE+_R
1
1
1 C46 C
1
1 C45 C 100P_0201_25V8J 2 Q16
C44 REMOTE-_R R177 1 @ 2 0_0402_5% REMOTE2- 100P_0201_25V8J 2 Q15 @ B MMBT3904WH_SOT323-3
2200P_0201_25V7-K @ B MMBT3904WH_SOT323-3 2 E @
3
@ 2 E @ REMOTE2-
3
2 REMOTE-_R R178 1 @ 2 0_0402_5% REMOTE1- REMOTE1-
+3VALW
D REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: +3VALW D
Trace width/space:10/10 mil Near CPU

Trace length:<8"
1
R36
13.7K_0402_1% R25
13.7K_0402_1%
2
NTC_V1
2
NTC_V2
SMSC thermal sensor
1
R287
placed near DIMM 100K_0402_1%_NCP15WF104F03RC
DIS@
R288
100K_0402_1%_NCP15WF104F03RC
+3VS
2
U1 @
2
1 8 EC_SMB_CK2
VDD SCL EC_SMB_CK2 7,20,44
2
REMOTE+_R 2 7 EC_SMB_DA2 R184 R185
1 D+ SDA EC_SMB_DA2 7,20,44
C47 @ 0_0402_5% 0_0402_5%
0.1u_0201_10V6K REMOTE-_R 3 6 @
@ D- ALERT#
1
2 R51 2 @ 1 4 5
+3VS T_CRIT# GND
10K_0402_5%
NCT7718W_MSOP8
EC_AGND
Address 1001_101xb for layout optimized, change the EC_AGND to GND
C C
+5VLP +5VLP
+5VLP
HW thermal sensor
2
2
1 R252 R253
C7 21.5K_0402_1% 21.5K_0402_1%
0.1u_0201_10V6K @ @
@
1
1
2
U4 @
1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1
VCC TMSNS1 NTC_V1 44
2 7 PHYST1 R6 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
44,54,55 EC_ON OT1 TMSNS2 NTC_V2 44
4 5 PHYST2 R7 1 @ 2 10K_0402_5%
Vinafix.com OT2 RHYST2
G718TM1U_SOT23-8
B over temperature threshold: B
RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C FAN Conn
+5VS
JFAN1 ME@
R52 1 @ 2 0_0603_5% +5VS_FAN 1
2 1
44 EC_FAN_SPEED 2
@ 3
0.1u_0201_10V6K
44 EC_FAN_PWM 3
1 1 4
C49 5 4
10U_0805_10V6K 6 GND1
GND2
2 2 ACES_85205-04001
C50
A A
Vinafix
Issued Date 2016/08/16 Deciphered Date 2017/08/15 Thermal sensor/FAN CONN

Custom
DG421 1.0

5 4 3 2 1
A B C D E
Mini-Express Card(WLAN/WiMAX)
+3VS
+3VS_WLAN
+3VS +3VS_WLAN
Need short
J2 @ JWLAN1 ME@
1
1 2 1 2
1 2 3 GND1 3.3VAUX1 4 R258 R259
9 USB20_P7 5 USB_D+ 3.3VAUX2 6 1
JUMP_43X79 1 @ T2 49.9K_0402_1% 49.9K_0402_1%
1 9 USB20_N7 7 USB_D- LED1# 8 1
C53
0.1u_0201_10V6K 9 GND2 PCM_CLK/I2S_SCK 10
SDIO_CLK PCM_SYNC/I2S_WS
2
@ 11 12
2 13 SDIO_CMD PCM_IN/I2S_SD_IN 14
15 SDIO_DATA0 PCM_OUT/I2S_SD_OUT 16 1 @ T3
17 SDIO_DATA1 LED#2 18
19 SDIO_DATA2 GND11 20
21 SDIO_DATA3 UART_WAKE# 22 UART_RX_DEBUG_R R256 1 @ 2 0_0402_5%
23 SDIO_WAKE# UART_RXD UART_RX_DEBUG 8
SDIO_RESET#
KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30
33 32 UART_TX_DEBUG_R R257 1 @ 2 0_0402_5%

35 GND3 UART_TXD 34 UART_TX_DEBUG 8
9 PCIE_PTX_C_DRX_P6 37 PETP0 UART_CTS 36
9 PCIE_PTX_C_DRX_N6 39 PETN0 UART_RTS 38 EC_TX_RSVD 1 2 0_0402_5%
R62 @
41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD R63 1 @ 2 0_0402_5%
9 PCIE_PRX_DTX_P6 43 PERP0 VENDOR_DEFINED2 42
9 PCIE_PRX_DTX_N6 45 PERN0 VENDOR_DEFINED3 44 1 2 0_0402_5%
R88 @
47 GND5 COEX3 46 EC_RX 44
10 CLK_PCIE_WLAN 49 REFCLKP0 COEX2 48
10 CLK_PCIE_WLAN# 51 REFCLKN0 COEX1 50 SUSCLK_R 1 2 0_0402_5%
R55 @
WLAN_CLKREQ_Q# GND6 SUSCLK PLT_RST# SUSCLK 10
10 WLAN_CLKREQ# R61 1 @ 2 0_0402_5% 53 52
PCIE_WAKE#_WLAN CLKREQ0# PERST0# BT_OFF# PLT_RST# 11,20,32,37,44
R262 1 @ 2 0_0402_5% 55 54 R53 1 2 1K_0402_5%
11,37,44 PCIE_WAKE# 57 PEWAKE0# W_DISABLE2# 56 WLAN_OFF# 1 2 0_0402_5% PCH_BT_OFF# 8
R56 @
1 2 0_0402_5% GND7 W_DISABLE1# PCH_WLAN_OFF# 8
R57 @
37,44 LAN_WAKE#
59 58 WLAN_SMB_DATA R58 1 @ 2 0_0402_5%
61 RSRVD/PETP1 I2C_DATA 60 WLAN_SMB_CLK 1 2 0_0402_5% SMB_DATA_S3 7,18
R59 @
63 RSRVD/PETN1 I2C_CLK 62 SMB_CLK_S3 7,18
65 GND8 ALERT# 64 EC_TX_R R89 1 @ 2 0_0402_5%
67 RSRVD/PERP1 RSRVD 66 EC_TX 44
2 2
69 RERVD/PERN1 UIM_SWP/PERST1# 68 +3VS_WLAN
GND9 UIM_POWER_SNK/CLKREQ1#
1
71 70
73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 R186
75 RSRVD/REFCLKN1 3.3VAUX3 74 100K_0402_5%
GND10 3.3VAUX4
77 76
GND15 GND14
2
ARGOS_NASE0-S6701-TS40
8/ 16 Update Conn. P/ N SP070013200 wei
3
Vinafix.com 3
4 4
Issued Date 2015/08/20 Deciphered Date 2016/08/20 NGFF WLAN&SSD

C
DG421 1.0

A B C D E
A B C D E
+USB_VCCA
C55 1 2
+
220U_6.3V_M
C1117 1 2
@ 47U_0805_6.3V6-M
LEFT SIDE USB3.0 PORT x2 C125 1 2
@ 1U_0402_10V6K
+5VALW +USB_VCCA C127 1 2

U2 @ 1U_0402_10V6K
5 1
1 IN OUT JUSB1 ME@
1
1
C128 2
1U_0402_6.3V6K GND USB30_TX_P1 C126 1 2 0.1u_0201_10V6K USB30_TX_C_P1 R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9
4 3 USB_OC1# 9 USB30_TX_P1 1 StdA_SSTX+
44 USB_ON# ENB OCB USB_OC1# 9 USB30_TX_N1 C124 1 VBUS
2 2 0.1u_0201_10V6K USB30_TX_C_N1 R96 1 @ 2 0_0402_5% USB30_TX_R_N1 8
9 USB30_TX_N1 USB20_P1 1 2 0_0402_5% USB20_P1_R 3 StdA_SSTX-
SY6288D20AAC_SOT23-5 1 R97 @
9 USB20_P1 7 D+
C140
1000P_0201_50V7-K USB20_N1 R93 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
9 USB20_N1 USB30_RX_P1 1 2 0_0402_5% USB30_RX_R_P1 6 D- GND_2 11
Low Active 2A 2
EMC_NS@
9 USB30_RX_P1
R94 @
4 StdA_SSRX+ GND_3 12
USB30_RX_N1 R98 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13
9 USB30_RX_N1 StdA_SSRX- GND_5
ALLTO_C190AG-10939-L
09/ 05 Update USBConn. P/ N DC021609011 wei
L13 EMC@
USB30_RX_N1 1 2 USB30_RX_R_N1
1 2
USB30_RX_P1 4 3 USB30_RX_R_P1
4 3
EXC24CH900U_4P USB20_P1_R
+USB_VCCA
USB20_N1_R D12 EMC@
USB30_RX_R_N1 9 USB30_RX_R_N1
L16 EMC@ 10 1 1
USB30_TX_C_N1 1 2 USB30_TX_R_N1
1 2 USB30_RX_R_P1 8 2 USB30_RX_R_P1
2
D11 9 2
D13
1
USB30_TX_C_P1 4 3 USB30_TX_R_P1 AZC199-02S.R7G_SOT23-3 USB30_TX_R_N1 7 4USB30_TX_R_N1
7 4
4 3 EMC@
EXC24CH900U_4P USB30_TX_R_P1 6 5 USB30_TX_R_P1
6 5
2
3
2 EMC@ 2
2
L8 EMC@ 8
USB20_P1 1 2 USB20_P1_R
1 2 AZ1045-04F_DFN2510P10E-10-9
1
USB20_N1 4 3 USB20_N1_R
4 3
EXC24CH900U_4P
EMC
EMC
+USB_VCCA
C2060 1 2
@ 1U_0402_10V6K
C2059 1 2
@ 1U_0402_10V6K
L30 EMC@ JUSB3 ME@

USB30_RX_N3 1 2 USB30_RX_R_N3
1 2 USB30_TX_P3 C2058 1 2 0.1u_0201_10V6K USB30_TX_C_P3 R3119 1 @ 2 0_0402_5% USB30_TX_R_P3 9
9 USB30_TX_P3 1 StdA_SSTX+
USB30_RX_P3 4 3 USB30_RX_R_P3 USB30_TX_N3 C2057 1 2 0.1u_0201_10V6K USB30_TX_C_N3 R3116 1 @ 2 0_0402_5% USB30_TX_R_N3 8 VBUS
3
Vinafix.com
USB30_TX_C_N3
USB30_TX_C_P3
USB20_P3
USB20_N3
1
4
4
EXC24CH900U_4P
L29
1
4
EXC24CH900U_4P
L17
1
4
EMC@
EMC@
3
3
2
3
USB30_TX_R_N3
USB30_TX_R_P3
USB20_P3_R
USB20_N3_R
9
9
USB30_TX_N3
9
9
USB20_P3
USB20_N3
USB30_RX_P3
USB30_RX_N3
USB20_P3
USB20_N3
USB30_RX_P3
USB30_RX_N3
R3103 1
R942 1
R3117 1
R3114 1
@
@
@
@
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
USB20_P3_R
USB20_N3_R
USB30_RX_R_P3
USB30_RX_R_N3
3
7
2
6
4
5
StdA_SSTX-
D+
GND_DRAIN
D-
StdA_SSRX+
GND_1
StdA_SSRX-
ALLTO_C190AG-10939-L
09/ 05 Update USBConn. P/ N DC021609011

GND_2
GND_3
GND_4
GND_5
10
11
12
13
wei
3
EXC24CH900U_4P
FOR ESD Close to Connector
D45 EMC@
USB30_RX_R_N3 9 USB30_RX_R_N3
10 1 1
USB20_P3_R +USB_VCCA
USB30_RX_R_P3 8 2 USB30_RX_R_P3
9 2
USB20_N3_R
USB30_TX_R_N3 7 7 4USB30_TX_R_N3
4
3
D43 USB30_TX_R_P3 6 6 5 USB30_TX_R_P3

5
1
EMC@ D34 3 3
1
EMC_NS@ 8
AZ1045-04F_DFN2510P10E-10-9
2
2
1
4 4
Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3.0 PORT (LEFT)

C
DG421 1.0

A B C D E
A B C D E F G H
SATA HDD Conn.
1 1
JHDD1
+5VS_HDD
10
SATA_PTX_DRX_P0 C66 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P0 9 10
9 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 9
C67 1 2 0.01U_0201_10V6K 8
9 SATA_PTX_DRX_N0 8
1 1 1 1 1 7 12
C74 C76 C75 C77 C78 SATA_PRX_DTX_N0 C68 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N0 6 7 GND2
33P_0201_50V8-J 33P_0201_50V8-J 0.1u_0201_10V6K 10U_0805_10V6K 10U_0805_10V6K 9 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P0 5 6
RF@ RF@ @ 9 SATA_PRX_DTX_P0 4 5
2 2 2 2 2 3 4 11
2 3 GND1
1 2
+5VS +5VS_HDD 1
Need short ELCO_006809610010846
For EMC ME@
J3 1 2 @
1 2
JUMP_43X79
2 2
+5VS +5V_ODD
Need Short
J4 @
1 2
1 2
JUMP_43X79
10U_0603_10V6K
0.1u_0201_10V6K
1 1
CD@
C85
2 2
C86
FOR 14"
SATA ODD Conn. FOR 15" 17''
Vinafix.com JODD1 ME@
SATA ODD FFC Conn
3 3
1
SATA_PTX_DRX_P1 14@ C70 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P1_14 2 GND_1 JODD2
9 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_PTX_C_DRX_N1_14 RX+
14@ C71 1 2 0.01U_0201_10V6K 3 1 ME@
9 SATA_PTX_DRX_N1 RX- SATA_PTX_DRX_P1 SATA_PTX_C_DRX_P1_15 1
4 15@ C79 1 2 0.01U_0201_10V6K 2
SATA_PRX_DTX_N1 14@ C72 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_14 5 GND_2 SATA_PTX_DRX_N1 15@ C80 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N1_15 3 2
9 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C73 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_14 6 TX- 4 3
9 SATA_PRX_DTX_P1 7 TX+ SATA_PRX_DTX_N1 15@ C81 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_15 5 4
GND_3 SATA_PRX_DTX_P1 15@ C82 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_15 6 5
8 7 6
9 DP +5V_ODD 8 7
+5V_ODD 10 +5V_1 8
11 +5V_2 14 9
12 MD GND1 15 10 GND1
13 GND_4 GND2 GND2
GND_5 HIGHS_FC5AF081-2931H
SUYIN_127382FB013S255ZL
8/ 16 Update Conn. P/ N SP01001YV00 wei
4 4
Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDD/ODD CONN

Custom 1.0
A B C D E F G H
5 4 3 2 1
D D
USB30_TX_N2
9 USB30_TX_N2 USB30_TX_P2
9 USB30_TX_P2
USB30_RX_N2
9 USB30_RX_N2 USB30_RX_P2
9 USB30_RX_P2
+3VALW
+3V_MUX +5VALW +5V_MUX
R133 1 @ 2 0_0402_5% R173 1 @ 2 0_0402_5%
U27 @ VBUS_P0
6 1
+3VS +5VS +5VALW IN OUT VBUS_P0
R134 1 @ 2 0_0402_5% R174 1 @ 2 0_0402_5% 3.3K_0402_1% 1 @ 2 R418
VBUS_EN
5
ISET GND
2
TYPE_C_OCP#
3A
4 3
EN/ENB OCB
Iset =6800/ 3.3k=2.06A SY6861B1ABC_SOT23-6
U26 11/ 16 SIT Reserve Power switch for OPC# flip issue wei
TYPE_C_OCP# 2 2
16
25
26
27
28
VBUS_EN 15 OCP_DET CC1271 CC1272 JP1 ME@
VBUS_EN 220P_0201_25V7-K 220P_0201_25V7-K
GND5
GND6
GND7
GND8
1 1
17 12 24 1
C
VMON
VMON CC1 14
CC1
CC2
A5
B5 +5VALW 1.5A VBUS_P0 Power_GND_B12 GND_A1 C
CC2 C_RX1_P_C 23 2 C_TX1_P_C
1 SSRXp1_B11 SSTXp1_A2
MUX_TX2_N C2076 1 C_TX2_N 1 + C_RX1_N_C C_TX1_N_C
11 2 0.1U_0201_6.3V6-K B3 C1333 22 3
C_TX2_1P/2N 10 MUX_TX2_P C2075 1 2 0.1U_0201_6.3V6-K C_TX2_P B2 C213 150U_B2_6.3VM_R35M SSRXn1_B10 SSTXn1_A3
C_TX2_1N/2P 47U_0805_6.3V6-M @ 21 4
USB30_RX_N2 C2068 1 2 0.1U_0201_6.3V6-K USB30_RX_N2_M 4 24 C_RX2_N A10 2 2 VBUS_B9 VBUS_A4
USB30_RX_P2 C2067 1 2 0.1U_0201_6.3V6-K USB30_RX_P2_M 5 SSRX_1P/2N C_RX2_1P/2N 1 C_RX2_P A11 20 5 CC1
SSRX_1N/2P C_RX2_1N/2P U6 SBU2_B8 CC1_A5
USB30_TX_N2 USB30_TX_N2_M 10Gbps 2:1 MUX MUX_TX1_N C2073 1 C_TX1_N C_DM C_DP
C2065 1 2 0.1U_0201_6.3V6-K 6 8 2 0.1U_0201_6.3V6-K A3 19 6
USB30_TX_P2 C2066 1 2 0.1U_0201_6.3V6-K USB30_TX_P2_M 7 SSTX_1P/2N C_TX1_1P/2N 9 MUX_TX1_P C2074 1 2 0.1U_0201_6.3V6-K C_TX1_P A1 A3 Dn2_B7 Dp1_A6
A2
SSTX_1N/2P C_TX1_1N/2P B1 VIN1 VOUT1 B3 C_DP 18 7 C_DM
2 C_RX1_N B10 C1 VIN2 VOUT2 C3 Dp2_B6 Dn1_A7
C_RX1_1P/2N 3 C_RX1_P B11 VIN3 VOUT3 CC2 17 8
C_RX1_1N/2P VBUS_EN D3 D1 TYPE_C_OCP# CC2_B5 SBU1_A8
GND1
GND2
GND3
+5V_MUX ON OC_FLAGB D2 TYPE_C_OCP# 9 16 9
13 ISET VBUS_B4 VBUS_A9
VCON_IN C_TX2_N_C C_RX2_N_C
1
FPF2595UCX_WLCSP12 15 10
SSTXn2_B3 SSRXn2_A10
A2
B2
C2
23 Realtek +3V_MUX R604
NC C_TX2_P_C C_RX2_P_C
10U_0805_10V6K
M1 21 19 523_0402_1% 14 11
0.1u_0201_10V6K
22 RP_SEL_M1 5V_IN SSTXp2_B2 SSRXp2_A11
M0
RP_SEL_M0 RTS5449 2 2
20 13 12
C2063
Rset 528 Min 1800mA Type 2000mA Max 2200mA
C2077
LDO_3V3 GND_B1 GND_A12
2
0.1u_0201_10V6K
4.7U_0402_6.3V6M
Rset 469 Min 2025mA Type 2250mA Max 2475mA
GND12
GND11
GND10
GND9
1 2 1 1
18 25
C2064
CC1273
REXT E-PAD
2
HIGHS_UB11246-15A0C-1H
2 1
32
31
30
29
R3150 RTS5449-GR_QFN24_4X4
6.2K_0402_1% VBUS_P0
Close Pin13 VBUS_P0
1
1
Close Pin19 09/ 02 Update Type-C Conn. DC021608291 wei
R3155
10U_0805_25V6K
4.7U_0805_25V6-K
0.47U_0402_25V6-K
0.47U_0402_25V6-K
0.47U_0402_25V6-K
0.47U_0402_25V6-K
200K_0402_1%
1
D38 1 1
1
Rp configuration
C918
C919
C922
C921
C920
C1334
1
+3V_MUX +3V_MUX VMON
EMC_NS@
Vinafix.com 2
@
2
2
2
Rp:1.5A (now)
R3139 R3142 R3149
2
10K_0402_5% @ 10K_0402_5% 10K_0402_1%
M1 M0 Note
2
B B
Rp:900mA 0 1 R3144/R3142 mount
1
M1 M0
Rp:1.5A 1 0 R3139/R3143 mount
2
R3144 R4674
Rp:3.0A 1 1 R3139/R3142 mount
@ 10K_0402_5% 10K_0402_5%
@ @
1
R943 1 2 0_0402_5% R3135 1 2 0_0402_5%
L23 EMC@ L31 EMC@

1 2 C_DP C_RX1_N 4 3 C_RX1_N_C CC1 C_DP
9 USB20_P2 1 2 4 3 C_DM
CC2
+3V_MUX For C_VBUS C_DM C_RX1_P C_RX1_P_C
2
4 3 1 2 D47 EMC_NS@ D48 EMC_NS@
power switch enable pin 9 USB20_N2 4 3 1 2
2
EXC24CH900U_4P EXC24CH900U_4P
R3146 R3137 1 @ 2 0_0402_5%
@ 10K_0402_5% R91 1 @ 2 0_0402_5%
R3136 1 @ 2 0_0402_5%
Power switch enable pin Note @
1
R944 2 1 0_0402_5%
VBUS_EN L32 EMC@
Low Active R3146 mount L24 EMC@ C_TX1_P 4 3 C_TX1_P_C
C_TX2_N C_TX2_N_C 4 3
2
3 4
R3141 High Active R3141 mount 3 4 AZC199-02S.R7G_SOT23-3 AZC199-02S.R7G_SOT23-3
1
10K_0402_5% 1 2
C_TX2_P 2 1 C_TX2_P_C 1 2
2 1 EXC24CH900U_4P
C_TX1_N R3138 1 @ C_TX1_N_C
1
EXC24CH900U_4P 2 0_0402_5%
R3107 2 @ 1 0_0402_5%
+3V_MUX R100 2 @ 1 0_0402_5%

For C_VBUS
power switch OCP pin L25 EMC@
PH at CPU side 09/ 06 wei C_RX2_P C_RX2_P_C
2
3 4 D36 EMC_NS@ D20 EMC_NS@

3 4 C_TX2_P_C 9 C_TX2_P_C C_TX1_P_C 9 C_TX1_P_C
R3147 10 1 1 10 1 1
@ 10K_0402_5%
C_RX2_N 2 1 C_RX2_N_C C_TX2_N_C 8 2 C_TX2_N_C C_TX1_N_C 8 2 C_TX1_N_C
9 2 9 2
2 1
Power switch OCP pin Note C_RX1_N_C 7 C_RX1_N_C C_RX2_N_C 7 C_RX2_N_C
1
EXC24CH900U_4P 7 4 4 7 4 4
A TYPE_C_OCP# A
Low Active R3147 mount R101 2 @ 1 0_0402_5% C_RX1_P_C 6
6 5 5 C_RX1_P_C C_RX2_P_C 6
6 5 5 C_RX2_P_C
High Active R3140 mount 3 3 3 3

2
R3140 8 8
@ 10K_0402_5%
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
For ESD
1
Issued Date 2015/08/20 Deciphered Date 2016/08/20 3D Camera

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DG421 1.0

5 4 3 2 1
5 4 3 2 1
For EMI RE1 1 2 0_0603_5%

For ESD +3VL V20B+
PLT_RST# CLK_PCI_EC RE2 1 2 33_0402_5%
EMC@
1
1 1 RE3 1 @ 2 0_0603_5%
CE1 CE2 Close EC +3VALW
RE261
220P_0201_25V7-K 22P_0402_50V8-J 470K_0402_5%
+3VL_EC +3VL_EC +3VL_EC_R
EMC@ EMC@ @
2 2 CE3 1 2 VCOREVCC
2
LE1 1 @ 2 0_0603_5% B+_Track
0.1u_0201_10V6K +3VL_EC All capacitors close to EC
1
CD@
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
1 1
1 1 1 @1 1 @1 CE4 CE5 +3VL_EC R260
0.1u_0201_10V6K 1000P_0201_50V7-K 47K_0402_5%
+3VS +3VL_EC_R @
2 2
2
D 2 2 2 2 2 2 EC_AGND D
1
Change RE6 to 0ohm jump LE2 1 @ 2 0_0603_5%
CE10
CE11
RE5
CE6
CE7
CE8
CE9
RE6 1 @ 2 0_0402_5% 10K_0402_5%
EC_AGND
2
LAN_WAKE#
minimum trace width 12 mil LAN_WAKE# 37,40
114
121
127
12
11
74
26
50
92
3
UE1
+3VS
VCORE
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VBAT
VCC
VSTBY(PLL)
AVCC
EC_FAN_SPEED RE10 1 2 10K_0402_5%
EC_FAN_PWM RE11 1 @ 2 10K_0402_5%
20 WRST# PWR_LED#
RE56 2 @ 1 0_0402_5% 4 24
7 KBRST# 2 1 0_0402_5% 5 KBRST#/GPB6 PWM0/GPA0 25 PWR_LED# 45 LPC_FRAME# 1 2 10K_0402_5%
RE59 @ RE7 @
+3VL_EC 7,32 SERIRQ 1 2 0_0402_5%LPC_FRAME#_EC 6 SERIRQ/GPM6 PWM1/GPA1 28 BATT_CHG_LED# 45
RE60 @
7,32 LPC_FRAME# 1 2 0_0402_5%LPC_AD3_EC 7 LFRAME#/GPM5 PWM2/GPA2 29 EC_VCCST_PWRGD BATT_LOW_LED# 45 1 2 100K_0402_5%
RE61 @ ENBKL RE9 @
7,32 LPC_AD3 LPC_AD2_EC LAD3/GPM3 PWM3/GPA3 EC_VCCST_PWRGD 11
DE1 1 2 @ RE62 1 @ 2 0_0402_5% 8 PW M 30
7,32 LPC_AD2 1 2 0_0402_5%LPC_AD1_EC 9 LAD2/GPM2 PWM4/GPA4 31 EC_FAN_PWM SYS_PWROK 11 CPU_VR_READY
RE63 @ RE270 1 2 10K_0402_5%
7,32 LPC_AD1 1 2 0_0402_5%LPC_AD0_EC 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM 39
RB751V-40_SOD323-2 RE64 @
7,32 LPC_AD0 CLK_PCI_EC 13 LAD0/GPM0 PWM6/SSCK/GPA6 34 EC_VCCST_EN_R BEEP# 30 EC_VCCST_EN EC_CMOS_ON#
LPC RE54 1 @ 2 RE275 1 @ 2 10K_0402_5%
1 2 7 CLK_PCI_EC 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120 LAN_WAKE# EC_VCCST_EN 13
WRST# 0_0402_5%
RE8 15 WRST# TMRI0/GPC4 124 SUSP# EC_LID_OUT# RE277 1 @ 2 10K_0402_5%
1 9
EC_SMI# EC_RX ECSMI#/GPD4 TMRI1/GPC6 SUSP# 46
100K_0402_5% 16
CE12 40
EC_RX EC_TX 17 PWUREQ#/BBO/SMCLK2ALT/GPC7 66
1U_0402_6.3V6K 40
EC_TX PLT_RST# LPCPD#/GPE6 ADC0/GPI0 NTC_V1 39
22 67 +3VALW +3VL_EC
2 11,20,32,37,40 PLT_RST# LPCRST#/GPD2 ADC1/GPI1 BATT_TEMP NTC_V2 39 For PMIC
23 68
4 EC_SCI# EC_RTCRST#_ON 126 ECSCI#/GPD3 ADC2/GPI2 69 BATT_TEMP 52,53
GA20/GPB5 ADC ADC3/GPI3 PM_SLP_SUS# 11
1
70
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72 B+_Track
CPU_VR_READY
ADP_I 53
59
+3VL_EC
RE273
0_0402_5% @
RE274
0_0402_5%
KSI[0..7] KSI0 58
LQFP-128L ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 0_0402_5% 1 @ 2 RE276 PSYS 53,59 @
45 KSI[0..7] KSI0/STB#
2
1
KSI1 59 78
KSI1/AFD# DAC2/TACH0B/GPJ2 SUSWARN# 11
KSO[0..17] KSI2 60 79 RE65 RPE4
45 KSO[0..17] 61 KSI2/INIT# DAC3/TACH1B/GPJ3 80 H_PROCHOT#_EC SUSACK# 11 EC_SMB_DA3 1 4
C KSI3 DAC 100K_0402_5% C
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 EC_SMB_CK3 2 3
KSI4 DAC5/RIG0#/GPJ5 ENBKL 33
KSI5 63
KSI5
2
+3VL_EC KSI6 64 85 EC_ON_GPIO 0_0402_5% 1 @ 2 RE57 2.2K_0404_4P2R_5%
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 EC_ON 39,54,55
KSI7
36 KSI7 PS2DAT0/TMB1/GPF1 87 EC_SMB_CK3 PBTN_OUT# 11
KSO0 +5VALW
EC_SMB_CK1 1 37 KSO0/PD0 GPF2 88 EC_SMB_DA3 EC_SMB_CK3 55
RPE2
EC_SMB_DA1 EC_SMB_DA1
PAD @
IT1
KSO1
KSO1/PD1 Int. K/B PS2 GPF3 EC_SMB_DA3 55 USB_ON#
2 3 PAD 1 @ KSO2 38 89 1 TE1 @ RE15 1 2 100K_0402_5%
1 4 EC_SMB_CK1 1 IT2 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 EC_LID_OUT#
PAD @ KSO3
1 IT3 40 KSO3/PD3 PS2DAT2/GPF5 EC_LID_OUT# 45
PAD @ KSO4
1 IT4 41 KSO4/PD4 96
2.2K_0404_4P2R_5% PAD @ KSO5 EXTERNAL SERIAL FLASH +3VL_EC
IT5 42 KSO5/PD5 GPH3/ID3 97 CAPS_LED# 45
KSO6
KSO7 43 KSO6/PD6 GPH4/ID4 98 PCH_PWR_EN 46,55
44 KSO7/PD7 GPH5/ID5 99 EC_BKL_EN 45
KSO8
+3VS 1 45 KSO8/ACK# GPH6/ID6 PCH_PWROK 11
KSI7 PAD @ KSO9 SUSP# RE18 1 @ 2 100K_0402_5%
1 IT6 46 KSO9/BUSY 101 EC_SPI_CS0#
KSI6 PAD @ KSO10
1 IT7 51 KSO10/PE NC1 102 EC_SPI_SI
RPE3 WRST# PAD @ KSO11 SUSP# RE19 1 2 100K_0402_5%
1 4 EC_SMB_CK2 IT8 KSO12 52 KSO11/ERR# NC2 103 EC_SPI_SO
EC_SMB_DA2 KSO12/SLCT SPI Flash ROM NC3 EC_SPI_CLK SYSON_R
2 3 KSO13 53 105 RE21 1 2 100K_0402_5%
KSO13 NC4
For factory EC flash KSO14 54
KSO14 EC_VCCST_EN
2.2K_0404_4P2R_5% KSO15 55 RE269 1 @ 2 100K_0402_5%
KSO16 56 KSO15 108 ACIN#
KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW# EC_VCCIO_EN RE268 1 2 100K_0402_5%
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 45
@
ON/OFF 110 82 1 TE2 @

EC_ON RE58 2 45 ON/OFF PWRSW# EGAD/GPE1
@ 1 0_0402_5% 111 SM Bus 83 VDDQ_PGOOD 55
EC_SMB_CK1 115 XLP_OUT EGCS#/GPE2 84 EC_VPP_PWREN Add to fix Reset&PWRGD test fail issue
52,53 EC_SMB_CK1 EC_SMB_DA1 116 SMCLK1/GPC1 EGCLK/GPE3 EC_VPP_PWREN 55
52,53 EC_SMB_DA1 PECI_EC SMDAT1/GPC2 VDDQ_PGOOD CE51 1
4 H_PECI RE24 1 2 43_0402_5% 117 GPIO 77 2 0.01U_0201_10V6K
118 SMCLK2/PECI/GPF6 GPJ1 100 EC_MUTE# 30
GPG2
37 LAN_PWR_ON# EC_SMB_CK2 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106
7,20,39 EC_SMB_CK2 EC_SMB_DA2 95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 104 EC_CMOS_ON# 33 PM_SLP_S4#
Vinafix.com CE50 1 2 EMC_NS@ 1000P_0201_50V7-K
+3VL 7,20,39 EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 SYSON_R 1 2 0_0402_5% ME_FLASH 8
RE271 @ SYSON
DTR1#/SBUSY/GPG1/ID7 119 SYSON 55
BKOFF#
CRX0/GPC0 123 BKOFF# 33 EC_VCCIO_EN PM_SLP_S3#
RE55 2 @ 1 0_0402_5% CE21 1 2 EMC_NS@ 1000P_0201_50V7-K
1 2 0_0402_5% 112 CTX0/TMA0/GPB2 18 EC_VCCIO_EN 13
RE27 @
1 2 0_0402_5% 125 VSTBY0 RI1#/GPD0 21 PM_SLP_S3# 11,13
RE272 @ PM_SLP_S4# 11
B 59 EC_VR_ON GPE4 RI2#/GPD1 76 B
WAKE UP NOVO# 45 SYSON CE13 1 2 EMC_NS@ 1000P_0201_50V7-K
PM_SLP_S3# DE2 1 2 TACH2/GPJ0 48
TACH1A/TMA1/GPD7 47 EC_FAN_SPEED EC_TS_ON 33
@ RB751V-40_SOD323-2 EC_FAN_SPEED 39
USB_ON# 33 TACH0A/GPD6 19 VGA_AC_DET
41 USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 VGA_AC_DET 20 EMC Request
2
35 GPIO 20
11 DPWROK_EC 93 RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# 45
11 EC_RSMRST# CLKRUN#/GPH0/ID0 Reserve for VGA_AC_DET
PCIE_WAKE# 2 DE3
11,37,40 PCIE_WAKE# CK32KE/GPJ7
1
128 Clock RB751V-40_SOD323-2
+3VL 11 AC_PRESENT CK32K/GPJ6 @
PM_SLP_S4#
RE34 1 @ 2 H_PROCHOT# 4,55

RE35 1 @ 2 10K_0402_5% ON/OFF 53,59 VR_HOT# 0_0402_5%
AVSS
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
EC_RTC_RST# 10
1
RE36 1 @ 2 10K_0402_5% BKOFF# 1
IT8586E-AX_LQFP128_14X14 RE267 CE14
1
LID_SW#
27
49
91
75
113
122
RE38 2 1 100K_0402_5% 100_0402_5% 47P_0201_25V8-J

EMC_NS@
2
1
QE3 D
1 2
EC_RTCRST#_ON 2
RE40 1 2 10K_0402_5% BKOFF# QE1 D G
EC_AGND H_PROCHOT#_EC 2 +3VL
G @ S 2N7002KW_SOT323-3
3
1
2N7002KW_SOT323-3 S RE50
for EC version update to EX, manual modify PN to FX
2
100K_0402_5%
RE42 @
100K_0402_5%
2
1
+3VL +3VS ACIN# RE262 1 @ 2 0_0402_5%
PECI_EC 11 ACIN#
EMC_NS@ CE15 1 2 47P_0201_25V8-J
+3VL_EC
BATT_TEMP
1
EMC_NS@ CE16 1 2 100P_0201_25V8J 1 D QE2
A GPG2 RE43 2 @ 1 10K_0402_5% CE19 2 A
ACIN 53
ACIN# EMC_NS@ CE17 1 2 100P_0201_25V8J 0.1u_0201_10V6K G
GPG2 RE44 2 1 10K_0402_5% EC_SPI_CS0# RE45 2 @ 1 0_0402_5% SPI_CS0#
SPI_CS0# 7 NOVO# ON/OFF @ CE18 1 2 1U_0402_6.3V6K 2 S 2N7002KW_SOT323-3
3
GPG2 RE46 2 @ 1 10K_0402_5% @
EC_SPI_SI RE47 2 @ 1 0_0402_5% SPI_SI
SPI_SI 7
when mirror, GPG2 pull high
EC_SPI_SO SPI_SO
when no mirror, GPG2 pull low RE48 2 @ 1 0_0402_5% 1
Vinafix
SPI_SO 7
CE48
0.01U_0201_10V6K Title
EC_SPI_CLK RE49 2 @ 1 0_0402_5% SPI_CLK EMC_NS@ Security Classification LC Future Center Secret Data
SPI_CLK 7 2
Issued Date 2015/08/20 Deciphered Date 2016/08/20 EC ITE8586LQFP
C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
ON/OFF switch +3VL +3VALW

Novo button NOVO_BTN#
2
SW2
1
R82 R83 4 D24
1
100K_0402_5% 100K_0402_5% AZ5123-01F.R7GR_DFN1006P2X2
@ 5 EMC@
R261 1 @ 2 0_0402_5%
2
NTC325-EKJ-A160T_3P
2
NOVO# D15 2 8/ 16 Del Power Button wei
44 NOVO#
1 NOVO_BTN#
ON/OFFBTN#
ON/OFF R85 1 @ 2 0_0402_5% 3 @
BAT54CW_SOT323-3 8/ 31 Update the P/ N SN100008W00 wei
1
D25
1
D D
+3VALW +3VL
LID switch
2
2
2
EMC@
2
R111 R114
100K_0402_5% 100K_0402_5%
@
1
ON/OFFBTN# R119 1 @ 2 0_0402_5% ON/OFF 1
ON/OFF 44
C1104
U14 100P_0201_25V8J
J5 1 2 @ 1
GND 2
1 LID_SW#
SHORT PADS C1105 3
0.01U_0201_10V6K OUTPUT LID_SW# 44
J6 1 2 @
R264 1 @ 2 2 +VCC_LID 2
+3VL VCC
SHORT PADS 0_0402_5%
AH9247-W-7_SC59-3
K/B Connector KSI[0..7]

KSI[0..7] 44 KB Backlight Connector
KSO[0..17] JKB1
KSO[0..17] 44
+5VS
32 33
ON/OFFBTN# 31 32 GND1 34
PWR_LED# +5VALW
R285 1 @ 2 0_0402_5% 30 31 GND2
EMC_NS@ NUM_LED#_R 30 +VCC_KB_LED
PWR_CAPS_LED 1 2 100P_0201_25V8J R279 1 15@ 2 0_0402_5% 29
C133 44 NUM_LED# KSO17_R 29 Q31
KSO17 R281 1 15@ 2 0_0402_5% 28
1
KSO16_R 28 R265 LP2301ALT1G_SOT23-3
KSO16 R280 1 15@ 2 0_0402_5% 27
10K_0402_5% KBL@
KSI1 26 27
KBL@ 3 1
D
KSI7 25 26
KSI6 24 25
KSO9 23 24 1 1
2
23 R266 C1106 C1107
G
KSI4 22
2
22 1 2 10U_0603_6.3V6M 0.1u_0201_10V6K
KSI5 21
21 KBL@ KBL@
KSO0 20 2 2
EMC@ 20 100K_0402_5% 1
CAPS_LED# 1 2 100P_0201_25V8J KSI2 19
C117 19 KBL@ C1108
KSI3 18 0.01U_0201_10V6K
NUM_LED#_R KSO5 17 18
C C118 1 2 100P_0201_25V8J 17 KBL@ C
KSO1 16 2
8/ 23 PWR LED function under check KSI0 15 16
EMC_15@ 15
KSO2 14
KSO4 13 14 To be confirm Pin define
KSO7 12 13
1
12 D
KSO8 11 EC_BKL_EN 2
11 Q32
CAPS_LED# NUM_LED#_R PWR_LED# KSO6 10 44 EC_BKL_EN G
10 2N7002KW_SOT323-3 JKBL1 ME@
KSO3 9 +VCC_KB_LED 1
9 KBL@
KSO12 8 S 2 1
KSO13 7 8 1 2
3
7 C1109 3 6
KSO14 6 0.1u_0201_10V6K 4 3 GND2 5
KSO11 5 6 4 GND1
1
5 KBL@ 1
KSO10 4 2
D22 D23 D46 4 C1110 CVILU_CF50041D0RN-10-NH
1
KSO15 3 0.1u_0201_10V6K
AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 CAPS_LED# CAPS_LED#_R 3
EMC@ EMC_15@ EMC@ R275 1 @ 2 0_0402_5% 2
@
44 CAPS_LED# PWR_CAPS_LED 2
R84 1 2 1 2
+3VALW 1
200_0402_1%
2
CVILU_CF32321D0RONH
ME@
2
8/ 31 Update KBL Conn. P/ N SP011608241 wei

For EMC
Finger Print Connector TP/B Connector

+3VS TP_PWR
FP_PWR
To be confirm Pin define R141 1 @ 2 0_0402_5%
+3VS
0.1u_0201_10V6K
JFP1 1
R3120 1 @ 2 0_0402_5% 1 JTP1 ME@
USB20_N4 USB20_N4_CONN 1 EC_LID_OUT#_R
R3122 1 @ 2 0_0402_5% 2 R4675 1 @ 2 0_0402_5% 1
9 USB20_N4 USB20_P4 USB20_P4_CONN 2 44 EC_LID_OUT# TP_INT# 1
R3121 1 @ 2 0_0402_5% 3 R4676 1 @ 2 0_0402_5% 2 7
0.1u_0201_10V6K
9 USB20_P4 4 3 2 8 PCH_TP_INT# 3 2 GND1
C114
1 4 TP_I2C_SDA0 3
5 4 8
6 5 8 TP_I2C_SDA0 TP_I2C_SCL0 5 4 GND2
7 6 8 TP_I2C_SCL0 6 5
FP@
2 7 TP_PWR 6
8
C2061
Vinafix.com
100P_0201_25V8J
100P_0201_25V8J
USB20_N4_CONN 8
EMC_NS@
EMC_NS@
1 1 ELCO_04-6809-606-110-846-+
9
10 GND1 TP_I2C_SCL0
USB20_P4_CONN GND2 TP_I2C_SDA0
B
HIGHS_FC5AF081-2931H 2 2 B
C115
C116
3
2
3
DT1
DT2
EMC_NS@
FP@
8/ 23 Update FG Conn. P/ N SP01001YV00 wei
11/ 16 SIT change to 6Pin I2C interface T/ P wei

1
AZC199-02S.R7G_SOT23-3 For EMC
1
9/ 7 Add for ESD wei
BATT_LOW_LED# 1 2
44 BATT_LOW_LED# LED2 R143 1 2 470_0402_5%
+3VALW
L-C192JFCT-LCFC_SUPER_AMBER
1
D18
1
EMC_NS@
2
2
BATT_CHG_LED# 1 2
44 BATT_CHG_LED# LED3 R144 1 2 1.5K_0402_5%
+5VALW
L-C192WDT-LCFC_WHITE
1
D19
1
EMC_NS@
2
2
A A
PWR_LED#
PWR_LED#
44 PWR_LED# LED4 1 2 R4672 1 2 1.5K_0402_5%
+5VALW
1
L-C192WDT-LCFC
D16
1
EMC_NS@
2
PWR_LED Change to M/ B (310->320) 08/ 17

2

Issued Date 2015/08/20 Deciphered Date 2016/08/20 KBD/PWR/IO/LED/TP Conn.
Custom 1.0
5 4 3 2 1
A B C D E
Load Switch
+5VALW To +5VS +3VS, C173 --> 2.74ms
+3VALW To +3VS +5VS, C176 --> 2.03ms
VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm Need Short
R64 1 @ 2 0_0402_5% 3VSON
+5VALW U13 +5VS
1 14 J12 @
2 IN1_1 OUT1_2 13 +5VS_LS 1 2
1 IN1_2 OUT1_1 1 2 1
1 5VSON 3 12 C176 1 2 1000P_0201_50V7-K JUMP_43X118 1

SUSP# R27 1 @ 2 0_0402_5% 5VSON EN1 CT1 C174 +3VALW
C177 4 11 0.1u_0201_10V6K +5VALW
+5VALW VBIAS GND
1U_0402_6.3V6K @
+3VALW 2 3VSON 5 10 C173 1 2 2200P_0402_25V7-K 2 +3VS
1 1 EN2 CT2 J11 @
C180 C179 6 9 +3VS_LS 1 2
1U_0402_6.3V6K 1U_0402_6.3V6K 7 IN2_1 OUT2_2 8 1 2
2 2 IN2_2 OUT2_1 JUMP_43X118
1 1
15 C175 1 1 1
GPAD 0.1u_0201_10V6K
C178
1U_0402_6.3V6K
Need Short C2078
0.1u_0201_10V6K
C2080
0.1u_0201_10V6K
C2079
0.1u_0201_10V6K
G5016KD1U_TDFN14_2X3 @
2 @ 2 @ @ @
2 2 2
Change the main source to SA000067600 (GMT) 7/ 16
EMC
+5VALW
+3VALW Need short +3VALW_PCH +1.8VALW +1.8VS
2 2
J7 @ Q35 0.6A
1
1 2
1 2 3 1
D
R155
JUMP_43X79
100K_0402_5% 1 LP2301ALT1G_SOT23-3 1
@
C201
0.1u_0201_10V6K
C203
0.1u_0201_10V6K
1
G
2
2
C1103
PCH_PWR_EN#_R PCH_PWR_EN#
R158 1 @ 2 100K_0402_5% 22U_0603_6.3V6-M LP2301ALT1G_SOT23-3 Id=3.2A 2 2
@ 1 1
2 Q29 3 1 @
C204
0.1u_0201_10V6K
C205
0.1u_0201_10V6K
S
D
1
Q30 D SUSP R201 1 @ 2 0_0402_5%

PCH_PWR_EN 2
44,55 PCH_PWR_EN 1 2 2
G C130
G
2
1
0.01U_0201_10V6K 1
@ S 2N7002KW_SOT323-3 @ R202
C202
0.1u_0201_10V6K
2
3
1
@ 470K_0402_5%
R162 PCH_PWR_EN#_R 2
2
100K_0402_5%
@ 1
2
C131
0.1u_0201_10V6K
@
2
1
R87
100K_0402_5%
@ 8/ 29 Add +1.8VS Circuit for Audio wei
3
Vinafix.com +5VLP +5VALW
2
For DisCharge
3
1
R156 R157 +0.6VS +2.5V_DDR

100K_0402_5% 100K_0402_5%
@ 1
1
2
R159 R278
SUSP 47_0603_5% 200_0402_5%
34 SUSP
@ @
2
2
1
1
Q10 D D Q11 D Q33
2 2 SUSP 2 SUSP
44 SUSP# G G G
S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3

3
3
@ @
4 4
08/ 29: Need double check enable signal and the resistance
Issued Date 2015/08/20 Deciphered Date 2016/08/20 DC V TO VS INTERFACE

Custom 1.0
A B C D E
5 4 3 2 1
B2 A2
D
+3VLP PCH_PWR_EN# 2 D
Q25,+3V_PCH
V
V
AC A1
M ODE VIN
A2 A4 B5
V V
3 +3V_PCH
PU301 PU904
V
B+
BATT BATT V +3VALW
1
DPWROK_EC
V
MODE
V V V
B1
4
PCH_RSMRST#
EC 14
5 PM_DRAM_PWRGD
PBTN_OUT#
V
EC_ON PM_SLP_S3# PCH 15
PM_SLP_S4# H_CPUPWRGD CPU
A3 B4
V V
PM_SLP_S5#
PM_SLP_SUS# 6
CPU_PLTRST# 16
V
12
PCH_PWROK
V V
C C
B3 13
SYS_PWROK
V
ON/OFF V
NOVO
NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE
+1.35V
V
11 VR_REDY SYSON 7 PU801
PU501
V
DGPU_PWROK
DGPU_PWR_EN
10
Va (DIS)
+1.5VS_VGA
V
PU901 VR_ON Q31
V
PU601
V
+CPU_CORE
V
Vinafix.com +5VS
B B
Q32 +1.05VSP_VGA
V
SUSP#,SUSP 9 +3VS PU702
VGA
V
PU602
V
+1.5VS +3VS_VGA
V
Q27
PU502
V
Vinafix +0.675V
8
SUS_VCCP PU701
V
+1.05VS
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 Power sequence block

Custom 1.0
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 Virtual symbol

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
CPU Thermal Holex3 GPU Thermal Holex2 PCB Fedical Mark PAD
Close to RJ45 Close to Audio jack
H1 H2 H3 H4 H5 H6 H7
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4 FD5 FD6
D 1 D
1
pad_c6p0d4p0 pad_c6p0d4p0 pad_c6p0d4p0 pad_c7p0d3p3 pad_c7p0d3p3 CHASSIS1_GND
pad_ct7p0b8p0d3p0 pad_ct7p0b8p0d3p0
DC-IN x2 WLAN Standoff

H10 H11 H12 H13 H15 H16
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
C C
pad_ct5p5d2p5 pad_ct7p0b6p0d3p3 pad_ct7p0d3p0 pad_ct7p0d3p0 pad_ct5p0d2p5 pad_cb5p5d2p5
H18 H19
H17 HOLEA HOLEA H20
HOLEA HOLEA
1
1
1
1
PAD_CT7P0D3P0 PAD_CT7P0D3P0
pad_o2p6x2p9d2p6x2p9n pad_c3p3d3p3n
SH1 ME@ SH2 ME@ SH3 ME@

1 1 1 SH12 ME@
B B
1 1 1 1 1 1
Vinafix.com 1 1 1 1
1
SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
SPRING_FINGER_6.2X1.64
1 1 1 SH13 ME@ SH9 ME@

1 1 1 SH10 ME@ SH11 ME@
1 1
1 1 1 1
1 1
SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64
SPRING_FINGER_6.2X1.64 SHIELDING_SUL-35A2M_9P2X3P3_1P
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
USB3.0 Shielding
DDR4 Shielding
A A

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Hole
B 1.0
5 4 3 2 1
5 4 3 2 1
Silergy
LV5028AGQV
VQFN40_5X5 +1.05VGS/1.5A
D
LDO D
EN
EN_VGA For DDR4 PGOOD NA
PCH_PWR_EN EN
Silergy
+5VLP/ 100mA LV5028AGQV
V20B+
Silergy VQFN40_5X5 +1.0VALW/6A
SY8288CRAC Converter
QFN20_3X3 +5VALW/6A FOR PCH PGOOD NA
Adaptor 45W/65W Converter

EC_ON EN FOR SYSTEM PGOOD NA
Silergy
+3VLP/ 100mA LV5028AGQV
Silergy +1.8VALW/1A
SY8286BRAC VQFN40_5X5
Converter
QFN20_3X3 +3VALW/ 5A PCH_PWR_EN EN
For GPU PGOOD NA
Converter
C EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD C
Silergy
LV5028AGQV +2.5V/1A
Silergy +1.2V/7A VQFN40_5X5
LV5028AGQV LDO
EC_VPP_PWREN EN PGOOD NA
SYSON S5 VQFN40_5X5 For DDR4
TI CPU_DRAMPG_CNTL S3 Switch Mode +0.6VS/2A
FOR DDR4
BQ24780SRUYR PGOOD VDDQ_PGOOD
Battery Charger
Switch Mode
MPS +1.35V/8A
NB685GQ-Z
QFN16_3X3
Vinafix.com FBVDDQ_PWR_EN EN Switch Mode
SMBus FOR VRAM
B PGOOD NA B
Richtek
RT8812AGQW
Battery WQFN20_3X3 +VGA_CORE/31A
VID
polymer Switch Mode
PXS_PWREN EN FOR GPU VDDC PGOOD DGPU_PWROK
2S1P
CPU Core/23A
Onsemi
NCP81216MNR2G VCCGT/25A
QFN60_7X7
VID Switch Mode VCCSA/7A
EC_VR_ON EN FOR CPU Core
PGOOD CPU_VR_READY
A A

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-Power Diagram
Custom
DG421 1.0

5 4 3 2 1
5 4 3 2 1
VIN
EMC@
HCB2012KF-121T50_0805
JDCIN1 PF101 PL101
1 ADPIN 1 2 APDIN_F 1 2
1 2
GND1 3 7A_24VDC_F1206HI7000V024TM EMC_NS@
GND2
1000P_0201_50V7-K
4 HCB2012KF-121T50_0805
GND3
470P_0201_50V7-K
470P_0201_50V7-K
1000P_0201_50V7-K
5 PL102
GND4 6 1 2
EMC@ PC101
EMC@ PC102
GND5
2
D 7 D
EMC@ PC103
EMC@ PC104
GND6
1
HIGHS_PJSS0026-8B01H
ME@
+3VL
1
PR102
1.5K_0402_1%
VCCRTC 2
1
PR103
C C
45.3K_0402_1%
RTC_VCC
2
1
JRTC1
3 2 PR101 1 1
2 1
PD101 1K_0603_5% 3 2
GND1
2
@ BAT54CW_SOT323-3 4
PC105 GND2
1U_0402_6.3V6K
1
HIGHS_WS33020-S0351-HF
ME@
JRTC2
1
2 1
3 2
4 GND1
GND2
RTC_VCC 20MIL
+3VL 20MIL HIGHS_WS33020-S0351-HF
VCCRTC 20MIL ME@
B
Vinafix.com No charge RTC
RTC Battery for GCM BOM

(2nd source and quoted price )
with 35mm cable
B
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-DCIN / RTC charger

Custom 1.0
5 4 3 2 1
5 4 3 2 1
VBAT
JBATT1
EMC@ BATT+
D HCB2012KF-121T50_0805 D
1 PL201
1 2 1 2
2 EC_SMCA
9
10 GND1 3
3
4 EC_SMDA
PR202 1
1
2100_0402_1%
2
EC_SMB_CK1
EC_SMB_DA1
44,53
44,53 1 2 2S1P polymer battery
GND2 4
5
5
6
PR201 100_0402_1%
PL202
voltage level: +6V ~
6
7
7 HCB2012KF-121T50_0805 8.4 V
2
8 EMC@
8
1
PC201 PC202
ME@ 1000P_0201_50V7-K 0.01U_0201_25V6-K
EMC@ EMC@
2
SUYIN_125022HB008M202ZL
PD201
1
EMC_NS@
PR209
1 2 +3VALW
100K_0402_1%
PR213
C BATT_TEMP_IN 1 2 C
BATT_TEMP 44,53
10K_0402_5%
1
1
PD202
AZ5215-01F_DFN1006P2E2
EMC_NS@
2
2
B
Vinafix.com B
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-BATTERY CONN/OTP

Custom 1.0
5 4 3 2 1
5 4 3 2 1
AON6414AL_DFN8-5
PQ312
PQ311
AON7408L_DFN8-5
N2
VIN N1
PR301
1 1 PJ301 @ 0.01_1206_1%
2 2 JUMP_43X118 V20B+
5 3 3 5 1 2 1 4
1 2
2 3
D D
10U_0603_25V6-M
10U_0603_25V6-M
470P_0201_50V7-K
220P_0402_50V7K
470P_0402_50V7K
680P_0402_50V7K
4700P_0402_50V7-K
6800P_0402_25V7-K
0.022U_0402_25V7K
0.01U_0201_25V6-K
4
4
PC301
1
EMC_NS@
EMC_NS@
PC303
PC304
EMC@ PC329
EMC@ PC330
EMC@ PC331
EMC@ PC332
EMC@ PC333
EMC@ PC334
1
PC302
PR302
2
4.7_0603_5%
5
0.1U_0201_25V6-K
2
PQ314
PC305
AON6324_DFN8-5
1 2
BQ24780_BATDRV 4
2
PC306
PC307 0.1U_0201_25V6-K
1
1U_0603_25V6K
3
2
1
2
PR303
499K_0402_1% PC308
0.01U_0201_25V6-K
1
VIN BATT+
2
BAT54CW_SOT323-3
PD302
V20B+
2200P_0201_25V7-K
PR313 PR315 :432K and 64.9k
10U_0805_25V6K
10U_0805_25V6K
VIN
1
1
2
EMC@ PC310
PC313
4.02K_0603_1%
4.02K_0603_1%
change to 43k and 7.15k.
ACN
ACP
PR310
PR311
PC314
vin detect volatege level:16.8V
1
2
PC309:0.1u change to 0.01u
5
PR314 BQ24780_VDD
2
1
C PR313 10_1206_5% C
decrease ACDET deassert time 7.15K_0402_1% 1U_0603_25V6K
ACP
ACN
1 2 43K_0402_1% PC315
1
PR315 2 1 780_VCC 28 24 1 2 PQ316
VCC REGN
2
2.2U_0603_10V6-K PC316 4
1 2 ACDET 6 AON7408L_DFN8-5
PC309 ACDET PR316 PC318
0.01U_0402_25V7K 25 BST_CHG
1 2 2 1
BTST 2.2_0603_5% PR317
3
2
1
BQ24780SRUYR_QFN24_4X4 0.047U_0603_16V7K 0.01_1206_1%
3
CMSRC HIDRV
26 DH_CHG PL302 BATT+
1 2 CHG 1 4
2 PR339 @120K_0402_1% 4 4.7UH_PCMB053T-4R7MS_4A_20%
ACDRV
1
2 3
LX_CHG
5
BQ24780_VDD 100K_0402_1% 2 PR324 @1 27 PR321
PHASE 2.2_0805_5%
10U_0805_25V6K
10U_0805_25V6K
ACIN_R
2
0_0402_5% 1 2 PR325 @ 5 EMC_NS@
PC319
44 ACIN ACOK
PC320
2
0_0402_5% 1 2 PR320 @ EC_SMB_DA1_R 11
SDA
1
44,52 EC_SMB_DA1 PU301 23 DL_CHG PQ317 4
LODRV
1
0_0402_5% 1 2 PR322 @ EC_SMB_CK1_R 12 22 AON7408L_DFN8-5 PC321
44,52 EC_SMB_CK1 SCL GND 1000P_0402_50V7K
2
EMC_NS@
3
2
1
0_0402_5% 1 2 PR323 @ ADP_I_R 7 29
0.1U_0201_25V6-K
0.1U_0201_25V6-K
44 ADP_I IADP PAD
BQ24780_BATDRV
2
IDCHG 8 18
PC322
PC323
IDCHG BATDRV
9 PR338 10_0603_5%
PMON
1
59 Psys 17 2 1
BATSRC
100P_0201_25V8J
100P_0201_25V8J
SRP_R
2
20 2 1 SRP
20K_0402_1%
0.1U_0201_25V6-K
SRP
2
10 PR328 10_0603_5%
Vinafix.com 44,59 VR_HOT# PROCHOT#
2
PC324
PC325
PR340
PC327
100P_0201_25V8J
1
13
CMPIN
1
BATPRES#
@ 14
TB_STAT#
PC1108
CMPOUT
1
19 SRN_R 2 1 SRN
B
ILIM 21 SRN PR329 10_0603_5% B
ILIM
2
PR330
16
15
0_0402_5%
1
1 2 ILIM_R@ 1 2 TB_STAT#
+3VALW BATT_TEMP 44,52
PR331 14.7K_0402_1%
316K_0402_1% PR332
0.1U_0201_25V6-K
1
2
PC328
PR333
100K_0402_1%
1
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-CHARGER

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
+3VALW
2
PR407 @
100K_0402_5%
V20B+ @
1
PJ401 PU401
2 1 +3V_VIN 5 9 +3V_PWRGD
2 1 4 IN1 PG 1 +3VBS 1 2
10U_0805_25V6K
10U_0805_25V6K
0.01U_0201_25V6-K
3 IN2 BS
1
PC403
+3VALW
SY8286BRAC_QFN20_3X3
JUMP_43X79 2 IN3 0.1U_0603_25V7-M
EMC@ PC401
PC402
PC452
IN4 6 2.2UH_PCMB053T-2R2MS_5.5A_20% @
LX1
2
7
8 GND1 LX2
19
20 +3VLX 1
PL401
2 +3VALW_P 2
PJ402
1
5A
18 GND2 LX3 2 1
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
D
21 GND3 D
GND4
1
JUMP_43X79
+3/5VALW_EN 12 14 +3VALW_P PR403
PC434
PC432
PC431
PC435
+3V_VIN EN1 OUT
11
EN2
2.2_0805_5%
Vout=3.3V± 5%
2
13 +3VALW_FB EMC_NS@
FF
10
NC1 Vset=3.37V± 1.5%
2
15
NC2 100mA +3VLP
1
16 17 OCP=12A
1M_0402_5%
0.1U_0201_25V6-K
NC3 LDO
1
PR401
1
PC410 OVP=(1.15~1.25)*Vout
PC408
4.7U_0603_6.3V6K
1
@ 1000P_0402_50V7K
2
EMC_NS@ UVP=(0.55~0.65)*Vout
PC409
2
2
Fsw=600Khz
PC411
PR405
1 2 1 2
1K_0402_1%
1000P_0201_25V7K
+3VLP @ +3VL
PJ404
2 1
2 1
PR414 @
EC_ON 1 2 +3/5VALW_EN JUMP_43X39
39,44,55 EC_ON
0_0402_5%
C C
+3VALW
2
PR406 @
100K_0402_5%
V20B+
1
@
PU402
PJ405
2 1 +5V_VIN 5 9 ALW_PWRGD PC415
2 1 4 IN1 PG 1 1 2 ALW_PWRGD 55
+5VBS
+5VALW
10U_0805_25V6K
10U_0805_25V6K
0.01U_0201_25V6-K
IN2 BS
1
3
PC413
PC414
IN3
JUMP_43X79 2 0.1U_0603_25V7-M PL402 PJ406 8A
EMC@ PC412
IN4 6 +5VLX 1 2 +5VALW_P 2 1

LX1 2 1
2
7 19 2.2UH_PCMB063T-2R2MS_8A_20%
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
8 GND1 LX2 20
GND2 LX3
1
18 JUMP_43X79
21 GND3 PR410
PC417
PC418
PC419
PC420
GND4 +5VALW_OUT +5VALW_P
1
OUT
14 1 2 @ @ Vout=5V± 3%
2
+3/5VALW_EN 12 0_0402_5% PR411
+5V_VIN EN1
11
EN2 FF
13 2.2_0805_5%
EMC_NS@
Vset=5.1V± 1.5%
LDO
15
+5VLP OCP=12A
2
10
NC1
16 17 +5VVCC 100mA OVP=(1.15~1.25)*Vout
1M_0402_5%
1U_0603_25V6M
0.1U_0201_25V6-K
4.7U_0603_6.3V6K
NC2 VCC
1
1
1
PC423 UVP=(0.55~0.65)*Vout
PC421
PR412
PC422
@ SY8288CRAC_QFN20_3X3 1000P_0402_50V7K
PC416
Vinafix.com 2
2
EMC_NS@ Fsw=600Khz
2
B PC424 B
PR413
+5VFB 1 2 1 2
1K_0402_1%
1000P_0201_25V7K
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_3VALW/5VALW

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
@
PR521 1 2
EC_ON 39,44,54
0_0402_5%
D
PMIC_VCC 1 2 D
PR522 @ 0_0402_5%
ALW_PWRGD 54
+5VALW
+5VLP PR502 @
1 2
10_0603_5%
@ PR520
VDDQ_EN
PMIC_EN
PR501 1 2 1 2
44 SYSON 0_0402_5% 10_0603_5%
@ VTT_EN PC500
PR503 1 2 1 2
5 CPU_DRAMPG_CNTL 0_0402_5% PR505
VDDQ_P 1 2
@ 2.2U_0603_6.3V6K
+1.8VALW_L_EN
PR507 1 2
VSYS_PMIC
0_0402_5% 10_0402_5%
2
@
+1.0VALW_EN
PR506 1 2 PC502 +3VALW
44,46 PCH_PWR_EN 0_0402_5% 0.1u_0201_10V6K
1
@
PR508 1 2 +2.5V_DDR_EN
44 EC_VPP_PWREN 0_0402_5%
28
27
41
9
100K_0402_5%
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
VSYS
VCC
PMIC_EN
GND
@
+2.5V_DDR_EN PMIC_SMB_DAT1
1
29 25 PR510 1 2
PC504
PC506
PC505
PC503
PC508
PR513
R_0402
EN_LDO1 SDA EC_SMB_DA3 44
0_0402_5% @
+1.8VALW_L_EN 1 26 PMIC_SMB_CLK1
PR511 1 2
EN_LDO2 SCL EC_SMB_CK3 44
1
PR526 0_0402_5%
1 2 +1.0VALW_EN 11 24 PMIC_ALERT# 2 1 @ 0_0402_5%
@ @ @ @ @ PR512 H_PROCHOT# 4,44
EN_V1P0A OT
2
+1.05VGS_B_EN 16 22 +1.0VALW_PG 1
0_0402_5% PAD @ PTC501
EN_V1P8A PG_V1P0A
OPT5075@ VDDQ_EN +1.05VGS_B_PG VDDQ_PGOOD 44
31 21 1 PAD @ PTC502
EN_VDDQ PG_V1P8A
VTT_EN 36 23 VDDQ_PGOOD
EN_VTT PG_VDDQ
+5VALW 12 LX_1P0 1
PL500
2 +1.0VALW_FB 2
PJ501 @
1
PJ500 @
22U_0603_6.3V6-M
2 1
+1.0VALW_B_VIN
7 LX_V1P0A1 13 0.47UH_CMMB062D-R47MS_15A_20% 2 1 +1.0VALW
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
2 1 8 VIN_V1P0A1 LX_V1P0A2 14 JUMP_43X79
VIN_V1P0A2 LX_V1P0A3
1
15
JUMP_43X39 PC510 EMC_NS@ LX_V1P0A4
PC509
PC511
PC512
PC513
PC514
PC515
PC516
10 +1.0VALW_FB
0.1u_0201_10V6K VO_V1P0A
2
+1.05VGS_B_EN PJ508 @ +1.05VGS_B_VIN @ @
2 1 2 1 17 PL502
OPT@ PJ509 @
22,23,58 EN_VGA
0_0402_5% +5VALW 2 1 19 LX_V1P8A1 18
LX_1P05
1 2
+1.05VGS_FB
2 1
VIN_V1P8A LX_V1P8A2 2 1 +1.05VGS
1
PR524 @ PC534 OPT@ 1UH_PH041H-1R0MS_3.8A_20%
0.1U_0402_25V6
JUMP_43X39 +1.05VGS_FB
20
5075 PJ512 tinplate
PC535 OPT@
22U_0603_6.3V6-M JUMP_43X79
22U_0603_6.3V6-M
22U_0603_6.3V6-M
VO_V1P8A
1
1 2 OPT@
PC537
22,23,58 DGPU_PWROK
2
5028 PJ509 tinplate
1
C PR525 PJ512 @ C
UG_VDDQ
0_0402_5% OPT5028@ 33 2 1
PC536
+1.2V_P UGATE_VDDQ 2 1 +1.8VGS
2
PC517 1 2 10U_0603_10V6K 38 PR1031 PC518
VIN_VTT BST_VDDQ
2
32 1 2 2 1 JUMP_43X79
PJ504 @ BS_VDDQ @
2 1 39 0_0603_5% 0.1U_0603_25V7-M
+0.6VS
LX_1P05
2 1 VTT LX_VDDQ
LX_1P0
34
LX_VDDQ
1
PC519
JUMP_43X39 40 35 LG_VDDQ
22U_0603_6.3V6-M VSNS_VTT LGATE_VDDQ
+1.2V_P
1
PR515 @ 37
1 2 30 VSNS_VDDQ PR1029 PR1030
33K_0402_1% CS_VDDQ 4.7_0603_5% 4.7_0603_5%
EMC_NS@ EMC_OPTNS@
PJ502 @ PJ503 @
+2.5V_DDR_VIN +2.5V_P
2
2 1 5 6 2 1
+3VALW 2 1 VIN_LDO1 LDO1 2 1 +2.5V_DDR
PC521
1
1 2
JUMP_43X39 1 2 JUMP_43X39 PC1109 PC1110
PC520 22U_0603_6.3V6-M 1200P_0402_50V7-K 1200P_0402_50V7-K
2
PJ511 @ EMC_NS@ EMC_OPTNS@
10U_0603_10V6K 3 +1.8VALW_L_P 2 1
4 LDO2 2 1 +1.8VALW
VIN_LDO2 2
22U_0603_6.3V6-M
FB_LDO2 JUMP_43X39
2
105K_0402_1%
1
PR516
PJ510 @
PC522
2 1 +1.8VALW_L_VIN PU500
+1.8VALW_L_FB
+3VALW 2 1
2
LV5028RPC_QFN40_5X5
1
JUMP_43X39
1
PC523 PJ506 @
VDDQ_P 2 1
10U_0603_10V6K 2 1 V20B+
0.1U_0201_25V6-K
5
10U_0805_25V6K
10U_0805_25V6K
JUMP_43X39
EMC@ PC524
1
1
PC525
PC526
2
PQ500
UG_VDDQ
2
PR517 4
75K_0402_1% AON7408L_DFN8-5
+1.2V
3
2
1
@
PJ507
0.47UH_CMMB062D-R47MS_15A_20%
LX_VDDQ 1 2 +1.2V_P 2 1
PL501 2 1
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
0.1U_0402_25V6
JUMP_43X79
2
AON7506_DFN @ @
1
B 4.7_0603_5% B
EMC_NS@ PC532
PR518
PC1113
PC527
PC528
PC529
PC530
PC531
PQ501 EMC_NS@
2
LG_VDDQ
1
4
1
PC533
Vinafix.com 1200P_0402_50V7-K
3
2
1
2
EMC_NS@
A A
Security Classification LC Future Center Secret Data T itle
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR PMIC-DDR4/1.0ALW/1.8ALW

D 1.0
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A Vinafix.com A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR

Custom 1.0
5 4 3 2 1
5 4 3 2 1
V20B+
D @ D
1A 2
PJ1401
1 +1.35V_VIN
2 1
PC1402 OPT@
PC1403 OPT@
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
EMC_NS@
JUMP_43X79
1
PC1401
2
2
PR1401 PC1404 +1.35VGS
PU1401 0_0603_5% 0.1U_0603_25V7-M OPT@
1 10 +1.35V_BST 1 2+1.35V_BST_R 1 2
VIN BST
0.47UH_PCMB053T-R47MS_13A_20% @
OPT@
PR1408 9 +1.35V_LX
OPT@ OPT@
1
PL1401
2 +1.35V_P 2
PJ1402
1
8A
1 2 +1.35V_S3 16 SW 2 1
PC1410 OPT@
OPT@
NB685GQ-Z_QFN16_3X3
EN1
1
PR1412 10K_0402_1% JUMP_43X79
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
1 2 +1.35V_S5 15 13 +1.35V_FB PR1402 PR1404
22,24 FBVDDQ_PWR_EN EN2 FB
1
10K_0402_1% 2.2_0805_5% 1M_0402_5% PC1405
OPT@ PC1406
OPT@ PC1407
@ PC1408
OPT@ PC1409
100K_0402_1%
+1.35V_P
EMC_OPTNS@ @ 220P_0402_50V7K
2 PR1403 1@ 12 6
PC1416 OPT@
@
0.1u_0201_10V6K
+3VALW PG VDDQ
2
+1.35V_SN
+1.35V_3V3
2
+3VALW 1 2 3
3V3 5
VTT +1.35V_COMP
1
PR1405 OPT@
1U_0402_6.3V6K
1
1
4.7_0402_5% 4
OPT@ PC1411
AGND
1
8 PC1412 PR1407
VTTS
1
2 1000P_0402_50V7K 41.2K_0402_1%
PGND
2
MPS_VTTREF
VTTREF
7 EMC_OPTNS@ PR1406 OPT@ Vout=1.35V± 5%
2
499_0402_1%
+1.35V_Mode 14
MODE OTW#
11 @ Vset=1.36V± 2%
1U_0402_6.3V6K
2
OPT@ OCP=13A
1
PC1415
1.35V_GND PR1410
OPT@
Vref=0.6V
0_0402_5%
1
@
OVP=(1.25~1.35)*Vref
1
C
1.35V_GND
PR1411
32.4K_0402_1%
UVP=(0.7~0.8)*Vref C
1.35V_GND OPT@ Fsw=700Khz(Rmode=0)
2
PJ1404
1 2 Fsw=500Khz(Rmode=150K)
JUMPER
@ 1.35V_GND
1.35V_GND
+5VALW
B
Vinafix.com
+1.8VGS
500mA
PC702
1U_0402_6.3V6K
1
2
OPT5075@
obligation
TP Pin connect to GND
6
5
9
PU701
VPP
VIN
TP
VO1
VO2
OPT5075@
3
4
+1.05VSP_VGA_5075
2
PJ702
2 1
1
+1.05VGS
2A
B
22U_0603_6.3V6-M
22U_0603_6.3V6-M
+1.05VGS_EN_5075 JUMP_43X39
1
2 1 8
22,23,58 EN_VGA VEN +1.05VGS_FB_5075
1
0_0402_5% 7 2 PR706 PC708 @ @
PC703
PC704
GND
PC701 PR705 POK ADJ

.1U_0402_10V6-K
220P_0201_25V7-K
2
22U_0603_6.3V6-M @ 22.6K_0402_1% @
2
@ G971MF11U _SO8
5075 PJ702 tinplate
PC706
OPT5075@
1
2
100K_0402_5%
OPT5075@
1
2
PR702
OPT5075@
@
PR707
2
2 1 71.5K_0402_1%
8,24,58 DGPU_PWROK 0_0402_5%
PR708 +3VALW
2
OPT5075@ OPT5075@
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-+1.05VGS/+1.35V_VRAM

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
NVVDD_PWM_VID
D 20 NVVDD_PWM_VID D
PSI_VGA +VGA_B+
20 PSI_VGA V20B+
VSSSENSE_VGA @
21 VSSSENSE_VGA
PJ801
VCCSENSE_VGA 2 1
21 VCCSENSE_VGA 2 1
DGPU_PWROK JUMP_43X118
8,24 DGPU_PWROK
10U_0805_25V6K
10U_0805_25V6K
0.1U_0201_25V6-K
1
1
PC801
PC802
PC803
2
2
PR835
@
2 1
8,22 PXS_PWREN
PD801 EMC_OPT@ OPT@ OPT@
0_0402_5% RB751V-40_SOD323-2 PQ801
2
OPT@ AON6982_DFN8-7
2 1 1 2 EN_VGA VGA_UGATE1 1
NVVDD_PWM_VID
20,22 3VGS_PWR_EN EN_VGA 22,23,57
PR841 OPT@
0_0402_5% 0.22UH_PCMB063T-R22MS_23A_20%
@
PR817
PL801 +VGA_CORE
2 1 7 VGA_PHASE1 1 2
1
PC812
VGA_LGATE1
1
0.1u_0201_10V6K 6
0_0402_5% OPT@ PR808 1 1
330U_D2_2V_Y
330U_D2_2V_Y
@ 2 2.2_0805_5%
2
EMC_OPTNS@ + +
PC808
PC807
7.15K_0402_1%
1
PR826
3
4
5
2
PR842
0_0402_5% OPT@ 2 2
1
@
1
PC809 OPT@ OPT@
2
PC816 OPT@ 1000P_0402_50V7K
2
1 2 EMC_OPTNS@
VGA_UGATE1
C PR807 PC806 C
VGA_BOOT1
2700P_0402_50V7-K 1 2 1 2
GPU_VID
PSI_VGA
10P_0201_25V8G
EN_VGA
1
PR804 0_0603_5% 0.22U_0603_16V7K
VREF_VGA 1 2 PC821 OPT@ OPT@
1
@
20K_0402_1% OPT@ PR803 2
20K_0402_1%
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
PR818 OPT@
PR801 OPT@ PR802
BOOT1
UGATE1
VID
EN
PSI
2
1
2 1 1 2 1 2
PC832
18K_0402_1% PC810 OPT@
PC829
PC830
PC831
PC833
PC834
2K_0402_1% OPT@ 6 20 VGA_PHASE1 4.7U_0603_6.3V6K
0_0402_5% REFADJ PHASE1
2
PC805 OPT@
@ 1 2 REFIN 7 19 VGA_LGATE1 1 2
PC804 REFIN LGATE1
2700P_0402_50V7-K 1 2 VREF_VGA 8 18 PVCC_VGA 2 1 OPT@ OPT@ OPT@ OPT@ OPT@ @
VREF PVCC +5VS
PR839 OPT@
+VGA_B+ 1 PR830 2 1 2 0.1U_0603_25V7K 9 17 VGA_LGATE2 PR815 0_0402_5% @
2.2_0603_5% 430K_0402_1% TON LGATE2
PC826 OPT@ OPT@ VSS_SEN 10 16 VGA_PHASE2
RGND PHASE2
UGATE2
2 1
PGOOD
BOOT2
VSNS
GND
0.1U_0201_25V6-K
SS
OPT@
PU801 OPT@
21
12
13
15
11
14
RT8812AGQW_WQFN20_3X3
+VGA_B+
VGA_BOOT2
VCC_SEN
VGA_UGATE2
PR831
PR823 OPT@ PC817 OPT@
Vinafix.com 2 1 1 2 1 2
0_0603_5% 0.22U_0603_16V7K
1000P_0201_25V7K
10U_0805_25V6K
100_0402_5%
PC824
10U_0805_25V6K
0.1U_0201_25V6-K
1
OPT@
PR836
1
PC813
PC814
PC815
DGPU_PWROK
B VSSSENSE_VGA VSS_SEN B
2
2 1
2
OPT@
PR822
2
PC842 10K_0402_1%
0_0402_5%
1
@ 1000P_0201_25V7K OPT@
PQ803
1
@ EMC_OPT@ OPT@ OPT@

PR837
2
2
AON6982_DFN8-7
VCCSENSE_VGA 2 1 VCC_SEN VGA_UGATE2 1 OPT@
+3VGS OPT@
0.22UH_PCMB063T-R22MS_23A_20%
+VGA_CORE
0_0402_5% PL802
@ 7 VGA_PHASE2 1 2 +VGA_CORE
PR832
VGA_LGATE2
1
1 2 6
PR824 1
330U_D2_2V_Y
2.2_0805_5%
100_0402_5% EMC_OPTNS@ +
PC818
OPT@
3
4
5
2
@
2
1
PC820
1000P_0402_50V7K
2
EMC_OPTNS@
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
1
1
PC843
PC844
PC845
PC846
2
2
OPT@ @ OPT@ OPT@
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-VGA_CORE

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
SVID Specification
Config
Vmin(V) 0
Vmax(V) 1.52
Vstep(mV) 5 +VCCST_CPU
+5VS +5VS
RFsw Core/GT SA V20B+
2
14K 600K 600K 2.2_0603_5% 2.2_0603_5%
1
PR922 PR926
+VCCST_CPU
1
PC918
1K_0402_1%
75_0402_1%
100_0402_1%
45.3_0402_1%
D D
PR923
PR933
PR943
PR932
1U_0402_6.3V6K
2
RVboot Core GT SA @
2.2U_0603_10V7K
2.2U_0603_10V7K
53 Psys
2
14K 0V 0V 1.05V
PC912
PC916
VR_VCC
VR_VRMP
VR_PVCC
1
1
PC920
1
@ 0.01U_0201_25V6-K
1K_0402_1%
1K_0402_1%
2
PR944 PR936
PR945
PR946
54.9_0402_1% @ @ 10_0402_1%
PU1402 VR_SVID_DAT_1 2 1
18
13
12
VR_SVID_DAT 12
PR940 PR937
2
1 2 50 36 VR_SVID_DAT_1 0_0402_5%
VRMP
VCC
PSYS/TSENSE_1b SDIO 38 VR_SVID_CLK_1 VR_SVID_ALRT#_1 2 1
PR916 SCLK 37 VR_SVID_ALRT#_1 VR_SVID_ALRT# 12
@ 0_0402_5% PR938
PVCC
2 1 VR_EN 41 ALERT# 49.9_0402_1%
44 EC_VR_ON EN VR_SVID_CLK_1 2 1
39 VR_SVID_CLK 12
0_0402_5%
42 DRON
44 CPU_VR_READY VR_RDY
35
44,53 VR_HOT# VRHOT# PR919 PC910
26 Vcore_BST 1 2 1 2
BST3 23.2K_0402_1%
2.7K_0402_1% 1500P_0402_50V6-K
VCORE PORTION 2.2_0603_5% 0.22U_0603_16V7K 1 PR947 2
1 PR903 2 2 1 PC902 Vcore_COMP 30 25 Vcore_PH 60
COMP_1a HG3 Vcore_HG 60
12K_0402_1%
1 2 2 PR901 1Vcore_ILIM 31
ILIM_1a
22K_0402_1%
PH905 +CPU_CORE
PC901 15P_0402_50V8J 1 2 24 Vcore_PH 1 PR948 2 1 2
1.07K_0402_1% 1000P_0402_50V7K PC909 SW3
1 PR913 2 Vcore_VSP 28 100K_0402_1%_TSM0B104F4251RZ
12 VCORE_VCC_SEN 1 2 1 2 VSP_1a 23
LG3/ICCMAX_1b Vcore_LG 60
2
PC913 PR910 PC904 1000P_0402_50V7K 348_0402_1% 11K_0402_1% 1 2

1.07K_0402_1% 1 PR911 2 Vcore_VSN 29 1 PR941 2 PC942 3300P_0402_50V7-K
1000P_0402_50V7K VSN_1a
470P_0402_50V7K
1
1 2 2 1 Vcore_IOUT 34 33 Vcore_CSP 1 2
12 VCORE_VSS_SEN IOUT_1a CSP_1a
C 330P_0402_50V7K PC906 PC911 PC922 2700P_0402_50V7-K C
2 1 27 32
PR917 TSENSE_1a CSN_1a
40.2K_0402_1%
Vcore_TSENSE
PR949
VCCGT PORTION GT_CSSUM
1
7 1 2
CSSUM_2ph GT_PH 60
PR942
MOSFET
6 GT_CSCOMP PR950 1 2 75K_0402_1% 1 2 PR904 93.1K_0402_1%

0_0402_5% CSCOMP_2ph
470P_0402_50V7K PH901 110K_0402_1%
@ 2 1 1 2
2
PC930 1 2 PC925
2 1 GT_IOUT 1 PR951 270P_0402_50V7K
220K_0402_5%_TSM0B224J4702RE
100K_0402_1%_TSM0B104F4251RZ
IOUT_2ph GT_ILIM
1
25.5K_0402_1% 100K_0402_1% 5 1 2 2 1
8.25K_0402_1%
0.1U_0402_25V6
ILIM_2ph +VCC_GT
1
Place close to
PR959 PR902 12.7K_0402_1% PC914 330P_0402_50V7K 10_0402_1%

PH902
PR931
PC924
2 1 8 GT_CSREF 1 PR924 2
CSREF_2ph
0.22U_0603_16V7K
2
GT_DIFFOUT 2 14 GT_BST1 1 2
0.01U_0402_25V7K
DIFFOUT_2ph/ICCMAX_2ph BST1
2
470P_0402_50V7K PR934 2200P_0402_50V7K PR925 2.2_0603_5%
PC915
1 PR914 2 1 2 1 2 1 2 GT_COMP 4
NCP81216MNTXG_QFN52_6X6
PC917
COMP_2ph
1
49.9_0402_1% PC907 8.45K_0402_1% PC908 15
1 2 1 2 HG1 GT_HG 60
1
PR918 PC932 10P_0402_50V8J 0.047U_0402_16V7K
2
1K_0402_1% GT_FB 3 16 GT_PH PC926
FB_2ph SW1
2
17
LG1/ROSC GT_LG 60
PR954
2 1
51 14K_0402_1%
12 VCCGT_VCC_SEN VSP_2ph 10 GT_CSP1 1 2 GT_PH
CSP1_2ph
2
Vinafix.com 910_0402_1% PR953

PC931 1 PR964 2 GT_VSN 52 1.8K_0402_1%
1000P_0402_50V7K VSN_2ph 9 GT_CSP2 2 1
CSP2_2ph +5VS
1
1 2 PR952
12 VCCGT_VSS_SEN
PC933 2200P_0402_50V7K 2K_0402_1%
B B
GT_TSENSE 11 40 1 2
TSENSE_2ph PWM/ICCMAX_1a 102K_0402_1%
PR927
1.5K_0402_1% 0.015U_0402_25V7-K
0.22U_0603_16V7K
1 PR965 2 2 1 PC936 SA_COMP 47 22 SA_BST 1 2
COMP_1b BST2
1
PR989 2.2_0603_5% 13K_0402_1%
PC989
1 2 PR912 1 PR956 2
PR960 VCCSA PORTION
2 SA_ILIM 46 SA_PH 60
2
0_0402_5% PC935 15P_0402_50V8J 1 21
ILIM_1b HG2 SA_HG 60
15.8K_0402_1%
@ 1 2 22K_0402_1%
PH904 +VCCSA
2
1
1.54K_0402_1% 1000P_0402_50V7K PC940 20 SA_PH 1 PR957 2 1 2
PR966 SW2 14K_0402_1%
100K_0402_1%_TSM0B104F4251RZ
SA_VSP 49
1
1 2 19 1 PR955 2 100K_0402_1%_TSM0B104F4251RZ
8.25K_0402_1%
.1U_0402_10V6-K
13 VCCSA_VCC_SEN VSP_1b LG2/ADDR_VBOOT

1
PH903
PR963
PC934
1 2 1 2 348_0402_1% PC941 1 2 3300P_0402_50V7K

SA_VSN 48 SA_LG 60
PC937 1.54K_0402_1% PC938 1000P_0402_50V7K 1 PR970 2
VSN_1b
2
SA_CSP
IOUT_1b
1000P_0402_50V7K PR907 44 PC927 1 2 3300P_0402_50V7K

CSP_1b
2
1 2
EPAD
13 VCCSA_VSS_SEN 45
PC939 220P_0402_50V7K
CSN_1b
43
53
SA_Iout
1
1
PR958
PC929 59K_0402_1%
470P_0402_50V7K
2
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_CPU_CORE1

C
DG421 1.0

5 4 3 2 1
5 4 3 2 1
PJ1001 +CPU_CORE
VCCIA_VIN 2 1
2 1 1 V20B+
10U_0805_25V6K
10U_0805_25V6K
0.1U_0201_25V6-K
1
1
JUMP_43X79 + PC1004
PC1002
PC1003
5
@ 68U_25V_M
PC1001
PQ1001 EMC@
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
2
2
2
AON6380_DFN8-5
1
Vboot=0V Loadline=2.4mΩ
PC1005
PC1006
PC1007
PC1008
PC1009
PC1013
PC1010
PC1011
PC1014
PC1012
59 Vcore_HG
4 Ripple=+30mV/-10mV(0A-0.5A)
2
+CPU_CORE Ripple=± 10mV(0.5A-TDC)
0.15UH_PCMB063T-R15MS_30A_20% @ @ Ripple=± 15mV(TDC-Iccmax)
3
2
1
1 2
59 Vcore_PH
D
PL1001 TDC=21A Iccmax=32A D
1
PQ1002 PR1002 OCP=37A
220U_D2_2VM_R6M
1
2.2_0805_5%
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
AON6324_DFN8-5
EMC_NS@ +
OVP=1.72V(during SS)OVP=VID+300mV
PC1015
1
2
4 UVP=VID-300mV
PC1022
PC1016
PC1023
PC1017
PC1025
PC1018
PC1024
PC1019
PC1020
PC1021
59 Vcore_LG +CPU_CORE 2 3
2
1
PC1026
1000P_0402_50V7K
3
2
1
2
EMC_NS@ Vcore_PH
@ @
@
PJ1002
VCCSA_VIN 2 1
2 1 V20B+
JUMP_43X79
10U_0805_25V6K
10U_0805_25V6K
0.1U_0201_25V6-K
1
1
PC1028
PC1029
SA_PH
PC1027
59 EMC@
2
PQ1003
2
3
4
9
+VCCSA
0.47UH_PCMB053T-R47MS_13A_20%
1 PL1002
59 SA_HG 10 1 2
47U_0603_4V6-M
47U_0603_4V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
1
1
8
PC1112
PC1111
59 SA_LG
1
PR1006
AON7934L_DFN10 2.2_0805_5%
PC1036
PC1037
PC1038
PC1039
PC1040
PC1041
PC1042
7
6
5
2
EMC_NS@
2
C C
2
@ @
1
@
PC1046
@ 1000P_0402_50V7K
2
PJ1003 EMC_NS@
VCCGT_VIN 2 1
2 1 V20B+
5
JUMP_43X79
10U_0805_25V6K
10U_0805_25V6K
PQ1005
0.1U_0201_25V6-K
1
+VCCSA
PC1033
PC1031
AON6380_DFN8-5
PC1032
EMC@
2
4
59 GT_HG SA_PH
+VCC_GT Vboot=1.05V Loadline=10.3mΩ

3
2
1
0.15UH_PCMB063T-R15MS_30A_20%
1 2
Ripple=+30mV/-10mV(0A-0.5A)
59 GT_PH
PL1003 Ripple=± 10mV(0.5A-TDC)
5
PQ1006 Ripple=± 15mV(TDC-Iccmax)
220U_D2_2VM_R6M
1 330U_D2_2V_Y 1
AON6324_DFN8-5 PR1008
2.2_0805_5% + +
TDC=5A Iccmax=5.1A
PC1045
PC1066
EMC_NS@ +VCC_GT
59 GT_LG
4 OCP=8A
2
2 2 3
1
Vinafix.com PC1047
+VCC_GT UVP=VID-300mV
3
2
1
1000P_0402_50V7K GT_PH
2
EMC_NS@
B B
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
1
1
@ @
PC1052
PC1053
PC1054
PC1055
PC1056
PC1057
PC1058
PC1059
PC1060
PC1061
PC1062
PC1063
PC1064
2
2
@ @
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
1
1
@ @
Vboot=0V Loadline=3.1mΩ
PC1067
PC1068
PC1069
PC1070
PC1071
PC1072
PC1073
PC1074
PC1075
PC1076
PC1077
2
2
Ripple=+30mV/-10mV(0A-0.5A)
Ripple=± 10mV(0.5A-TDC)
@ @
Ripple=± 15mV(TDC-Iccmax)
TDC=18A Iccmax=31A
OCP=76A
UVP=VID-300mV
A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_CPU_CORE2

C
DG421 1.0

5 4 3 2 1

Ideapad 320 15IKB DG421 DG521 DG721 NM B241 NM B242 Rev 1 0 DIS

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Ideapad 320 15IKB DG421 DG521 DG721 NM B241 NM B242 Rev 1 0 DIS

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Vinafix.

Security Classification LC Future Center Secret Data Title

Date: Sunday, January 22, 2017 Sheet 5 of 60

DDRB_DQ0 AF65 AN45

RC23 1 @ 2 0_0402_5% CPU_DRAMRST#_R

Security Classification LC Future Center Secret Data

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)

+3VALW_PCH +3VS +3VS

* 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.

RPC25 2. This signal is in the primary wel

+3V_SPI PCH_SML1_CLK QC10A 6 1 @ SML1_ALERT# RC1569 1 @ 2 150K_0402_5% +3VS

UC3 2N7002KDWH_SOT363-6 RC1655 1 2 150K_0402_5%

SPI_SI 2 (Refer to WW52_MOW)

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (MISC,JTAG,SPI,LPC,SMB)

Date: Sunday, January 22, 2017 Sheet 7 of 60

RC1559 2 DIS@ 1 10K_0402_5% PXS_PWREN_R 1K_0402_5% 2 DIS@ 1 RC7

RC47 1 @ 2 1K_0402_5% HDA_SDOUT SKYLAKE-U_BGA1356 1 OF 20

AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11

GSPI1_MOSIBoot BIOS Internal PD Rising edge

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (LPSS,ISH,AUDIO,SDIO)

Date: Sunday, January 22, 2017 Sheet 8 of 60

@DIS For NV and AMD GPU SKU

20 PCIE_CTX_C_GRX_P[0..3] SSIC / USB3

2016/05/03: Implement as Power Button

+3VS GPP_E4 RC1617 2 @ 1 10K_0402_5%

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCIE,SATA,USB3,USB2)

2 7 WLAN_CLKREQ# B31 CSI2_DN6 AP2

@DIS For NV and AMD GPU SKU UC1J SKL_ULT ?

CLK_PCIE_GPU# D42 DIFFCLK_BIASREF RC1555 1 2 60.4_0402_1%

need to use 38.4MHz (30ohm) for Cannonlake-u

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CSI2,EMMC,CLOCK)

SYSTEM POWER MANAGEMENT

RC88 1 @ 2 0_0402_5% AC_PRESENT_R

+3VALW_PCH +3VALW +VCCST_CPU +VCCSTG

Add to fix Reset&PWRGD test fail issue

PCH_DPWROK_R RC81 1 @ 2 0_0402_5% DPWROK_EC 44

100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R

10/ 25 SIT Add to fix PLT_RST# glitch issue wei Title

+CPU_CORE ? +CPU_CORE +CPU_CORE +VCC_GT +VCC_GT

Security Classification LC Future Center Secret Data Title

Date: Sunday, January 22, 2017 Sheet 12 of 60

Security Classification LC Future Center Secret Data Title

Date: Sunday, January 22, 2017 Sheet 13 of 60

+1.0VALW RC1503 1 @ 2 0_0603_5% +VCCAMPHY

+1.0VALW RC1504 1 @ 2 0_0402_5% +VCCAPLL_1P0 +3VALW_PCH +VCCPGPPG

+3VALW_PCH RC1586 1 @ 2 0_0402_5%

RC1620 1 @ 2 0_0402_5% VCCMPHYON_1P0_L1

N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3

2 2 +3VALW VCCDSW_3P3_AD17 VCCCLK4 +VCCCLK4

VCCDSW_3P3_AJ17 VCCCLK5 +VCCCLK5

CD@ 1 +1.0VALW AK20

33mA N18 RC1588 1 @ 2 0_0603_5%

Security Classification LC Future Center Secret Data

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCH PWR)

Date: Sunday, January 22, 2017 Sheet 14 of 60

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (VSS)

CPU_CFG0 E68 BB68 1 TC173 @ PAD

E70 AK12 1 TC176 @ PAD