Development of An On-Board Computer For A Nanosatellite: Intelligent Robotics"

https://lib.uliege.be https://matheo.uliege.
be
Development of an on-board computer for a nanosatellite
Auteur : Horbach, Amadis

Promoteur(s) : Redouté, Jean-Michel
Faculté : Faculté des Sciences appliquées
Diplôme : Master : ingénieur civil électricien, à finalité spécialisée en "signal processing and
intelligent robotics"
Année académique : 2020-2021
URI/URL : http://hdl.handle.net/2268.2/11659
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Master’s thesis carried out to obtain the degree of Master
of Science in Electrical Engineering by Horbach Amadis
Development of an on-board computer for

a nanosatellite
University of Liège - School of Engineering and Computer Science
Supervisor: Jean-Michel Redouté
Academic year 2020-2021

Acknowledgements
I would like to start by thanking Hervé Pierre. Firstly, for proposing this thesis to
me. Then, for his follow-up and guidelines during the whole year. And finally, for his
proofreading of this thesis. His help was really valuable to me. I would also like to thank
Professor Jean-Michel Redouté for giving me and other students the chance to work on
such an interesting project.
I would like to express my thanks to the Microsys team for the good atmosphere that
always prevailed in the working room and their kind advice in case of need. I would
especially like to thank Morgan with whom I was happy to share on the current OUFTI
project.
I also would like to thank my friends for their support during this particularly strange
and hard period we are all living. You have allowed me to get a bit of fresh air and to go
through this work.
Finally, I want to thank my family for their constant support during my studies and
particularly during this work. I would especially like to thank my mother, my sister and
my uncle for their proofreading of this thesis.
2
Abstract
The purpose of this master thesis is to develop the On-Board Computer (OBC) of
the University educational CubeSat OUFTI. The OBC is the central part of a CubeSat
allowing the control of all the other subsystems. Its development is therefore crucial and
must be carried out effectively and efficiently. As this is not the first CubeSat developed
by the university, the first thing to do is to analyze the previous ones in order to extract
their strengths and more importantly their weaknesses. Thus, this work starts with an
introduction of the concept of CubeSat followed by a brief analysis of the main elements
that created difficulties in the previous CubeSat of the University.
Once the context of this thesis is introduced, the development of the electric circuit
can be detailed. The choice of the components is logically based on the space conditions
introduced in the first chapter. The most important part of the circuit is the micro-
controller. Indeed, this is the component that will manage and monitor all the other
components, whether they are on the OBC board or on one of the other boards in the
CubeSat. It is thus essential that it works efficiently and without any failure. Then,
the other components of the OBC can be selected and assembled in schematics. All the
components are finally placed in a PCB to form the OBC’s PCB.
When the hardware of the OBC is finished and its PCB is created, it is important to
test that the OBC performs all its required tasks. To this end, a software has to be devel-
oped. This software implements a real time operating system architecture. The creation
of the code implemented to test the correct functioning of the OBC is then detailed.
The final part of this thesis explores the various tests that have been performed along
with the most important results obtained. These tests went from simple voltage measure-
ments to communication with external devices. The tests allow a first validation of the
OBC of the university CubeSat.
3
List of acronyms
ACK Acknowledge
ADC Analog-to-Digital Converter
ADCS Attitude Determination and Control Subsystem
AFEC Analog Front-End Controller
ARM Advanced RISC Machine
COTS Commercial Off The Shelf
CPHA Clock Phase
CPOL Clock Polarity
CS Chip Select
DDR Double Data Rate
DOUT Data Out
DRAM Dynamic Random Access Memory
DTCM Data Tightly Coupled Memory
ECC Error Correction Code
EEPROM Electrically Erasable Programmable Read-Only Memory
EPROM Erasable Programmable Read-Only Memory
EPS Electrical Power System
FRAM Ferroelectrical Random Access Memory
GCR Galactic Cosmic Rays
HSMCI High Speed Multimedia Card Interface
I2C Inter-Integrated Circuit
ICD In-Circuit Debugger/Programmer
IDE Integrated Development Environment
IO Input/Output
ITCM Instruction Tightly Coupled Memory
LEO Low Earth Orbit
LET Linear Energy Transfer
MCAN Master Controller Area Networks
MCU Microcontroller Unit
MISO Master In Slave Out
MOSI Master Out Slave In
MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
MSB Most Significant Bit
NASA National Aeronautics and Space Administration
NCPHA Not Clock Phase
4
NVIC Nested Vector Interrupt Control
OBC On-Board Computer
OS Operating System
PCB Printed Circuit Board
PMC Power Managment Controller
PROM Programmable Read-Only Memory
PZT Lead zirconate titanate
RAM Random Access Memory
RMAP Remote Memory Access Protocol
ROM Read-Only Memory
RSD Redundant Signed Digit
RSWDT Reinforced Safety Watchdog Timer
RTC Real Time Clock
RTOS Real Time Operating System
RTT Real-Time Timer
SAA South Atlantic Anomaly
SCL Serial Clock Line
SDA Serial Data
SDR Single Data Rate
SDRAM Synchronous Dynamic Random Access Memory
SDRAMC Synchronous Dynamic Random Access Memory Controller
SEE Single-Event Effects
SEL Single-Event Latchup
SEU Single-Event Upset
SLC Single-Level Cell
SPCK Serial Peripheral Interface Clock
SPE Solar Particle Events
SPI Serial Peripheral Interface
SRAM Static Random Access Memory
TCM Tightly Coupled Memory
TID Total Ionizing Dose
TWI Two Wire Interface
UART Universal Asynchronous Receiver/Transmitter
USART Universal Synchronous/Asynchronous Reveiver/Transmitter
VREFP Positive Voltage Reference
WDT Watch Dog Timer
WREN Write Enable
5
Contents
Acknowledgements 2
Abstract 3
List of acronyms 4
Contents 6
1 Introduction 8
1.1 Project’s presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 CubeSat history and architecture . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.1 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.3 On-Board Computer . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Space conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.1 Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.2 Radiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 Hardware design 15
2.1 Choice of the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1 SAMV71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Selection of the other components . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.1 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.2 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.3 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.4 Power monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3 Final PCB presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3 Software implementation 38
3.1 Software architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2 MPLAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.1 Harmony v3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3 Code implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3.1 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.3 External I2C bus task . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.4 External ADC (SPI) task . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.5 FRAM (SPI) task . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6
CONTENTS Master thesis
3.3.6 User task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4 Hardware and Software testing 52

4.1 Development board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2 PCB compatible with the development board . . . . . . . . . . . . . . . . 54
5 Conclusion 58
Appendices 60
A Final PCB Schematics 61
B Test PCB Schematics 67
C Codes Git link 71
References 73
7
Chapter 1
Introduction
1.1 Project’s presentation

The University of Liège (ULiège) has a well known history with nanosatellites. It
all started in September 2007 when ULiège and the Higher Education Institution of the
Province of Liège (HEPL) decided to launch a project aimed at developing a nanosatel-
lite. After several years of development, the nanosatellite named OUFTI-1 was launched
and successfully reached its orbit on 25th April 2016. Unfortunately, the nanosatellite
encountered a failure quickly after. Even if there is no proof of what caused the failure,
radiation is thought to be responsible. In 2017, ULiège and HEPL decided to develop a
second nanosatellite named OUFTI-2. However, mainly due to the high power consump-
tion of its microcontroller (MCU), this one was never launched.
In 2020, ULiège and HEPL decided to start a new OUFTI project. This one is meant to
be composed of four main sections: (i) an Electrical Power System (EPS), (ii) a telecom-
munication system, (iii) a scientific payload, and (iv) an On-Board Computer (OBC)
controlling the entire nanosatellite. The purpose of this master thesis is to develop the
OBC of this nanosatellite. The work is divided into two main tasks.
The first one concerns the hardware of the OBC. It consists in selecting the compo-
nents and assembling them to produce the OBC schematics. Once the schematics are
done, the conception of a Printed Circuit Board (PCB) is also needed. For this task,
particular attention must be paid to the choice of components. Indeed, previous OUFTI
experiments have shown that it is important to choose components that are (i) resistant
to the harsh conditions encountered in space, (ii) efficient in terms of power consumption.
The second task consists in a series of tests to check the proper functioning of some
components. Some tests only require the reading of some voltages through external com-
ponents such as voltmeters but most of the tests require a software. For that reason, a
complete software has also to be realized. It is important for this software to be easily
readable and well documented as the development of the nanosatellite will continue in
the coming years.
8
1.2. CUBESAT HISTORY AND ARCHITECTURE Master thesis
1.2 CubeSat history and architecture

Traditional satellites are huge, heavy, and expensive. Thanks to the invention of mi-
crocontrollers, which integrate multiple components, and the reduction of Printed Circuit
Board size, engineers were able to develop a new class of satellites, with lower size and
weight, and therefore, with lower power consumption: the nanosatellites.
1.2.1 History
CubeSats are nanosatellites with specific characteristics. They are the result of a col-
laborative work carried out by two university professors, Jordi Puig-Suari, a professor at
California Polytechnic State University (Cal Poly), and Bob Twiggs, a professor at Stan-
ford University’s Space Systems Development Laboratory (SSDL) [1]. Their aim was to
make it possible for engineering students within their universities to work on space pro-
grams and so improve their training. To reach their objective, it was necessary to reduce
considerably the size and cost of satellites. In 1999, they succeeded with the conception
of the first CubeSat. And in 2003, the first CubeSat was launched.
CubeSats were first used within universities as educational tools. But now they are
more and more popular in the satellite industry. As they are much smaller and consider-
ably less expensive than conventional satellites, they give affordable access to space and
offer a perfect solution for several industrial applications. Therefore, CubeSats are now
developed by Government organizations as well as private firms worldwide. What makes
CubeSats so popular is their standard size and modularity, which not only reduces pro-
duction costs but also makes the launch process very efficient, as will be detailed below. In
addition to this, as the production time is also greatly reduced, if something goes wrong,
a whole mission does not have to be stopped for years, as is the case with traditional
satellites.
1.2.2 Architecture
In 1999, the CubeSat standard was defined. The basic unit, called 1U, is a 10 cm cube
with a maximum mass of 1,33 kg [1]. Thanks to its modularity, different units, based on
the standard CubeSat unit (1U), can be combined and so form a larger structure (2U,
3U,...).
Standard dimensions make mass production possible. The use of commercial off-
the-shelf (COTS) components for the structure and electronics of CubeSats considerably
reduces both costs and production time. The launch of Cubesats is also greatly facilitated
by their reduced volume, light weight, and standard dimensions. As a result, they can be
installed in a specific container and launched from commercial space flights, which enables
more frequent launches and at reduced costs since they can be shared.
9
As it can be seen in Figure 1.2.1, the main components of a CubeSat are the following:
• Payload: it is the reason why the satellite is designed.
• Attitude Determination and Control System (ADCS): it controls the orien-

tation of the satellite.
• On-Board Computer (OBC): it is the central part of the CubeSat allowing the
control of all the other subsystems.
• Communication system: it handles the external communications of the CubeSat.
• Electrical Power System (EPS): it is responsible for the adequate distribution

of power to all the subsystems.
• Solar panels: they generate power and reload the EPS batteries.
• Antenna: it is used to send and receive CubeSat’s communications.
Figure 1.2.1: Representation of the different parts of a CubeSat.
SOURCE : http://spacebillboard.com/mission/
10
1.2.3 On-Board Computer

This thesis aims at developing the on-board computer of a CubeSat. The character-
istics and role of the OBC will therefore be detailed in this section. During the mission,
data will be collected through sensors and be processed. Communication with the ground
station will also happen. Although they usually involve other sub-systems, all these op-
erations are linked at some point to the OBC. An example is the voltage of the batteries
which is frequently monitored by the EPS board and whose values are then stored in the
OBC memory. The OBC can thus be represented at the center of a CubeSat diagram.
This can be seen in Figure 1.2.2 with the subsystems introduced in the previous section.
Figure 1.2.2: Block diagram representing the interconnection between the main CubeSat
subsystems.
Based on what has been explained above the main components required by an OBC
will now be explored. First, a microcontroller is needed. The MCU can be viewed as the
brain of the OBC and more generally of the CubeSat. It will handle the different commu-
nications happening inside the CubeSat and will process the data. The communications
and data processing will be managed through a software that needs to be implemented.
Then, connectors are needed to allow communication between the different subsystems
and the OBC. It is also important to ensure that the power signals coming from the EPS
board are well regulated in order to avoid a system failure. A monitoring of the power
consumed by the OBC is also required as power is limited inside the CubeSat. Finally,
the OBC will need to have memories in order to store data and the software. Differ-
ent memory types will be required. Indeed, some information needs to be stored for a
long time while other information will need to be processed quickly using volatile memory.
The components selected for the realization of the OBC of this project will be described
in the next Chapter. Then, Chapter 3 will detail the software implemented in order to
ensure that the OBC performs its operating tasks. Finally, Chapter 4 will present the
tests that have been performed to ensure the good working of the OBC. But before that,
a presentation of the space conditions that the CubeSat and thus the OBC will encounter
is required in order to justify some of the choices made later.
11
1.3. SPACE CONDITIONS Master thesis
1.3 Space conditions

CubeSats operate in Low Earth Orbit (LEO), which means at an altitude comprised
between 160 km and 2.000 km. It is therefore important to take into account the partic-
ular space environment in LEO while choosing the components used in the OBC. Indeed,
the temperature extremes and radiation that electronic systems will be subjected to may
cause serious disturbances and failures [2].
In Low Earth Orbit, CubeSats will be exposed to temperature extremes, ranging from
-55° to +125°C in a short period of time, putting a strain on all materials. This could
affect the operational functionality of electronic components and limit their lifetime. It is
thus essential to use components specially designed to withstand such a range of temper-
ature extremes. Moreover, satellites in LEO are particularly affected by space radiation
that can pass through a satellite and consequently damage electronic devices. Shielding
can help to protect the components from radiation but it adds weight. Another solution
is the use of radiation hardened or radiation tolerant components.
Space conditions in LEO will now be explained in more detail.
1.3.1 Temperature
Satellites orbiting the Earth move in and out of the sunlight. Therefore, they are
submitted to extreme swings of temperature depending on whether they are facing the
Sun or in the shadow. When they are in view of the Sun, as they are not protected
by the Earth’s atmosphere, they are subjected to solar radiation, and thus to very high
temperatures. Thermal effects are also enhanced by the lack of convection in space. On
the reverse, when satellites pass into the shadow of the Earth, the absence of atmosphere
leads to rapid cooling as a result of the lack of energy being absorbed and of the thermal
energy released by the satellites. It is therefore important to use electronic equipment
that can withstand these temperature cycles.
1.3.2 Radiation
There are three main sources of ionizing radiation that can affect CubeSats and their
electronic components. They are depicted in Figure 1.3.1.
Galactic Cosmic Rays (GCR) are high energy protons and heavy ions which are con-
stantly bombarding the Earth. These particles originate outside the solar system. They
are made up of atomic nuclei that have been stripped of their surrounding electrons and
that are moving almost at the speed of light. These high-energy particles can alter com-
ponents in electronic integrated circuits.
Energetic solar particles emanate from solar flares and coronal mass ejections. These
events occur from time to time on the surface of the Sun. They are unpredictable. Dur-
ing these giant explosions, a large number of particles (protons, electrons, X-rays, and
gamma rays) are released into space and can cause light to severe damage to electrical
12
1.3. SPACE CONDITIONS Master thesis
components. These are known as Solar Particle Events (SPE).
Trapped particles are highly charged particles, emanating mainly from the Solar Wind.
They are trapped by the Earth’s magnetic field in the Van Allen belts. Over the South
Atlantic Ocean, there is a magnetic field anomaly. This region of weaker magnetism
is called the South Atlantic Anomaly (SAA). Because the axis of the magnetic field is
slightly offset from the one of the Earth, the inner belt is closer to the Earth’s surface in
this area. This weak point allows charged particles, mainly protons and electrons, to fall
closer to the ground and reach satellites operating in LEO. As a result, when they pass
through this zone, as CubeSats often do, they are exposed to particularly intense radiation.
Figure 1.3.1: Main sources of space radiation in LEO.
SOURCE : https://www.nasa.gov/audience/foreducators/stem-on-station/
learning_launchers_radiation
Electronic devices are impacted by space radiation in two different ways. Indeed, radi-
ation effects can be either cumulative or due to a single event. That will now be described.
Total Ionizing Dose (TID): Electronic devices are subject to the long-term effects of
radiation and are being deteriorated by the charges they have accumulated.
Single-Event Effects (SEE): A single charged particle hits and ionizes the material,
causing a current pulse that can damage the component. The effects can be reversible
(soft errors, which can be mitigated by a reset or an erase operation, for instance) or
non-reversible (hard error).
There are different types of SEEs, depending on the location of the hit and its intensity.
13
1.4. POWER MANAGEMENT Master thesis
The two more common are:
• Single-Event Upset (SEU): In this case an ionizing particle from the radiation
reaches a sensitive area of the circuit such as the memory and creates a change
of state (bitflips).
• Single-Event Latchup (SEL): An ionizing particle from the radiation creates an

overcurrent within the device which can cause irreparable damage if not directly
addressed.
1.4 Power management

Satellites get all their power from solar panels. When exposed to the Sun, the solar
arrays transfer energy to the EPS. Part of this energy is used for operations and part
for recharging the batteries. The batteries are required to operate during eclipses, when
the CubeSat is in the shadow of the Earth, or to deal with power peaks that are beyond
what the solar cells can provide. Due to their small size, CubeSats have a reduced surface
area for solar arrays and strict constraints on the subsystem components, including the
EPS, that can be installed. As CubeSats are increasingly used for more sophisticated
applications, the power needs are constantly growing. Even with the advent of deployable
solar panels and more efficient batteries, moderate use and correct management of power
are thus crucial. A negative power budget could lead to the failure of a CubeSat mission.
In short, energy is precious on a Cubesat. Particular attention must therefore be paid to
the choice of low-power components.
14
Chapter 2
Hardware design
The development of the on-board computer starts with the creation of its PCB. To
this end, the components constituting the OBC have to be selected and the schematics
have to be realized. This chapter will present this hardware part of the OBC’s conception.
It will start with an explanation about the thinking that was made in order to choose the
microcontroller. Then, the chosen MCU will be investigated and some of its characteristics
will be detailed. After having presented the MCU, the other components constituting the
OBC will be explored. This exploration will start with a review of all the different memory
components that have been placed on the OBC. Then, the connectors and oscillators that
have been used will be detailed. The last components that will be presented in this
chapter are those used to monitor the power of the OBC. Finally, the chapter will end
with a presentation of the final OBC’s PCB.
2.1 Choice of the microcontroller

The microcontroller is the central part of the OBC. It is therefore important to choose
it with particular attention. Indeed, a malfunction of the MCU will lead to the failure of
the OBC, and thus, of the whole nanosatellite. The previous chapter introduced the main
difficulties encountered in space. Research has been conducted in order to find a MCU
consuming relatively low power and being able to survive in the harsh space environment.
Two main challenges were encountered during this procedure. First, radiation-resistant
MCUs generally consume much more power than more basic MCUs. Second, the price of
MCUs capable of surviving in space is much higher than that of MCUs designed for use on
Earth. The second point is particularly problematic for the development of a university
CubeSat. Indeed, the budget is not unlimited and some tests must be done this year
while the OBC will still evolve before being launched one day. It is thus impossible to
spend hundreds of euros in order to get a MCU to test the OBC’s PCB this year and to
have to buy a new one next year for the updated PCB.
For the reasons mentioned above, the choice has been made to develop the OBC
around the SAMV71 MCUs. This choice is motivated by the fact that three different
versions of this MCU exist [3]. They are shown in Figure 2.1.1. Microchip has developed
the SAMV71 to be Arm® -based MCUs able to operate properly in space. The standard
version, the ATSAMV71Q21, is a COTS device and costs only a few dozen euros. The
second one, the SAMV71Q21RT, is the radiation-tolerant version of the ATSAMV71Q21.
The third one, the SAMRH71, is the radiation-hardened MCU based on the standard
15
2.1. CHOICE OF THE MICROCONTROLLER Master thesis
one. It is also worth noting that a development board made around the standard MCU
version is available.
(a) ATSAMV71Q21, the standard version (b) ATSAMV71Q21RT, the radiation-

of the SAMV71 tolerant version of the SAMV71
(c) SAMRH71, the radiation-hardened version of the SAMV71
Figure 2.1.1: The three versions of the Arm® -based SAMV71 developed by Microchip.
SOURCES:
(a) https://www.microchip.com/wwwproducts/en/ATSAMV71Q21
(b) https://www.microchip.com/wwwproducts/en/SAMV71Q21RT
(c) https://www.microchip.com/wwwproducts/en/SAMRH71
The development board has been used to implement the software and to realize the
tests performed during this thesis. For the future tests, the standard version will be
placed in the designed OBC’s PCB. Finally, the radiation-tolerant version will replace
the standard version before the launch of the nanosatellite. The transition from the
standard version to the radiation-tolerant version is straightforward since the masks of
the latter are the same as those of the former. Some little modifications should be made
16
to adapt the software to the radiation-hardened version. However, they are negligible
compared to the gain obtained from developing the software on the standard version.
Moreover, the radiation-tolerant MCU will be the one used when the nanosatellite will be
launched. Firstly, because it is well adapted to operate in LEO, which is precisely where
the CubeSats operate. Secondly, because it is way cheaper than the radiation-hardened
version. The characteristics of the three versions will now be detailed in the next section.
2.1.1 SAMV71
As already stated, one of the reasons for which the SAMV71 has been chosen is
because it exists in three different versions. Before presenting the space characteristics
of the radiation-tolerant and radiation-hardened versions, the main characteristics of the
standard version will be described. Figure 2.1.2 represents the block diagram of the
ATSAMV71Q21 microcontroller [4]. This gives an overview of the main functions of the
MCU in one picture.
Figure 2.1.2: Block diagram of the ATSAMV71Q21 [4].
2.1.1.1 Core
The main component of a microcontroller is its core. The ATSAMV71Q21 contains an
ARM® Cortex® -M7 core processor running at up to 300 MHz [4]. In addition to being
very powerful, this processor offers great flexibility and consumes relatively low power,
which makes it ideal for this application. Moreover, it supports Real Time Operating
System (RTOS) and there exists a lot of third party tools working with it. One of the main
17
properties of the Cortex-M7 is the presence of a six-stage, in-order super-scalar pipeline

that enables dual-issue processing of instructions. This feature allows the processor to run
two instructions in parallel. Another interesting point is that the latency of the Cortex-
M7 processor is reduced thanks to the fact that memory accesses are interleaved with
computation.
2.1.1.2 Memories
The ATSAMV71Q21 has different memories. They will now be detailed in turn [4].
Internal SRAM
The MCU contains 384 Kbytes of high speed Static Random Access Memory (SRAM).
Four priority levels are available to improve processor efficiency without compromising the
high-priority latency-critical requests. Some features make possible to optimize the SRAM
performances. First, it is equipped with a Multi-Port SRAM with four ports to ensure
optimal bandwidth and latency. Then, the MCU is equipped with an SRAM controller.
This one allows the minimization of latency by giving priority to the most urgent requests
without neglecting the less urgent ones. Indeed, the latter are executed at the latest
during the next cycle.
Tightly Coupled Memory (TCM) Interface
A tightly coupled memory (TCM) is integrated into the MCU. Unlike other memories
that are accessed at bus speed, TCM operates at processor speed. TCM is therefore
used to store critical parts of the code that require the fastest possible processing. It
is divided into two parts. The instruction tightly coupled memory (ITCM) is a single
64-bit interface that allows the processor to fetch two 32-bit instructions in a single access
and thus use the dual issue property of the pipeline. The data tightly coupled memory
(DTCM) consists of two interleaved 32-bit interfaces that makes possible the optimization
of concurrent accesses. Finally, the software allows both the configuration of the TCM in
4 different modes and the activation or deactivation of the ITCM and DTCM.
Internal ROM
The SAMV71Q21 embeds an internal Read Only Memory (ROM). It is used for the
SAM Boot Assistant, In-Application Programming and Fast Flash Programming Inter-
face functions.
Backup SRAM
The MCU embeds 1 Kbytes of backup SRAM. This one is only accessible in 32-bit
words. A power switch ensures that the contents of the backup SRAM are retained. In-
deed, in normal mode, it is powered by VDDCORE. However, in backup mode, when
VDDCORE is turned off, the power switch allows the backup SRAM to be powered by
VDDIO. To save power, the power switch can be turned off.
Flash Memories
18
The SAMV71 embeds 2084 Kbytes of internal Flash. It is organized in sectors of 128
Kbytes in size. Each sector is organized in pages of 512 bytes. Figure 2.1.3 represents the
general organization of the internal Flash. It is interesting to note that the first sector is
divided into three smaller sectors, two 8 Kbyte sectors, and one 112 Kbyte sector.
Figure 2.1.3: Flash Sector Organization [4].
The MCU has an Enhanced Embedded Flash Controller that manages the Flash mem-
ory. Thanks to it, it is possible to read the Flash and to write the write buffer. It also
provides the interface of the Flash block. It uses a complete set of commands to manage
the programming, erasing, locking and unlocking sequences of the Flash.
External Memories
Finally, the MCU includes an Synchronous Dynamic Random Access Memory Con-
troller (SDRAMC). This controller increases the memory capacity by allowing an external
16-bit DRAM device to be connected. The MCU also has an external bus interface giving
the possibility to use external memories. All external memories that have been used will
be presented in the next section.
2.1.1.3 Peripherals
The ATSAMV71Q21 has many peripherals. Therefore, only the most useful ones are
detailed below [4].
The Two-wire Interface
There are three different two-wire interfaces (TWI) on the SAMV71Q21. The TWI is
a two-wire bus used for data transfer that is based on a byte-oriented format. The two
wires correspond to a clock line and a data line. TWI is I2C compatible and works with
two-wire serial Electrically Erasable Programmable Read-Only Memory (EEPROM). An
I2C bus has been implemented in the software, its operation will thus be explained in
more detail in the following Chapter. TWI can operate at speeds up to 400 kbit/s in fast
mode and up to 3.4 Mbit/s in high-speed slave mode only. It uses a configurable baud
19
rate generator to match the clock rates of a wide range of external components.
Serial Peripheral Interfaces
Two Serial Peripheral Interfaces (SPI) bus are present on the MCU. It is a synchronous
communication system requiring only 4 wires to perform data transfers with external de-
vices. The SPI operating speed is generally way higher than the TWI one. As for the
I2C bus, a complete description of the functioning of the SPI bus is presented in the next
Chapter.
Analog Front-End Controllers
The MCU contains two Analog Front-End Controllers (AFEC) that rely on an Analog
Front-End cell containing various modules. It can be used to perform different types of
data conversion either in differential or single-ended mode and it has a programmable
gain stage. The conversion results range from 0V to VREFP which is the positive voltage
reference. It has a standard resolution of 12-bit which can be extended up to 16-bit. A
digital error correction circuit offers the possibility to reduce integral non-linearity and dif-
ferential non-linearity errors. This circuit is based on the multi-bit redundant signed digit
(RSD) algorithm. The Analog-to-Digital Converter (ADC) of the AFEC has been used in
the software of the OBC and some clarifications about it will be given in the next Chapter.
USART/UART
Three Universal Synchronous Asynchronous Receiver Transceiver (USART) and five

Universal Asynchronous Receiver Transmitter (UART) are available on the MCU. The
UART enables asynchronous serial communications while the USART enables synchronous
and asynchronous serial communications. The remaining part of this explanation will fo-
cus on the UART since it is a more widespread system. UART is a serial device-to-device
hardware communication protocol. Data is transferred bit by bit using only two wires for
its transmitting and receiving ends. Those two wires are Transmitter (Tx) and Receiver
(Rx). The data bus on the transmitter and receiver side transfers the data in parallel.
However, as in the UART data is sent and received serially, bit by bit, on a single line,
it must be converted at the beginning and end of the transfer. This is shown in Figure
2.1.4.
Figure 2.1.4: Representation of UART with data bus [5].
20
During the development of this thesis, this communication system has only been used
as a debugging tool to print messages on the terminal. However, as it is a very useful
communication system it will be used in future works based on this one, for example, to
communicate with the communication board.
Controller Area Network
Two Master Controller Area Networks (MCAN) can be used on the MCU. CAN is a
communication bus standard that allows communication between multiple devices with-
out a host computer. It is a message-based protocol that transmits data sequentially.
When multiple devices attempt to transmit at the same time, only the device with the
highest priority continues to transmit. Eventually, all devices connected to the bus receive
the data, even the sending device.
Real-Time Clock
The Real-Time Clock (RTC) device is developed for very low power consumption. A
crystal oscillator provides an accurate 32.768 kHz external clock that allows the RTC to
operate perfectly. The oscillator works when the power consumption is critical and the
MCU is in power saving mode. The choice of the crystal must therefore be made taking
into account its power consumption as well as the effects of temperature on its oscillation
frequency. An interesting feature of the RTC is the possibility it offers to program a
periodic interrupt. Finally, it also has a complete clock with an alarm and a Gregorian
or Persian calendar.
Real-Time Timer
The Real-Time Timer (RTT) is built around a 32-bit counter. It is used to generate
a periodic interrupt when the user-programmed value in the counter is reached. In its
standard configuration, the RTT uses the 16-bit programmable prescaler from the 32 kHz
slow clock. However, it can also be configured to operate with the 1Hz RTC signal to take
advantage of the 1Hz calibrated clock. Finally, when it is only necessary to count elapsed
seconds, it is possible to disable the slow clock source to reduce power consumption.
Power Management Controller
As explained in the Introduction, power is limited within the CubeSat. The Power
Management Controller (PMC) optimizes power consumption by monitoring all system
and user peripheral clocks. The PMC can actually enable and disable the clock inputs
of both the devices connected to the MCU and the Cortex-M7 processor. The MCU is
equipped with two oscillators that can act as clock signals, a slow RC oscillator, and a
32.768 kHz crystal oscillator. To optimize power consumption only one of the two oscil-
lators is used while the other is disabled. By default, at startup, the main RC oscillator
operating at 12 MHz is enabled. Finally, one of the main interesting features of the PMC
is that it can detect failures of the main crystal oscillator.
21
2.2. SELECTION OF THE OTHER COMPONENTS Master thesis
2.1.1.4 Other characteristics

The ATSAMV71Q21 possesses some very interesting characteristics that haven’t been
detailed yet. First, it has an embedded voltage regulator for single-supply operation [4].
In other terms, that means that the microcontroller only needs a single supply voltage of
3.3V. The embedded voltage regulator will convert this 3.3 V tension to a 1.23V tension
for the parts of the microcontroller needing it.
As far as reliability is concerned, the MCU features a Power-on-Reset, a Brown-out

Detector, a Watchdog Timer (WDT) as well as a Reinforced Safety Watchdog Timer
(RSWDT) working independently from the WDT for increased safety. The last two men-
tioned were used in this project and more details about them will be given in the next
chapter.
Finally, it is worth noting that the ATSAMV71Q21 is composed of 114 I/O lines with
external interrupt capability.
2.1.1.5 Space characteristics

The second version of the microcontroller, the SAMV71Q21RT [6] is the radiation-
tolerant version of the SAMV71. This version is perfectly suited for CubeSats as they
operate in LEO. It should therefore be the version of the MCU used in the final design
of the OBC that will be sent to space. The first improvement achieved by this device is
that it can work in temperatures ranging from -55 to 125◦ C while the operating temper-
atures of the ATSAMV71Q21 goe from -40 to 105◦ C. Besides being able to operate in
a wider temperature range than the standard version, the radiation-tolerant version has
the following characteristics in terms of radiation tolerance:
• It ensures an accumulated TID of 30Krad (Si) with latch-up immunity;
• It is nondestructive against heavy ions;
• It is completely immune to SEL below a Linear Energy Transfer (LET) Threshold

of 60 MeV.cm2 /mg at 125◦ C.
Finally, the third version, the SAMRH71 [7] is the radiation hardened version of
the SAMV71. Even if this version is more suited for deep space applications, its main
characteristics will be given. It operates in the same temperature range as the radiation-
tolerant version and has the following radiation performances:
• It ensures an accumulated TID of more than 100 Krad (Si);
• It ensures no SEU below an LET Threshold of 62.5 MeV.cm2/mg at 125◦ C;
• It includes SpaceWire interface with two SpaceWire ports with Integrated RMAP
support and embedded SpaceWire router.
2.2 Selection of the other components

Now that the microcontroller of the OBC has been presented, the other components
required by the OBC will be explored. These include the external components required
22
by the MCU in order to properly operate as well as some devices used to perform specific
tasks. Apart from the MCU, the memories are the most important components of the
OBC. Therefore, this point will be examined in detail.
2.2.1 Memories
The memories are naturally the first thing investigated after having chosen the MCU.
The OBC is the place where everything is stored in a CubeSat. There are two main
categories of memories. Volatile memories and non-volatile memories.
The basic difference between these two types of memories is that volatile memories lose
their data when they are no longer powered, whereas the data in non-volatile memories
is retained even without power [8]. Volatile memories may thus seem useless compared to
non-volatile memories. However, non-volatile memories are slower and have a higher cost
per bit compared to non-volatile memories. Moreover, volatile memories are more wear
tolerant than non-volatile memories. Volatile memories therefore have a great impact
on system performances while non-volatile memories have a great impact on the storage
capacity of the system.
It is important that the OBC contains both types of memory. It needs non-volatile
memories to save data that must be kept for a long time. And, since a lot of computing
is done within the OBC, it is essential that it also contains volatile memory for faster and
more frequent access.
The different types of technologies existing in these two categories will now be investi-
gated. Volatile memories will be studied first. Then the component chosen in this category
will be described. After that, the non-volatile memory systems will be detailed. Finally,
the three non-volatile memory components selected for the OBC will be presented.
2.2.1.1 Volatile Memory

As a reminder, volatile memory is the type of memory that loses its data when it is not
powered. It is used to store temporary data in order to increase the computation speed
and to reduce the workload of non-volatile memories and thus preserve them. Volatile
memory can be separated into two main categories: Static Random Access Memory and
Dynamic Random Access Memory (DRAM).
SRAM
A typical SRAM memory cell consists of six transistors [9]. Four of these are config-
ured as two cross-coupled inverters. This configuration works like flip-flops and provides
the two logical states "0" and "1". The other two transistors are used for access moni-
toring of the memory cell during read and write operations.
DRAM
DRAM memory cells, on the other hand, require only a single transistor combined
with a capacitor to maintain the state of the cell [9]. The "1" state happens when the ca-
pacitor is charged, while the "0" state occurs when the capacitor is discharged. However,
23
due to charge leakage, the capacitor will discharge itself. For this reason, it is necessary
to refresh periodically the cells of DRAM memories. This refreshing process ensures that
the state of the capacitor is not lost. The term dynamic comes from the need to refresh,
which SRAM does not have. In order to retain their data, DRAM must therefore be both
powered and refreshed periodically.
SDRAM
DRAM operates asynchronously. This means that it processes the information that
arrives one by one. Synchronous Dynamic Random Access Memory (SDRAM) constitutes
an improvement on DRAM [9]. SDRAM is synchronized to the MCU clock, which makes
it much more efficient. Because of its synchronous nature, SDRAM can operate in more
complex ways than DRAM. Indeed, it is able to keep two sets of memory addresses opened
at the same time. As a result, while DRAM must close one address bank before open-
ing the next, SDRAM can have two address banks opened at the same time. Therefore
SDRAM is able to prepare the next instruction while it is performing the current one.
It is worth noting that this feature of SDRAM is called pipelining. This characteristic
considerably reduces delays and therefore SDRAM is much faster than DRAM.
Comparison
Now that the different volatile memory technologies have been introduced they need
to be compared in order to motivate the choice made. This is done in Table 2.2.1.
Feature SRAM SDRAM

More expensive as they Cheaper as they only require
Cost
require 6 transistors 1 transistor and 1 capacitor
Faster as they don’t need to Slower because of the periodic
Speed
refresh the cells refresh of the cells
Density Low (6 transistors per bit) High (1 transistor per bit)
Lower as fewer cells can Larger as more cells can fit
Capacity
fit in the same space in the same space
Lower because they don’t need Larger due to the need to
Power consumption
to be periodically refreshed periodically refresh the cells
Table 2.2.1: Comparison between the main features of SRAM and SDRAM.
To conclude this comparison, it should be noted that none of these technologies are
radiation-tolerant. However, as they store data only for a short period, radiation does
usually not have enough time to corrupt their data.
Final choice
Due to its lower cost and higher capacity, it was decided to select an SDRAM as
volatile memory for the OBC. Once the technology is selected, it is still necessary to
choose between different types of systems.
24
Single data rate (SDR) is the first SDRAM that was created. After that, the Dou-
ble data rate (DDR) SDRAM was developed on the basis of SDR. The main difference
between the two is that DDR can access data on both edges of the clock signal, whereas
SDR can only access it on one edge. The speed of DDR is therefore twice that of SDR.
Further improvements in bandwidth and power consumption were then made with DDR2,
DDR3, and DDR4 technologies.
Finally, the MCU includes an SDRAM Controller (SDRAMC) [4]. This controller
is compatible with external 16-bit DRAMs and therefore increases the memory capacity
of the MCU. SDRAM performances are improved by the fact that the controller keeps
track of the active row in each bank. The controller optimizes the power consumption
of the external SDRAM device by offering different operating modes such as Self-refresh,
Powerdown, and Deep Powerdown. However, as this controller is only compatible with
SDR devices, this type of technology was finally chosen despite being a bit older and less
advanced than modern DDR technologies.
MT48LC16M16A2
The MT48LC16M16A2 [10] is a 256Mb high-speed CMOS SDRAM. Its operations are
burst-oriented. The location at which the memory is accessed and the number of locations
to be processed are configured by the user. In order to start an operation, an ACTIVE
command must be sent followed by a READ or WRITE command. It is possible to define
the length of the writes and reads. The refresh rate of this compound is 64 ms and an
automatic refresh mode is provided along with a power-saving mode and a power-down
mode.
2.2.1.2 Non-Volatile Memory

As already mentioned, non-volatile memories retain their data even when they are not
powered. This kind of memory is therefore used to store long-term data. An intuitive
example is sensor data coming from other subsystems. This data may simply need to be
stored in order to be reused by the CubeSat some time later or it can require to be sent to
the Earth. As communication between the CubeSat and the Earth is only possible when
the CubeSat is at some specific locations, the data should be stored while the CubeSat is
in a region where it cannot communicate with the Earth.
There are many technologies for storing data in a non-volatile way. Therefore only the
most popular ones will be presented in this thesis. After having explored these technolo-
gies, the chosen components will be detailed and their choice will be justified.
ROM
The first non-volatile memory technology investigated is the Read-Only Memory. As

the name suggests, it is impossible to write to this type of memory. The data is entered
into the device during its creation and cannot be changed afterward. These memories are
mainly used for applications where mass production takes place to store boot loaders and
application codes.
25
PROM
There are several variants of ROM-based memories. The first one is Programmable
Read-Only Memory (PROM). This type of devices can only be programmed once. They
are also mostly used in mass production, but this time for products with a shorter life
span. Indeed, unlike ROMs, they are programmed after they are manufactured. This
avoids the need to change the whole production line when updates are required. A differ-
ent code can simply be programmed after the production.
EPROM
Erasable Programmable Read-Only Memory (EPROM) is the next type of studied

ROM. Unlike the above-mentioned memories, EPROM can be erased and reprogrammed.
They have a small glass window. When this window is exposed to ultraviolet light for
a certain period, the data is erased and new data can be programmed. These memories
can therefore be erased and reprogrammed in the lab but not during operation. They
are therefore usually used during the development of applications during software testing.
When the software is finished, it is programmed onto a PROM.
EEPROM
Electrically Erasable Programmable Read-Only Memory is another type of memory

based on ROM. Like EPROM these memories can be erased but this time using an elec-
trical signal. This makes them easier to reprogram and more useful as external memories
needing to be reprogrammed several times.
Flash
Finally, the last type of non-volatile memory derived from ROM is Flash EEPROM,
more commonly referred to as Flash memory. Like EEPROM, Flash can be erased using
an electrical signal [9]. However, the data is erased and reprogrammed faster than with
EEPROM, hence the name Flash. Apart from the speed of reprogramming, the difference
between EEPROM and Flash is that the former gives the opportunity to reprogram bit-
by-bit, whereas the latter works in blocks. There are two main types of Flash memories
that must now be introduced: (i) NAND memories and (ii) NOR memories.
NOR Flash memory cells are connected in parallel to the bit lines. This makes it
possible to program the NOR memory cells individually. The name of these memories
comes from the fact that the cell arrangement resembles a NOR gate.
NAND Flash memory cells, on the other hand, are connected in series. This config-
uration then resembles a NAND gate. The cell structure of NAND and NOR Flash can
be seen in Figure 2.2.1. It must be mentioned that the cell structure of a NAND memory
shown in this figure is that of a single-level cell (SLC) that can store one bit of data per
cell. In order to increase the storage capacity, NAND operating with multi-level cells
or three-level cells have been developed. Nevertheless, while these technologies increase
storage capacity, their higher complexity reduces the speed of operations. This increased
complexity also leads to more bit errors, making it necessary to implement more complex
26
error correction codes (ECC).
Figure 2.2.1: Comparison between the cell structure of NOR and NAND memories.
Source : Toshiba America Electronic Components, Inc. November 2003
NAND & NOR comparison
Now that the cell structure of the two types of Flash memory has been presented, it
is time to compare their characteristics [11]. As can be seen in Figure 2.2.1, the serial
connection of the NAND memory cells makes them occupy less space than the parallel
connection of the NOR memory cells. The two consequences of this are that: (i) NAND
devices are provided with higher storage densities as more memory cells can be packed
into a single device and (ii) the cost per bit of NAND is lower than that of NOR.
As far as speed is concerned, it all depends on the type of operation performed. The
reading speed of NOR memories is faster than that of NAND memories. NOR has a full
set of address lines providing random access to each byte of memory. NAND on its side
accesses blocks or pages, which makes them slower to read a particular bit. On the other
hand, the above-mentioned characteristics mean that the erasing and writing speed of
NAND is higher than that of NOR.
With regard to the reliability of the stored data, NOR has better performance than
NAND. NAND memories already have some bad memory cells when shipped and the
number of bad cells will increase during use. NOR, on the other hand, is shipped without
any errors and the number of errors during use is very low.
27
It is also interesting to consider the differences in power consumption between these

two technologies. In active mode NOR consumes more power than NAND. However, in
standby mode, the opposite is true and NOR consumes less power than NAND. The most
interesting technology in terms of power consumption, therefore, depends on the operat-
ing and standby times.
NOR technology is typically chosen for applications that do not require very large
storage capacity but require very fast random read access combined with high data re-
liability. As a result, it is ideally suited for code storage in embedded systems. NAND
memory, on the other hand, is more suitable for storing data that requires larger storage
capacities and frequent erasing and writing.
Finally, Table 2.2.2 gathers all the information. It consists of a summary of the
different studied characteristics of NAND and NOR Flash memories.
Feature NOR NAND

Cost per bit Higher Lower
Storage Capacity Lower Higher
Read Speed Faster Slower
Erase Speed Slower Faster
Write Speed Slower Faster
Bit flip Less frequent More frequent
Active Power Consumption Higher Lower
Standby Power Consumption Lower Higher
Table 2.2.2: Comparison between the main characteristics of NAND and NOR Flash
memories.
Before proceeding to the details and justifications of the chosen components it is im-
portant to introduce one last memory technology that provides some of the advantages
of RAM while being a non-volatile memory.
FRAM
Ferroelectric Random Access Memory (FRAM) is a non-volatile memory that uses

a ferroelectric capacitor to store data [12]. This technology is based on the properties
of some materials with a perovskite type crystal structure. The most commonly used
material in FRAM is lead zirconate titanate (PZT) and its structure is shown in Figure
2.2.2a. The presence of a cation in the center of the PZT structure must be noticed. This
cation can take two equal and stable low-energy states. The FRAM technology takes
advantage of this cation. Indeed, when an electric field is applied to the PZT the cation
moves in the direction of the field. It is then sufficient to apply an electric field in the
required direction so that the cation moves and brings the PZT to the desired state. This
displacement produces energy in the form of a charge.
The structure of a FRAM memory cell contains the aforementioned ferroelectric capac-
itor as well as an access transistor. This structure, shown in Figure 2.2.2b, can therefore
recall that of the DRAM seen above. It can be noted that the symbol of the capacitor
28
is not the classical symbol of a linear capacitor since the ferroelectric capacitor has a
variable capacitance.
(a) Atomic structure of PZT [12]. (b) Structure of an FRAM memory cell [9].
Figure 2.2.2: The atomic structure of the ferroelectric material used in FRAM (a) and
the structure of an FRAM memory cell (b).
Although the name may sound like there is iron in FRAM, this is not the case. The
name actually comes from the resemblance between the well-known hysteresis loop in
ferromagnetic materials and the curve obtained when the charge of the ferroelectric ca-
pacitor is plotted as a function of the applied voltage. FRAM is therefore not affected
by magnetic fields. The main advantages and drawbacks of FRAM will now be considered.
The first strength of FRAM is its speed [13]. Writing can be up to 1000 times
faster with FRAM than with EEPROM or Flash. Then, data reliability is much bet-
ter with FRAM than with EEPROM or Flash. Indeed, it can generally perform up to
1015 write/erase cycles which is about 100 million times more than for EEPROM.
The FRAM also has some particularly interesting advantages for this project. Indeed,
it can modify data with very little current, resulting in very low power consumption.
Finally, the FRAM has an essential characteristic. It is radiation resistant which means
that it is very unlikely to be affected by the radiation phenomena presented in the Intro-
duction. The other memories studied so far are much more affected by these phenomena
which flip the state of a bit.
However, the FRAM has some negative points. The main one is that the ferroelectric
properties are lost when the material is too compressed. The memory cells of FRAM can
therefore not be as small as those of other memories. FRAM has therefore a lower storage
capacity and a higher cost per bit.
Final choice
It is now time to detail and justify the choices made in terms of non-volatile memory.
The advantages of FRAM in the harsh space environment make this technology necessary
in this project. Indeed, it is essential to have a reliable device to save important data in
the long term while minimizing the risk of errors associated with radiations. However,
29
the limited storage capacity of FRAM combined with its high purchase price makes it
impossible to only use this technology to save non-volatile data. As the density of the
chosen FRAM is 2 Mbits for a price of 15e, the choice was made to include 8 FRAMs
in the OBC design. This makes it possible to have enough space to store critical data
without paying too much or taking up all the space on the OBC’s PCB.
In order to complete FRAM with a non-volatile storage device of greater capacity and
lower cost, it was decided to use NAND Flash. The decision to use NAND rather than
NOR is due to the fact that the desired memory will have to be regularly written and
erased. As seen above, NAND is better for this type of operations. As Flash memory is
not radiation-tolerant, three NAND were placed on the OBC to increase the reliability.
Finally, in order to further increase the total storage capacity it was decided to place two
SD cards in the OBC design.
FM25V20A
As mentioned above, the FM25V20A [14] is a 2 Mbits FRAM memory. Since 8 of these
devices were placed in the design, the total FRAM memory is 16 Mbits. Communications
between the MCU and the FM25V20A take place via the high-speed SPI bus. This means
that the high communication speeds of FRAM are fully exploited. In terms of power con-
sumption, the FM25V20A consumes 800 µA at 1 MHz, 100 µA in standby mode, and
3 µA in sleep mode. Although the SPI bus will be explained in the next chapter, it is
important to point out that one line of this bus is used to choose which component the
MCU communicates with. Each component must therefore have a dedicated selection
line. However, by using a demultiplexer, the number of MCU pins required to select a
FRAM can be reduced from 8 to 4.
After selecting the FRAM with which communication is taking place, the user can
perform a write/read operation to that memory. To do this, the user must send a first
byte corresponding to the opcode of the operation to be performed, followed by 3 bytes
corresponding to the address where this operation is to be effectuated. The FM25V20A
has 256K locations of eight bits of data. The 3 bytes (i.e. 24 bits) of address are thus
used to code the 18 bits necessary to differentiate all the addresses. It should be noticed
that the first 6 address bits are " don’t care " values. Finally, it is interesting to note that
the access time to the memory is practically zero, which means that the speed of reading
or writing data is the speed of the SPI bus.
MT29F2G01ABAGDWB
MT29F2G01ABAGDWB [15] is a 2GB NAND Flash memory that operates through

the SPI bus. It uses SLC technology and therefore prioritizes speed and data reliability
over higher capacity.
This device is made up of blocks, each of which has 64 programmable pages. A pro-
grammable page consists of 2048 bytes of data storage area and 128 bytes used for memory
and error management. This makes a total of 2176 bytes per page. Reading and writing
to this memory is done by pages while erasing is done by blocks.
30
It is also important to talk about data reliability with this component. As mentioned in
the presentation of NAND memories, this type of technology is subject to data corruption
in the form of inverted bits. In order to reduce these errors, the MT29F2G01ABAGDWB
has an error correction code that can detect and correct some of those errors. Finally, the
choice to place 3 of these devices on the OBC PCB was not made to triple the storage
capacity but to have triple modular redundancy (TMR). The three NAND store the same
data and a majority voting system is used to reduce the risk of errors induced by the
harsh space conditions against which the NAND is not protected.
SD Card
For the moment, two sockets that can hold SD cards have been placed on the PCB.
The choice of the SD cards used has not yet been made. As the payload and some of the
functions that the OBC will have to perform are not yet known this choice is impossible.
Indeed, the capacity of the SD card as well as some of its characteristics depend on these
elements. However, some research has already been carried out to give an idea of the type
of SD card to be chosen for the CubeSat. The results shown in this paper [16] indicate
that not all technologies are equal and that it is better to choose an industrial grade SD
card over a consumer grade one.
2.2.2 Oscillators
The MCU and its peripherals require clock signals to operate. The role of oscillators is
to provide a stable clock signal at a predetermined frequency. There are different types of
circuits that can act as oscillators, but the ones that offer the most accuracy and stability
are quartz crystals. In an OBC it is important that the clock signals are as accurate and
stable as possible to avoid all kinds of problems. This is why quartz crystals are chosen as
oscillators in the design. Two oscillators are required by the MCU, a slow clock oscillator
with a frequency of 32.768 kHz and a fast clock oscillator with a frequency between 3 and
20 MHz.
The MS1V-T1K 32.768KHz [17] has been chosen as slow clock crystal oscillator. It
is a square-bodied metal structure containing a high-quality quartz crystal resonator. Its
operating temperatures range from -40 to +80◦ C.
Concerning the high frequency oscillator, the 12MHz ABM3BAIG [18] has been se-
lected. The crystal is placed in a closed ceramic package which ensures high precision and
reliability. Its operating temperatures range from -40 to +125◦ C.
2.2.3 Connectors
Connectors can be used to connect different PCBs between them or to connect a PCB
to an external device. There are two types of connectors required in this thesis. The
first one is a PC/104 used to interconnect the different boards constituting the CubeSat.
The second one is a RJ-11 connector used to connect the PCB to an external In-Circuit
Debugger/Programmer (ICD). These two connectors are described below.
31
2.2.3.1 PC/104
As it has been presented in the Introduction (Figure 1.2.1), the CubeSat is made of
a superposition of different boards. It is essential that some signals are transmitted from
one board to another. An intuitive example is the power signals that are generated on the
EPS board but must be accessible on all other boards. The PC/104 allows this inter-board
communication. Indeed, each board is equipped with one of these connectors and they
are stacked on top of each other. In addition to the power signals which are obviously
essential, the OBC uses the PC/104 to enable communication between the other boards
and the microcontroller. Two examples of communication signals present on the PC/104
of the OBC are the I2C lines and the SPI lines.
2.2.3.2 RJ-11 connector

The MPLAB ICD 4 [19] is used to program and debug the microcontroller. It is
compatible with the MPLAB Integrated Development Environment (IDE), which has
been used to implement the software of the OBC. The ICD 4 has to be connected to a
computer through a USB 2.0 interface to get its power. Once it is powered, the device is
connected to an RJ-11 connector placed on the OBC PCB. This connector comprises six
pins which are listed below:
1. VP P : power;
2. VDD_T GT : power on target;
3. GND: ground;
4. PGD: Standard Com Data;
5. PGC: Standard Com Clock;
6. Reserved.
Figure 2.2.3 shows an MPLAB ICD 4 along with its connections. The only difference
between the image and the use of the device in this thesis is obviously that the test
interface module has been replaced by the OBC PCB.
Figure 2.2.3: MPLAB ® ICD 4 connection example [19].
32
2.2.4 Power monitoring

As it has been explained in the previous section, the OBC board receives its power
from the EPS board through the PC/104. All the components present on the OBC board
operate at a voltage of 3.3V. For that reason, the only power signals on this board are
3.3V and ground.
2.2.4.1 Protection circuit

Although the EPS board is supposed to provide a stable 3.3V signal, it has been de-
cided to place a device to monitor the voltage and current coming from the EPS upstream
of the other components of the OBC board. This device is the LTC4368 [20] and has the
following features:
• Overvoltage protection;
• Undervoltage protection;
• Forward and backward overcurrent protection.
To perform its protection functions the LTC4368 is connected to a Dual N-Channel

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) used as a switch. When
the LTC4368 detects a voltage or current outside the defined ranges, it isolates the load
from the power supply by switching the MOSFET off. Overvoltage and undervoltage are
detected using comparators whose values are set via several external resistors forming a
voltage divider. Overcurrents are detected using an external sensing resistor that allows
the selection of the overcurrent value. Figure 2.2.4 shows an example application of the
LTC4368.
Figure 2.2.4: Example application of the LTC4368 [20].
33
The choice of the resistor’s values for the OBC protection is based on the equations
2.2.1, 2.2.2, 2.2.3, and 2.2.4. The first one is based on VOS(U V ) , which is the maximum
tolerable offset voltage at the UV pin, and IU V , which represents the worst case leakage
current at the UV pin. IU V is given to be equal to 10nA and VOS(U V ) is chosen to be equal
to 3mV. It is worth noting that in what follows, R3 corresponds to R3 + R4 from Figure
2.2.4. The first equation is obtained as being:
VOS(U V ) 3mV
R1 + R2 = = = 300kΩ (2.2.1)
IU V 10nA
The second equation is based on the UV threshold value which is chosen equal to 3V
in this application since the minimum supply voltage of the MCU is 3V. It also relies on
the comparator rising threshold voltage which is equal to 0.5V. The equation is thus given
by:
VOS(U V ) U VT H − 0.5V 3mV 3V − 0.5V
R3 = · = · = 1.5M Ω (2.2.2)
IU V 0.5V 10nA 0.5V
The last two equations are based on the OV threshold value, which is chosen equal to
3.6V as the maximum supply voltage of the MCU is 3.6V. These equations are as follows:
VOS(U V ) 3mV
( IU V
) + R3 ( 10nA ) + 1.5M Ω
R1 = · 0.5V = · 0.5V = 250kΩ (2.2.3)
OVT H 3.6V
VOS(U V ) 3mV
R2 = − R1 = − 250kΩ = 50kΩ (2.2.4)
IU V 10nA
The equations giving the forward and backward overcurrent are easier. The forward
overcurrent threshold (IOC,F W D ) is determined by the value of the external sense resistor
(RSEN SE ). Indeed, the forward current passing through RSEN SE generates a voltage that
is compared with a 50mV threshold by an internal comparator. It has been decided to
limit the forward current to 0.5A. The value of RSEN SE is thus given by:
50mV 50mV
RSEN SE = = = 0.1Ω (2.2.5)
IOC,F W D 0.5A
Concerning the reverse overcurrent, the method is the same. The only difference is
that the voltage generated by the reverse current flow through RSEN SE is compared to a
threshold of -3mV. The reverse overcurrent threshold (IOC,REV ) is thus given by:
−3mV −3mV
IOC,REV = = = −30mA (2.2.6)
RSEN SE 0.1
To conclude on the use of the LTC4368, Table 2.2.3 resumes the threshold values
causing the device to switch the MOSFET off in order to protect the OBC components.
34
Type of protection Threshold value

Undervoltage 3V
Overvoltage 3.6V
Forward overcurrent 0.5A
Reverse overcurrent -30mA
Table 2.2.3: Summary of the protection threshold values of the LTC4368.
2.2.4.2 Power consumption

In addition to the protection circuit, it was decided to measure the power consumption
of the OBC board. For this purpose, the MAX9938 device [21] and the AFEC of the MCU
were used. The MAX9938 is a high-side current sense amplifier that amplifies the voltage
generated by the current flowing through a sense resistor with a voltage gain of 25V/V.
A special characteristic of this device is that its input common-mode voltage is used as
supply voltage. Its typical operating circuit is represented in Figure 2.2.5.
Figure 2.2.5: Typical operating circuit of the MAX9938 [21].
The choice of the RSEN SE had to be done carefully. Indeed, a large value would have
caused a lot of power dissipation due to the I 2 RSEN SE losses. RSEN SE was finally chosen
equal to 20mΩ. The output voltage of the MAX9938 goes to the AFEC of the MCU and
is converted using its ADC module. A capacitor is placed at the output of the MAX9938.
It is used to stabilize the voltage while it is sampled by the ADC as well as to reduce
the noise at the output. The power consumption of the OBC can thus be monitored easily.
Since the CubeSat project is not yet ready to be tested in its entirety, the results
obtained now would not have been representative. Indeed, most of the power consumption
of the OBC will come from the tasks related to the other subsystems of the CubeSat. For
this reason, no power consumption test was performed during this thesis.
35
2.3. FINAL PCB PRESENTATION Master thesis
2.3 Final PCB presentation

To end the presentation of the hardware part of this project a representation of the
final OBC’s PCB is given in Figure 2.3.1. It is divided into separate areas that have been
highlighted with colored rectangles. The components laying in each rectangle will now be
listed.
• The yellow rectangle contains the microcontroller and its passive components;
• The red rectangles include the eight FRAMs along with their passive components
and the demultiplexer that has been used with these memories;
• The two black rectangles enclose the two crystal oscillators. The 32.768KHz slow
clock crystal oscillator is on the top side while the 12MHz high frequency crystal
oscillator is on the bottom side;
• The orange rectangles comprise all the components linked to the power monitoring;
• The white rectangle contains the DRAM and its passive components;
• The green rectangles include the two micro SD card sockets along with their passive
elements;
• The purple rectangle comprises the three NAND memories and their passive com-
ponents;
• The brown rectangle simply contains the demultiplexer used by the micro SD cards
and the NAND memories;
• The pink rectangles include the RJ-11 connector and its passive components;
• The big white box and the 120 pins situated at the bottom of respectively the top
and bottom views is the PC104 connector.
It is worth noting that a lot of free space has been left on the PCB. This has been
done intentionally to allow the addition of other components in this area. Indeed, as
the payload of the CubeSat is still to be determined, it might be necessary to add some
components in the future development of the OBC.
36
2.3. FINAL PCB PRESENTATION Master thesis
(a) Top view.
(b) Bottom view.
Figure 2.3.1: 3D top (a) and bottom (b) views of the final OBC’s PCB.
37
Chapter 3
Software implementation
The OBC is the subsystem at the center of the CubeSat design that interacts with
all the other subsystems. It can thus be viewed as the brain of a CubeSat. However,
until now the only link between the OBC and the other subsystems is a mechanical one
that happens through the PC/104 connector. A software is therefore required in order to
implement the actions of the OBC.
This chapter is dedicated to the introduction of this OBC software. The first thing
while designing the software of an embedded application is to select a software architec-
ture. The first section will thus be related to that selection. After that, some explanations
will be given about the software program that was used to develop the code. Lastly, the
different OBC applications implemented during this thesis will be detailed. This will give
an overview of what the OBC can already do and how those tasks have been implemented.
It is worth mentioning that all the codes have been implemented using the C programming
language.
3.1 Software architecture

The choice has been made to develop the software of the OBC following a Real-Time
Operating System (RTOS) architecture. An operating system (OS) is the part of the
software that manages the interaction between tasks and the system resources [22]. It is
composed of a kernel that controls the system and a library of functions that facilitate its
use. RTOS is the OS developed for embedded applications.
Some important features of RTOS need to be introduced. An RTOS is made of sev-

eral tasks each with a given priority and a given state. Interrupts are also available. An
interrupt consists in sending a signal asking the processor to suspend the task currently
in progress in order to execute an interrupt routine making it possible to execute urgent
operations within them. The kernel contains a scheduler that manages the state of the
system by assigning the processor to the tasks.
Data communications between different tasks is critical and can be handled with
semaphores and message queues. Semaphores are objects having a value ≥ 0. A semaphore
can either be given, which increments its value, or taken, which decrements its value. A
semaphore can only be taken if its value is > 0. Message queues are objects used to
transfer data between tasks. The number of messages that a queue can store and the size
38
3.2. MPLAB Master thesis
of a single message are fixed by the user. A task trying to read an empty queue moves to
the suspended state.
Finally, there are five possible states for a task:
1. Dormant: The task is not scheduled;
2. Active: The task is currently running;
3. Executable: The task is ready to perform operations but another task is already
active;
4. Blocked: The task is suspended and waits for a signal, or for a resource;
5. Interrupted: The task is executing an interrupt routine.
There are a lot of advantages to the use of RTOS. First, the OS dynamically controls
the execution of non-urgent tasks through the scheduler and can suspend a task before
its completion to execute another one. This allows long computations to be performed
while maintaining low latency. Then, the structure of the RTOS makes it easy to add
new tasks without having to rethink the whole system. This feature is particularly useful
in the case of this project as the payload of the CubeSat is still to be determined and
therefore additional tasks will need to be implemented and performed by the OBC.
On the other hand, drawbacks of RTOS include the difficulties introduced by data
exchange and the consumption of resources by the OS. In addition, the main difficulty
associated with RTOS is the complexity of its implementation. However, this is not a real
problem as there already exist open source RTOS that can be used. The one used in this
project is FreeRTOS.
3.2 MPLAB
MPLAB X IDE is a freeware developed by Microchip that is widely used for em-
bedded applications. It offers some interesting characteristics such as a debugger and a
code configurator, which will be explained in more detail in the next section. It is also
worth noting that some examples of codes using the ATSAMV71Q21 are available on the
Microchip website [23].
3.2.1 Harmony v3
Harmony v3 is an embedded software integrated into MPLAB X IDE which offers soft-
ware modules that simplify the development of the code. In order to use it, the first step
is to download the necessary modules for the application that needs to be implemented.
This is done using the Harmony 3 Content Manager that can be found by going to the
Tools tab in MPLAB X IDE and then selecting Embedded > MPLAB ® Harmony
3 Content Manager. The next step is to launch the Harmony 3 Configurator. This is
done by clicking Tools > Embedded > MPLAB ® Harmony 3 Configurator. At
that point, the project graph will open. All available modules are then listed under the
tab Available components. The user must now select the modules needed in his appli-
cation. Figure 3.2.1 shows the modules used for the implementation of the software of the
39
3.2. MPLAB Master thesis
OBC. Each module must also be configured with the appropriate values. The most im-
portant ones will be detailed in the corresponding subsection of the Code implementation
section.
Figure 3.2.1: Project graph
When the project graph is finished, it is necessary to assign the different pins of the
microcontroller. This is done by going to the MHC tab that is present in MPLAB
X IDE when the Harmony 3 Configurator is open and then selecting Tools > Pin
Configuration. The pin diagram of this project is depicted in Figure 3.2.2. This one
makes it possible to see that many pins of the MCU are still available. Most of them will
be assigned before launch once the other subsystems of the CubeSat will be finished.
40
3.3. CODE IMPLEMENTATION Master thesis
Figure 3.2.2: Pin diagram of the ATSAMV71Q21. The green pins are the ones assigned
while the blue ones are available and the grey ones are unavailable.
It is also worth mentioning that some other interesting functionalities are available by
clicking MHC > Tools such as the Clock Configurator or the Nested Vector Interrupt
Control (NVIC) Configurator.
Finally, when the project graph and all configurations are completed, the code can
be generated by clicking on the "Generate Code" icon. At that point MPLAB X IDE
generates all the required drivers’ code. Those can be found in the project files.
3.3 Code implementation

For this project, five tasks were implemented in order to achieve all the objectives of
the project. Each task has a set of states in which it can be. The states indicate what the
task is currently doing. In addition, a data structure representing the data of the task is
associated to each task.
41
3.3.1 I2C
An I2C bus is a serial communication mechanism consisting of a pair of two-way lines:
(i) the Serial Data (SDA) line and (ii) the Serial Clock (SCL) line [22] [24]. The default
state of both lines when no communication is in progress is high. To do this, the lines
are connected to VDD through pull-up resistors. Thus, the devices connected to the
I2C bus can only pull the lines down. Master and slave are two important terms in the
I2C protocol. The master is the device that generates the clock signal and manages the
data transaction with the slaves. The slave on its side is the device responding to the
instruction of the master. Regarding the transmission speed, the standard mode speed is
100kHz while the fast mode speed is 400kHz. Figure 3.3.1 represents the structure of an
I2C bus with one master and three slave devices.
Figure 3.3.1: Structure of an I2C bus with one master and three slave devices [24].
Figure 3.3.2 shows an example of communication on an I2C bus. A communication

always starts with a start condition and always ends with a stop condition. These two
conditions are sent by the master and correspond to the only two moments when a tran-
sition from high to low on SDA is possible while SCL is high. At all other times, SDA
changes must take place when SCL is low.
Between the start and stop conditions data are exchanged in 8 bits blocks and Most
Significant Bit (MSB) first. The master always sends the first block. It corresponds to
the address of the slave and the direction of the communication. Indeed, the first 7 bits
represent the address of the slave while the last one indicates whether the master wants
to perform a read or a write operation with the slave. A low value of the 8th bit means
that the master will write data to the slave while a high value of the 8th bit means that
the master will read data sent by the slave. The other data blocks are thus sent by the
master in case of a write operation or by the slave in case of a read operation. Moreover,
any number of data blocks can be communicated between the start and stop conditions.
The last essential information about I2C concerns the acknowledge (ACK) and not
acknowledge (NACK) bits. Indeed, each block of data is followed by a bit placed on SDA
by the receiver. This bit is used as a verification mechanism. The first ACK is sent by the
slave which address corresponds to the one sent by the master. In case the master sends
an address that does not correspond to any slave, the first block is not acknowledged and
the communication stops immediately. Concerning the subsequent blocks, if the receiver
does not acknowledge the block the communication is also immediately stopped.
42
Figure 3.3.2: Example of communication of an I2C bus. Note that in this figure TWD
corresponds to SDA in the text while TWCK corresponds to SCL [4].
One of the advantages of I2C buses is that they allow communication between many de-
vices using only two wires. Another advantage is the feedback provided by the ACK/NACK
bit. Regarding the disadvantages, the first one is the limited speed of I2C bus communi-
cations when compared to the speed of SPI bus communications. Finally, it is important
to point out that all the slaves on an I2C bus must have different addresses in order to
identify which one the master wants to start a transaction with.
3.3.2 SPI
Serial Peripheral Interface (SPI) is a 4-wire synchronous serial communication inter-
face. The four signals used by SPI are the following [25]:
• Serial Peripheral Interface Clock (SPCK);
• Master In Slave Out (MISO);
• Master Out Slave In (MOSI);
• Chip Select (CS).
As the names of the signals indicate, the SPI works with master and slaves as was
the case with the I2C bus. The clock signal is generated by the master and is used as
a synchronization method. MISO and MOSI are the two lines for data transfer. The
first one corresponds to the line on which the slaves send data to the master while the
second one is the line on which the master sends data to the slaves. The master can only
communicate with one slave at a time. The CS line is used for that purpose. Indeed,
the standard state of this line is high and when the master wants to communicate with
a slave, it pulls the CS line of that slave down. During communication between a master
and a slave, all CS lines other than that of the slave communicating must be high.
It is important to specify that SPCK, MISO, and MOSI lines are shared by all the
devices connected to the SPI bus, while every slave has a different CS line. Finally, the
CS lines can be connected to a demultiplexer in order not to use too many pins from the
master. That method has been applied in this thesis and is depicted in Figure 3.3.3 along
with the above-mentioned SPI components.
43
Figure 3.3.3: Representation of an SPI bus working with a demultiplexer used to decode
the CS lines [4].
Before explaining the way data are exchanged in SPI, it is necessary to introduce the
clock polarity (CPOL), the clock phase (CPHA), and the idle state concepts. The latter
corresponds to the start and end of communications when the CS signal switches from
high to low and from low to high respectively. CPOL and CPHA on their side relate to a
specificity of the SPI bus. Indeed, the master must define a polarity and a phase for the
clock signal that satisfy the technical characteristics of the slave. This is done through
the CPOL and CPHA bits. The first one defines the polarity of the clock signal in the
idle state. The second one determines on which clock edge the master writes on MOSI
and on which one the slave writes on MISO. Master and slave writes always occur on
opposite clock edges.
To initiate a communication, the master must generate a clock signal and pull down the
CS line of the slave with which it wants to initiate a transmission. Another characteristic
of SPI is that it is a full-duplex interface. This means that data are transmitted both
on MOSI and MISO even when only one line is sending a useful signal. At the end of
the communication, the master has to pull the slave CS line back to the high state. An
example of SPI communication with CPHA = 1 is shown in Figure 3.3.4. However, it is
interesting to note that the selected microcontroller uses NCPHA instead of CPHA where
the N simply means Not.
44
Figure 3.3.4: Example of an SPI communication with NCPHA = 0 [4].
Finally, one of the main advantages of the SPI bus is its speed. Indeed, it can operate
at speeds up to a few MHz. On the other side, it requires at least 4 wires and that number
can quickly increase with the number of slave devices.
3.3.3 External I2C bus task

The role of this task is to enable communication with the TCA9555 [26]. The TCA9555
is a 16-bit I/O expander for the I2C bus. It comprises two ports of 8 pins that can be con-
figured as inputs or outputs. The user can configure the direction of each pin by writing
the appropriate bit inside the configuration register. At power on, all pins are configured
as inputs. This component also includes an interrupt pin that indicates when a new value
appears at one of the inputs. This device is used by the EPS board to monitor different
signals.
The initial state of the task performs the configuration of the I2C driver used to com-
municate with the TCA9555. The I2C driver clock speed is set at 400kHz.
Once the I2C driver is initialized, the task moves to the state in which the TCA9555 is
configured. In that state, the task waits for a message on the I2C_Queue. This message
is sent by the user task and contains the transfer type, which must be equal to TRANS-
FER_TYPE_I2C_CONFIGURATION, as well as the values of the two configuration
registers of the TCA9555. The role of these registers is to configure the directions of the
I/O pins. In order to define a pin as an input, the bit corresponding to this pin must be
set to 1 in the configuration register. Conversely, when the bit corresponding to a pin is
set to 0, the pin is defined as an output. When the message queue has been received, the
two configuration registers are initialized with the values defined by the user. The last
thing to do in this state is to read the values of both ports before activating the interrupt
I2C pin of the MCU connected to the interrupt pin of the TCA9555. Indeed, modifying
the configuration registers can cause an interrupt to occur and that is the reason why the
MCU I2C interrupt pin is only enabled after the initialization of these registers.
45
When the initialization of the I2C driver and of the configuration registers is over, the
task moves to the read/write state. In this state, the task waits once again for messages on
the I2C_Queue coming from the user task. A message contains the type of operation to
be performed, one or two data bytes depending on the type of operation to be performed,
and the address to which the data must be stored in the case of a read operation. The
five different types of messages will be described hereafter.
The first type is a port write request. In this case, the user task sends a data byte
and the port in which this byte has to be written. The I2C task then performs the write
of that byte in the right port.
The second type of operation is a bit write. The process is similar to the previous
case, except that the data byte is replaced by a data bit and the port is replaced by a
channel.
The third type is a port read request. Here, the user task sends the number of the
port that needs to be read and the address of the FRAM where the result must be stored.
The I2C task then performs a read of that port and sends the result to the FRAM.
The fourth type, which corresponds to a read bit, works in the same way as the pre-
vious one with the difference that the port is replaced by the channel.
Finally, the fifth type is called by the user task when an interrupt occurs on the MCU
I2C interrupt pin. In this case, the user task only sends the FRAM address to which the
data have to be stored. The I2C task then reads the two ports of the TCA9555 and the
results are stored in the FRAM.
3.3.4 External ADC (SPI) task

This task is responsible for performing analog to digital conversions using the MAX11128
[27] and saving their results in the FRAM memory. The MAX11128 is a high speed
analog-to-digital converter that has low-power consumption characteristics. Indeed, it
only consumes 5.4mW at a speed of 1 Megasamples per second with a 3V power supply.
It has 16 ADC channels that can be configured in single ended or differential mode and it
can be used with internal or external clock signals. This device is used in the EPS board
to monitor some signals.
Its first state is responsible for the initialization of the SPI driver used to communicate
with the MAX11128. The SPI driver parameters are the following:
• A baud rate in Hertz of 1MHz.
• Data is changed on the leading edge of SPCK and captured on the following edge
of SPCK.;
• Idle High Clock Polarity;
• 8 data bits per transfer;
• Pin PD27 used as chip select pin with active low polarity configuration of the chip
select.
46
When the SPI driver is configured, the task goes to the configuration state in which
the MAX11128 is configured by putting the appropriate values in the ADC Configuration
register. The configuration is the following:
• External single-ended voltage reference;
• Averaging mode off;
• 1 conversion for each requested result;
• Scans channel N and returns 4 results if repeat mode activated;
• Full shutdown power mode;
• Instruction echo on Data OUT (DOUT) disabled.

In full shutdown power mode, all circuits are powered down at the end of each conver-
sion. The falling edge of CS switches the device back on and 2 cycles are needed before
valid conversions take place. Finally, it is worth noting that the information in the regis-
ters is not lost while the device is in full shutdown.
After the SPI driver and the MAX11128 are configured, conversions can take place.
In order to do that, the task enters in the conversion state. In this state, the task waits
for a conversion instruction to be received on the ADC_Queue. A conversion instruction
is a data structure consisting of the high and low bytes of the ADC Mode Control register
along with the address where the conversion must be stored in the FRAM.
Concerning the two ADC Mode Control registers, they are defined in the Constant.h
file and configured in the following way:
• The conversions are started manually;
• The user selects the channel for which he wants the conversion;
• The registers are not reset;
• Auto Shutdown mode;
• DOUT is a 16-bit data word starting by a default 0 bit, followed by a 15-bit con-
version result led by the MSB.
When the conversion has been performed, the result is read and finally sent to the
FRAM address that was previously specified by the user.
3.3.5 FRAM (SPI) task

The role of this task is to store data in the FM25V20A [14] FRAM memories and to
read it back when needed. Its first state corresponds to the initialization of the SPI driver
used to communicate with the FM25V20A memories.
Before detailing the configuration of the driver, it is important to mention that some
modifications had to be made in the source files generated by the Harmony v3. Indeed,
as explained in section 2.2.1.2, the FRAM chip select is managed with a demultiplexer. It
47
is therefore necessary to be able to manage the 3 FRAM chip select pins and the demul-
tiplexer enable pin simultaneously. This was not the case in the original codes in which
only one chip select could be defined per SPI driver handler.
Another important comment must be made concerning the use of the FRAMs. Each of
these memories has addresses ranging from 0h to 3FFFFh. To simplify the use of the code,
the memory addresses range from 0h to 23FFF6h which corresponds to 9 · 3F F F F h − 1.
Thus, the user only needs to provide a memory address within this range and the program
is responsible for finding the memory and the internal address of that memory correspond-
ing to the value entered.
Having explained the above, the configuration of the driver can be detailed. It is as
follows:
• A baud rate in Hertz of 1MHz;
• Data is changed on the leading edge of SPCK and captured on the following edge
of SPCK;
• Idle High Clock Polarity;
• 8 data bits per transfer;
• Pins PA25, PD25, and PA5 used as chip select pins with active low polarity config-
uration of the chip select.
When the initialization of the driver is done, the task moves to the transfer state. In
this state, it waits for a read or write instruction on the FRAM_Queue. In addition to
the write or read instruction, the message queue contains the address of the FRAM with
which communication is desired, the size of the transfer and the data to be saved in the
case of a write. The received address is transferred as a 32 bits integer. At that point,
it is therefore decomposed in the 3 addresses of 8 bits needed to communicate with the
FM25V20A. The number of the FRAM with which the communication has to take place
is retrieved at the same time. Once the correct FRAM is selected and the 3 addresses
bytes are known, the task can proceed with the writing or reading of data.
In order to write data to the FM25V20A the first thing to do is to issue the Write
Enable (WREN) command. Then the write operation can be performed. It starts with
the WRITE opcode followed by the 3 addresses bytes and finally by the data that has to
be written in the FRAM. It is worth noting that CS has to be deasserted between the
WREN and the WRITE commands.
The reading operations on their side work in the following way. The first byte sent
to the FM25V20A corresponds to the READ opcode. This one is followed by the three
addresses bytes. After that, the FM25V20A starts sending the data bytes on the MISO
line. The number of data bytes sent from the FM25V20A is equal to the number of bytes
specified by the user in the message queue when requesting a read operation. It is inter-
esting to note that the MOSI line is ignored while a read operation is in progress.
48
Finally, the following are some specificities of the FM25V20A, both in write and read
mode:
• The addresses continue to be incremented as long as the master continues to transmit

a clock signal and CS is low;
• If the last address of the FRAM is reached, the counter will jump back to the first
one;
• Data are written/read MSB first;
• A rising edge of CS terminates the current operations.
3.3.6 User task

The user task has already been mentioned many times in the previous points. Indeed,
it is the task that manages all the other tasks. It was developed mainly but not only to
show how the other tasks should be used in the future use of this work. The first notable
thing about this task is that the three message queues already mentioned before are cre-
ated at the initialization of the task. Each queue is created with a number of elements
being equal to a constant defined in the Constants.h file. The size of an element is itself
equal to the size of the data structure used in that queue.
The first state of this task is used as a configuration state. In this state, the different
flags and callback functions are initialized. A callback function and a flag are linked to
each interrupt. When the interrupt occurs its corresponding callback function is called.
This function updates the status of the flag related to it.
Once everything has been initialized, the task moves to its operating state. In this
state, the task basically checks the value of different flags in an infinite loop. When the
value of a flag is true, the user task performs the application related to this flag, changes
the value of the flag to false, and then moves to the next flag. These flags are used for three
different things. The first one corresponds to timer interrupts used to send a message to
one of the tasks detailed above through the corresponding message queue. This is done
in order to show how the other tasks can be used in future works. The other two types
of flags relate to the MCU’s internal ADC and watchdog timers. They will be described
in the following sections.
3.3.6.1 Internal ADC

The second application requiring flags in the user task is linked to the MCU Analog
Front-End Controller [4]. Before detailing the role of those flags, some details about the
AFEC are needed. The part of the AFEC that is used in this application is the Analog-
to-Digital Converter.
This ADC has a standard resolution of 12 bits and integrates a sleep mode which is of
great interest in this project. A final point of great value is that the AFEC incorporates
a temperature sensor. This one will thus be used in order to monitor the temperature
around the MCU. In addition to being used to obtain a voltage proportional to tem-
perature, the MCU’s internal ADC is also used to monitor the power consumed by the
49
OBC. Indeed, as described in section 2.2.4, a MAX9938 is present on the OBC in order
to monitor constantly the consumed power.
Now that the AFEC has been detailed, the flags that depend on it can be explained.
The first flag simply relies on a timer interrupt used to launch the ADC conversions. The
second flag relies on the AFEC driver functions and is true when the specified AFEC
channel result is ready to be read. To conclude on the use of the internal ADC, it is
important to notice that some manipulations have to be made with the ADC results. The
formula 3.3.1 is used to obtain the ADC voltage from the ADC result.
AFEC_VREF
ADC_voltage = ADC_result × (3.3.1)
ADC_COUNT_MAX
Where the AFEC parameters are as follows:
• Positive reference voltage: AFEC_VREF = 3.3V;
• ADC_COUNT_MAX is equal to 212 − 1 as the ADC has a resolution of 12 bits.
Finally, the temperature is obtained with the formula 3.3.2.

100
Temperature = (ADC_voltage − 0.72) × + 25 (3.3.2)
233
Where the temperature sensor parameters are the following:
• Typical ADC_voltage at 25◦ C = 0.72V;
• Typical temperature Sensitivity = 2.33mV/◦ C.
3.3.6.2 Watchdog timers

If the software enters a deadlock, the system may get blocked. The purpose of the
Watchdog Timer is to prevent this from happening [4]. For this purpose, a 12-bit counter
is used. The user chooses a value for this counter, the maximum value corresponding to
16 seconds, and the counter must be reset before it expires. Otherwise, a total or partial
reset of the MCU takes place.
As it is important to prevent any blockage of the system to happen, the Reinforced

Safety Watchdog Timer of the MCU is also used. Even if it shares the same features as
the WDT, the RSWDT is entirely independent of the WDT. In fact, its clock source is
automatically selected to be different from that of the WDT. Thus, if the WDT clock
source fails, the RSWDT performs the monitoring of the system. This provides maximum
safety regardless of the external operating conditions.
The last application requiring a flag in the user task is related to the two above-
mentioned Watchdog Timers of the MCU. That flag is simply linked to a timer interrupt
and is used to reset the two WDT. Finally, the Watchdog Timer and Reinforced Safety
Watchdog Timer parameters are the following:
• WDT counter value = 1536 which corresponds to 6 seconds;
50
• RSWDT counter value = 4095 which corresponds to 16 seconds;
• Booth timers are reset every 4 seconds.
51
Chapter 4
Hardware and Software testing
When making a new product, it is always important to make sure that it works prop-
erly. However, this is specially critical for a space application. Indeed, while it is not
uncommon to see cars called back to the garage for corrections, this is not feasible in
this case. If the CubeSat encounters a problem, it is impossible to solve it and the whole
mission is lost. The goal of this chapter is to verify that the OBC design discussed in the
previous chapters works perfectly.
To start, the development board conceived around the selected MCU will be detailed.
Then, the first batch of tests performed with this board to learn how to use it will be
described. After that, the PCB designed for testing purposes will be shown. Finally, the
components of the latter will be separated into groups according to their function. The
different groups will then be presented together with the tests performed within them.
4.1 Development board

As it has been explained in section 2.1.1, an Xplained Ultra evaluation kit is available
to perform tests on the ATSAMV71Q21 [28]. This evaluation board has been largely used
during this thesis, so it is interesting to detail some of its features. An overview of the
board is shown in Figure 4.1.1.
52
4.1. DEVELOPMENT BOARD Master thesis
Figure 4.1.1: SAM V71 Xplained Ultra Evaluation Kit Overview [28].
The evaluation board comprises a lot of hardware components, but only the most
important ones will be listed below:
• An ATSAMV71Q21 MCU;
• An embedded debugger (EDBG), used to program and debug the MCU;
• Two external crystal oscillators. A 32.768 kHz crystal for the slow clock signals and
a 12 MHz for the speed clock signals;
• Three mechanical buttons: one reset button and two configurable buttons.
• Two yellow LEDs that can be programmed by the user;
• An external IS42S16100E-7BLI, 512Kx16x2, 144MHz, SDRAM;
53
4.2. PCB COMPATIBLE WITH THE DEVELOPMENT BOARD Master thesis
• An SD card connector linked to the High Speed Multimedia Card Interface (HSMCI)
of the MCU;
• An external EEPROM connected to the I2C bus of the MCU;
• Arduino shield connectors on which the test PCB has been plugged.
Some of the above-mentioned components have been used to develop the software of
the OBC. Since the test PCB is based on them, they will be mentioned again in the
following section. But prior to that, the first tests performed using only the development
board should be presented.
To learn the basic features of the board, the first tests were carried out by following
online tutorials such as those presented by Microchip [23]. The first thing tested was to
turn on and off one of the LEDs by pressing one of the buttons. The next thing was to
add the RTOS in the previous application. Once that worked properly, several features
of the RTOS were explored.
The first RTOS feature studied was the development of an application using multi-
ple tasks. Then it was necessary to implement the communication between these tasks.
Additionally, tests with semaphores and timers were performed. Finally, the last key
functionality of RTOS that needed to be tested was related to interrupts.
It is also necessary to point out that while waiting for the reception of the test PCB,
experiments were carried out with an EEPROM connected to the development board via
a breadboard. That made it possible to carry out preliminary communication tests with
the I2C bus. This way, when the test PCB was received, the communication with this
bus could be implemented more quickly.
4.2 PCB compatible with the development board

A test PCB has been realized in order to develop and test the software of the OBC.
It has been conceived to be plugged into the development board. For that reason, it is
based on the Arduino Mega shape, as it is the case of the Arduino connectors of the
development board. The 3D view of this testing PCB is shown in Figure 4.2.1.
54
Figure 4.2.1: 3D view of the testing PCB that was plugged into the evaluation board.
The components are divided into different groups that have been highlighted with
colored polygons in Figure 4.2.1. Each group will now be detailed.
The red rectangle contains the components linked to the external ADC. Therefore,
it includes the MAX11128 [27] along with its required passive components. In addition,
there are a potentiometer and two test points. One of the test points is directly connected
to a channel of the MAX11128. It gives the opportunity to put any wanted external volt-
age on it to verify that the ADC result given by the MAX11128 is correct. The other test
point is connected to the potentiometer and to another channel of the MAX11128. The
potentiometer being itself connected to the 3.3V power source, its output is a fraction
of this voltage. This gives an easy way to monitor that the MAX11128 ADC results are
valid for different voltage values by just turning the potentiometer button and without
the need for an external power source. The MAX11128 was thus tested in different ways.
The blue polygon comprises the components related to FRAMs. This includes the
eight FM25V20A [14] with their passive components as well as the demultiplexer. The
first test performed with this group was to select the correct FRAM CS line at the output
of the demultiplexer. Indeed, as explained in section 2.2.1.2, the OBC manages simultane-
ously different CS lines with a demultiplexer. As this functionality was not implemented
by the SPI driver management codes generated by MPLAB, they needed to be adapted.
Some changes in these generated codes allowed the use of the demultiplexer for the se-
lection of the FRAM CS line. Then, the first real test with these memories was a simple
write of a text to a given address of a memory, followed by a read to the same address of
the same memory. Once this writing and reading of text were working perfectly, further
tests were carried out. The important function of FRAMs is to store and then read the
values obtained by other components, such as the MAX11128 or the TCA9555. The next
55
test was therefore logically the writing and reading of ADC results from the MAX11128
into the memories. When this second test was working, a last check was made with the
writing and reading of values coming from the TCA9555.
The orange rectangle contains the PCA9306 [29] and its passive components. This
device is used as a dual bidirectional voltage-level translator for the I2C bus. Indeed, the
I2C bus of the MCU has a voltage-level of 3.3V while the devices present in this PCB
and with which the MCU communicates via the I2C bus have a voltage-level of 5V. The
PCA9306 is consequently only used to enable other components to work. The components
in question belong to the two groups that will now be analyzed.
The yellow rectangle includes the AD5272 [30] digital rheostats along with its pas-
sive components and two test points. The purpose of that group is to make some I2C
communication with the MCU. Figure 4.2.2 shows the functional block diagram of the
AD5272. The two test points are connected to the A and W pins of the AD5272. This
block operates as follows: an input voltage is applied to one of the two test points and
thus to the A or W pin of the AD5272, while the other test point is used to measure the
output voltage of the AD5272. The output voltage will thus be a fraction of the input
voltage. This fraction depends on the resistance value chosen for the AD5272. This resis-
tance value is programmed through the I2C bus. Therefore, the tests performed consisted
in programming the digital rheostats and checking that the output voltage was correct,
given this chosen resistance value and the applied input voltage.
Figure 4.2.2: Functional block diagram of the AD5272 [30].
The green rectangle comprises the TCA9555 [26], its passive components, two LEDs,
and two switches. This block involved two kinds of communications through the I2C bus.
The first one was the writing of a value to the TCA9555 pins connected to the LEDs. In
this case, the MCU was thus the sender and the TCA9555 the receiver. The first thing to
do in order to reach that goal was to define the pins connected to the LEDs as outputs.
56
When the direction of the pins was correctly defined, it was necessary to put a "1" value
in the bits corresponding to the two LEDs pins. Once the pins were configured and set
as described, the two LEDs turned on. Some more tests were performed in order to turn
only one of the LEDs on. The second type of communication was a reading of the values
of the two pins connected to the switches. Here, the TCA9555 is the sender and the MCU
is the receiver. The methodology was close to that of the first type of communication. In-
deed, the pins were configured as input, which is the case by default, and then the value of
those pins was read. The read value was then displayed on the terminal debugger to check
if it was in accord with the switches positions. The tests have been performed with the
switches in all possible configurations in order to be sure that everything was working well.
The two purple circles correspond to test points directly connected to pins of the con-
nectors. They were used as a power source for some tests. Indeed, a simple bit set was
sufficient to obtain a 3.3V voltage at those two test points. It was then only necessary to
connect these points to the desired location in the circuit. For example, at one of the test
points of the variable resistors.
Finally, it is worth noting that the connectors are represented as female connectors
while in reality male connectors were soldered to the PCB in order to be compatible with
the female connectors of the development board. This is simply because only the CAD
models of female connectors were found online, but as their footprints are the same as
the ones of the male connectors, it is not an issue.
57
Chapter 5
Conclusion
This project has lead to significant progress in the development of the on-board com-
puter of the CubeSat being developed by the University. As far as the hardware is
concerned, the choice of the microcontroller and its external components was made. The
MCU was chosen for its excellent general performance combined with the fact that it
is available in different versions. Indeed, it is a huge advantage to be able to carry out
all the development of the OBC with a standard COTS version and simply switch to a
radiation-tolerant version when sending it into space. Beyond the choice of the MCU and
its external components, the different memories of the OBC were also chosen. This choice
took into consideration the harsh space environment as well as the necessary storage ca-
pacities and the time spent by data in the memories. Due to the current absence of a
payload, it was decided not to make a definitive choice concerning the two SD cards. A
first study has been carried out and their location on the PCB is already defined. Only the
model that will be the most suitable for the payload, once this one has been determined,
remains to be chosen based on the results obtained in this work. A power control system
has also been set up. Its objective is twofold. Firstly, it is used to protect the downstream
circuits from overvoltage, undervoltage and overcurrent. Secondly, it is used to evaluate
the total power consumed by the on-board computer. In addition to the choice of the
components, a PCB has been designed. This PCB has been developed so as to leave some
space for the possible addition of new components during the future development of this
project. Indeed, once the payload will be established, it might be necessary to add some
components to the OBC.
In addition to the choice of the components and the realization of the PCB, codes
allowing the OBC to carry out some functions have also been developed. These ones are
based on an RTOS. This architecture has been chosen because it is the most widespread
architecture in the space domain. Moreover, given the current absence of payloads, it was
necessary to make sure that future developments would not require modifying the entire
code. Using an RTOS prevents this from happening. This software was made using the
MPLAB X IDE. This program makes it very practical to develop applications around
the chosen microcontroller. Indeed, it provides many pre implemented modules such as
FreeRTOS, an open-source RTOS. Codes enabling communication with the FRAMs lo-
cated on the OBC as well as with several sensors contained on the EPS board have been
implemented. Finally, a code to demonstrate the functioning of the above-mentioned
codes has also been implemented to simplify future works related to this thesis. This
code also handles some security aspects such as the WDT that is used to ensure that the
58
Master thesis
program does not get stuck in a deadlock.
A series of tests were also carried out to ensure the proper functioning of the codes
implemented for the OBC. In order to perform these tests, the development board de-
signed for the chosen MCU was used. A test PCB created to be compatible with this
development board was created for further testing. These tests verified that everything
was working as it should.
For the further development of the on-board computer, it will first be necessary to
know the payload included in the CubeSat. This will allow to make the final choices of
components and to complete the OBC PCB. After that, the OBC software will have to
be developed further so that it can perform all the required tasks. The last step will
be to replace the standard MCU with the radiation-tolerant version before sending the
CubeSat into space. It could also be interesting to include some modern features in the
CubeSat. Indeed, technologies such as artificial intelligence and machine learning are
increasingly used in CubeSat. For example, ESA has worked on a nanosatellite contain-
ing artificial intelligence techniques to send back to earth only the interesting images that
have been pre-processed in the satellite. This avoids sending many useless images to earth.
To conclude, this work has been a huge opportunity for me. The space domain is a
very interesting domain but quite difficult to access. I am very happy to have had the
opportunity to already gain a first experience in this field. Furthermore, this work allowed
me to familiarize myself with the Altium Designer software as well as with RTOS-based
systems.
59
Appendices
60
1 2 3 4
A
SDRAM A
COU10A
COU10B
U10A NLD0NLD1NLD2NLD3NLD4NLD5NLD6NLD7NLD8NLD9NLD10NLD11NLD12NLD13NLD14NLD15
D11
D13
D15
D3
D10
D12
D14
D5
D7
D8
D0
D1
D2
D4
D6
D9
Appendix A
NLA0
A0 23
PIU10023
2
PIU1002
NLA1 A0 DQ0
A1 24
PIU10024
4
PIU1004
NLA2 A1 DQ1
A2 25
PIU10025
5
PIU1005
B NLA3 A2 DQ2 B
A3 26
PIU10026
7
PIU1007
NLA4 A3 DQ3
A4 29
PIU10029
8
PIU1008
NLA5 A4 DQ4
A5 30
PIU10030
10
PIU10010
NLA6 A5 DQ5
A6 31
PIU10031
11
PIU10011
NLA7 A6 DQ6
A7 32
PIU10032
13
PIU10013
NLA8 A7 DQ7
A8 33
PIU10033
42
PIU10042
NLA9 A8 DQ8
A9 34
PIU10034
44
PIU10044
NLA10 A9 DQ9
A10 22
PIU10022
45
PIU10045
NLA11 A10 DQ10

A11 35
PIU10035
47
PIU10047
NLA12 A11 DQ11
A12 36
PIU10036
48
PIU10048
A12 DQ12
50
PIU10050
DQ13
51
PIU10051
DQ14
NLBA0
BA0 20
PIU10020
53
PIU10053
BA0 DQ15
Final PCB Schematics
NLBA1
BA1 21
PIU10021 BA1 NLDQML
15
PIU10015
DQML
DQML NLDQMH
39
PIU10039
DQMH
DQMH
NLSDCK
SDCK 38
PIU10038
CLK
NLSDCKE
SDCKE 37
PIU10037
C CKE C
NLSDWE
SDWE 16
PIU10016
NLCAS WE#
CAS 17
PIU10017
NLRAS CAS#
RAS 18
PIU10018
NLSDCS RAS#
SDCS 19
PIU10019
40
PIU10040
CS# NC
MT48LC16M16A2P-6A:G
+3.3V
U10B
3
PIU1003
6
PIU1006
PIC160 PIC1701 PIC1801 PIC1901 PIC20 1 PIC210 PIC2 01 PIC2301 9
VDDQ VSSQ
12
COC16
C16 COC17
C17 COC18
C18 COC19
C19 COC20
C20 COC21
C21 COC22
C22 COC23
C23 PIU1009 VDDQ VSSQ PIU10012
2.2uF 100n 100n 100n 100n 100n 100n 100n 43

PIU10043 VDDQ
46
PIU10046
PIC1602 PIC1702 PIC1802 PIC1902 PIC20 2 PIC2102 PIC2 02 PIC2302 VSSQ
49
PIU10049
52
PIU10052
D VDDQ VSSQ D
1
PIU1001 VDD
28
PIU10028
VSS
14
PIU10014 VDD
41
PIU10041
VSS
27
PIU10027 VDD
54
PIU10054
GND GND GND GND GND GND GND GND VSS
MT48LC16M16A2P-6A:G
GND
1 2 3 4
1 2 3 4
FRAM
A A
+3.3V +3.3V +3.3V

+3.3V +3.3V +3.3V
PIR602 PIR402 PIR502

COR6
R6 PIC10 2 COR4
R4 PIC802 COR5
R5 PIC902
COC10
C10 10k COC8
C8 10k COC9
C9
10k COU1
U1 PIC801 100nF COU2
U2 PIC901 100nF
COU3
U3 PIC10 1 100nF
NLCS0M1 8 NLCS0M4
CS_M4 1
PIR401 8
PIU108 NLCS0M7
CS_M7 PIR5011 8
PIU208
CS_M1 1
PIR601 PIU308 PIU101 Vdd PIU201 Vdd
PIU301 Vdd CS CS
CS 6 6
SPI0_SCK 6 SPI0_SCK PIU106 PIU206
PIU306 SCK GND SPI0_SCK SCK GND
SCK GND 5 2
PIU102 5 2
PIU202
SPI0_MOSI 5 2
PIU302 SO SO
PIU305
PIU205 SI
SI SO NLSPI00MISO
SPI0_MISO SPI0_MOSI PIU105 SI SPI0_MISO SPI0_MOSI SPI0_MISO
7 7
PIU107 4 7
PIU207 4
PIU307 4 +3.3V HOLD PIU104 +3.3V HOLD PIU204
+3.3V HOLD PIU304 Vss Vss
Vss 3 3
3 PIU103 PIU203
PIU303 WP WP
WP
GND FM25 GND FM25 GND
FM25
B B
+3.3V +3.3V +3.3V

+3.3V +3.3V +3.3V
PIR702 PIC1 02 PIR902 PIR802

COR7
R7 COR9
R9 PIC1302 COR8
R8 PIC120
10k
COC11
C11 COC13
C13 COC12
C12
COU4 10k 10k
U4 PIC1 01 100nF COU6
U6 COU5
U5 PIC1201 100nF
PIC1301 100nF
NLCS0M2
CS_M2 PIR701 1 8
PIU408 8 NLCS0M8
CS_M8 PIR8011 8
PIU508
PIU401 Vdd NLCS0M5
CS_M5 PIR901 1 PIU608 PIU501 Vdd
CS PIU601 Vdd CS
6 CS
NLSPI00SCK
SPI0_SCK PIU406 6 6 PIU506
SCK GND SPI0_SCK PIU606 SCK SPI0_SCK SCK GND
NLSPI00MOSI 5 2 2 GND 5 2
SPI0_MOSI PIU405 5 PIU602 PIU505 SO PIU502
SI PIU605
SO PIU402 SPI0_MISO SO SI
SPI0_MOSI SI SPI0_MOSI SPI0_MISO
SPI0_MISO
7
PIU407 4 7 7
PIU507 4
+3.3V HOLD PIU404 PIU607 4 +3.3V HOLD PIU504
Vss +3.3V HOLD Vss PIU604 Vss
3
PIU403 WP 3 3
PIU503
PIU603 WP WP
FM25 GND GND FM25 GND

C FM25 C
+3.3V +3.3V
+3.3V +3.3V
PIR10 2 GND
COR10 PIC1402 PIR1 02 COU7
U7
R10 COR11
R11 PIC1502
10k
COC14
C14 COC15
C15 4 PIU704
15 CS_M1
PIU7015
10k E1 Y0
COU8
U8 PIC1401 100nF COU9
U9 PIC1501 100nF 5 PIU705
14 CS_M2
PIU7014
NLE30FRAM E2 Y1
NLCS0M3 PIR10 1 8 NLCS0M6 8 E3_FRAM 6
PIU706
13 CS_M3
PIU7013
CS_M3 1
PIU801 PIU808 CS_M6 PIR1 01 1 PIU908 E3 Y2
CS Vdd CS PIU901 Vdd 12 CS_M4
PIU7012
SPI0_SCK 6
PIU806
6 PIU906 NLCS0FRAM0 Y3
SCK GND SPI0_SCK SCK GND CS_FRAM0 1 PIU701
11 CS_M5
PIU7011
SPI0_MOSI 5 2
PIU802 5 2
PIU902
A0 Y4
PIU805 SI SO PIU905 SI SO NLCS0FRAM1
CS_FRAM1 2
PIU702
10 CS_M6
PIU7010
SPI0_MISO SPI0_MOSI SPI0_MISO NLCS0FRAM2 A1 Y5
CS_FRAM2 3
PIU703
9 CS_M7
PIU709
A2 Y6
7 CS_M8
PIU707
7
PIU807 4 7
PIU907 4 Y7
+3.3V HOLD Vss PIU804 +3.3V HOLD Vss PIU904
3 3
PIU903 16 8
PIU7016 PIU708
PIU803 WP
WP +3.3V VCC GND
D FM25 GND FM25 GND CD74HC138M D
GND
1 2 3 4
1 2 3 4 5 6 7 8
SAMV71Q21
A A
VDDCORE COL1 VDDOUT

L1
PIL102 PIL101
BLM18PG471SN1 PIC10
+3.3V PIC201 PIC301 + COC1
C1
COC2
C2 COL2
L2 COC3
C3
PIL202 PIL201
2.2uF
PIC20 100n PIC302 100n
PIC401 BLM18PG471SN1 PIC102
GND COC4
C4
PIC501 PIC402 100n GND GND
COC5
C5
10uF NLVD PL NLVD UTMIC
VDDPLL
VDDUTMIC
PIC502 GND
+3.3V
GND
5
134
143
72
96
80
43
30
81
107
50
33
29
123
139
3
PIC105 PIC1034 PIC1043 PIC1072 PIC1096 PIC108 PIC1043 PIC103 PIC108 PIC107 PIC105 PIC103 PIC1029 PIC1023 PIC1039 PIC103 COIC1
IC1
2
SAMV71Q21B
2
PIR102 COR1
PIR20 R1 NLBA1
BA1
102 PIIC10102
1 PIIC101
COR2
R2 4.7k PA00 PD00
99
PIIC1099
132
PA01 PD01 PIIC10132
VDDIN
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
4.7k 93
PIIC1093
131
VDDPLL
VDDOUT
PA02 PD02 PIIC10131
NLSDA0303V
SDA_3.3V
PIR10 91 128
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
1
PIIC1091 PIIC10128
VDDUTMII
PA03 PD03
VDDUTMIC
NLSCL0303V
VDDPLLUSB
PIR201 SCL_3.3V 77 126
1
PIIC1077
PA04 PD04 PIIC10126
73
PIIC1073
125
PA05 PD05 PIIC10125
114
PIIC10114
121
PIIC10121
PA06 PD06
NLXIN32
XIN32 35 119
POXIN32
XIN32 NLXOUT32 PIIC1035
XOUT32 PIIC1036 36
PA07 PD07 PIIC10119
113
POXOUT32
XOUT32 NLURXD PA08 PD08 PIIC10113
URXD PIIC1075 75 110
PIIC10110
NLUTXD PA09 PD09
UTXD PIIC1066 66 101
PA10 PD10 PIIC10101 NLINT0I2C0EXP
B 64
PIIC1064
98 INT_I2C_EXP B
PA11 PD11 PIIC1098 NLCS0FRAM0
68
PIIC1068
92 CS_FRAM0
PA12 PD12 PIIC1092
42
PIIC1042
88
PA13 PD13 PIIC1088
51
PIIC1051
84 NLSDCKE
SDCKE
NLD14 PA14 PD14 PIIC1084 NLDQMH
49
D14 PIIC1049 106 DQMH
PA15 PD15 PIIC10106 NLRAS
D15 45
NLD15 PIIC1045 78
PIIC1078
RAS
NLPower0303V PA16 PD16 NLCAS
Power_3.3V 25
PIIC1025
74 CAS
PA17 PD17 PIIC1074
24
PIIC1024
69 NLSD10DETECT
SD1_DETECT
PA18 PD18 PIIC1069 NLSD20DETECT
23
PIIC1023
67
PIIC1067
SD2_DETECT
PA19 PD19
NLBA0 22
BA0 PIIC1022
PA20
65
PD20 PIIC1065
NLSPI00MISO
SPI0_MISO
32
PIIC1032
63 NLSPI00MOSI
SPI0_MOSI
PA21 PD21 PIIC1063 NLSPI00SCK
37
PIIC1037
60
PIIC1060
SPI0_SCK
PA22 PD22 NLSDCK
46
PIIC1046
57 SDCK
PA23 PD23 PIIC1057
56
PIIC1056
55
PA24 PD24 PIIC1055
59
PIIC1059
52
PIIC1052
NLCS0FRAM1
CS_FRAM1
PA25 PD25 NLE30FRAM
62
PIIC1062
53 E3_FRAM
PA26 PD26 PIIC1053 NLCS0FRAM2
70 PIIC1070
47 PIIC1047
CS_FRAM2
PA27 PD27
112
PIIC10112
71
PIIC1071
PA28 PD28
129
PIIC10129
108 NLSDWE
SDWE
PA29 PD29 PIIC10108
116
PIIC10116
34
PA30 PD30 PIIC1034
118
PIIC10118
2
PIIC102
PA31 PD31
NLD0
D0 11
PIIC1011
4 NLD8
D8
NLD1 PC00 PE00 PIIC104 NLD9
D1 38
PIIC1038
6 D9
D2 39
PIIC1039
7 D10
D3 40
PIIC1040
10 D11
D4 41
PIIC1041
27 D12
PC04 PE04 PIIC1027
NLD5
D5 58
PIIC1058
PC05 PE05
28 PIIC1028
NLD13
D13
C NLD6
D6 54
PIIC1054
C
NLD7 PC06 NLCS0MEM0
D7 48
PIIC1048
21 CS_MEM0
PC07 PB00 PIIC1021 NLCS0MEM1
82
PIIC1082
20 CS_MEM1
PC08 PB01 PIIC1020 NLCS0MEM2
86
PIIC1086
26 CS_MEM2
PC09 PB02 PIIC1026 NLE30MEM
90
PIIC1090
31 E3_MEM
PC10 PB03 PIIC1031
94
PIIC1094
105
PIIC10105
PC11 PB04
17
PIIC1017
109 PIIC10109
PC12 PB05 NLSWDIO
19
PIIC1019
79 SWDIO
PC13 PB06 PIIC1079 NLSWCLK
97
PIIC1097
89
PIIC1089
SWCLK
PC14 PB07 NLXOUT
SDCS 18
NLSDCS PIIC1018 141 XOUT
PC15 PB08 PIIC10141 XOUT
100
PIIC10100 PC16
142
PB09 PIIC10142
NLXIN POXOUT
XIN POXIN
XIN
103
PIIC10103
87
PIIC1087
NLDQML PC17 PB12
DQML 111
PIIC10111
144
NLA0 PC18 PB13 PIIC10144
117
A0 PIIC10117
NLA1 PC19
120
A1 PIIC10120 137
PIIC10137
NLA2 PC20 HSDP
122
A2 PIIC10122 136
PIIC10136
NLA3 PC21 HSDM
124
A3 PIIC10124
PC22
NLA4 127
A4 PIIC10127
PC23 NRST
83
PIIC1083
NLTARGET0RESET
TARGET_RESET
NLA5 130
A5 PIIC10130 85
PIIC1085
NLA6 PC24 TST
133
A6 PIIC10133 104
PIIC10104
NLA7 PC25 JTAGSEL
A7 PIIC1013 13
PC26
NLA8
A8 PIIC1012 12
PC27
NLA9
A9 PIIC1076 76 9
PIIC109
NLADVREF
ADVREF GND
NLA10 PC28 ADVREFP
A10 PIIC101616 8
PIIC108
NLA11 PC29 ADVREFN COC6
A11 PIIC101515 C6
NLA12 PC30
A12 PIIC101414 PIC602 PIC601
PC31
140
PIIC10140
GND
GND
GND
GND
GND
GND
VBG
100n PIL302
D GND D
COL3
L3
61
44
95
115
138
135
PIC104 PIC106 PIC1095 PIC105 PIC1038 PIC1035 BLM18PG471SN1

PIR302
GND PIC701 COC7
C7 PIL301
COR3
R3
5.62k
PIC702 10p +3.3V

PIR301
GND
1 2 3 4 5 6 7 8
1 2 3 4
NAND + SD
A A
+3.3V
+3.3V COU11
U11
PIR120 PIR1302 +3.3V 8 6 SPI0_SCK
PIU1108 VCC SCK PIU1106
COR12
R12 COR13
R13
2
PIC2401 5 SPI0_MOSI
PIU1105
47k 47k COCD1 PIR1402 COC24
C24 SI/IO0
PIR1502 CD1 2 SPI0_MISO
PIU1102
COR14
R14 PIC2402 100n SO/IO1
COR15
R15 PIR1201 PIR1301 3
PIU1103
10k WP/IO2 +3.3V
47k DAT2
PICD101
7
PIU1107
CD/
HOLD/IO3
PIR1602 PIR1702 PIR1501 NLCS0SD2
CS_SD2 DAT3
PICD102 SD CARD 1 NLCS0NAND1
CS_NAND1
PIU1101
PIR1401 CS
1
COR16
R16 COR17
R17 NLSPI00MOSI
SPI0_MOSI CMD PICD103
DET NLSD20DETECT
PICD109
SD2_DETECT GND
47k 47k VDD
PICD104
SW
PICD1010
4
PIU1104
VSS GND
1
1
PIR1601 PIR1701 NLSPI00SCK CLK
SPI0_SCK PICD105 SHLD
PICD1011
PIC2501 PIC2601 VSS PICD106
SHLD
PICD1013
MT29F2G01ABAGDWB-IT:G TR
COC25
C25 COC26
C26
DAT0
PICD107
SHLD
PICD1012
PIC2502 10µF PIC2602 100nF +3.3V COU12
U12
2
2
DAT1
PICD108
SHLD
PICD1014
8
PIU1208
6 SPI0_SCK
PIU1206
VCC SCK
502774-0891 PIC2701 5 SPI0_MOSI
PIU1205
COC27
C27 SI/IO0
2 SPI0_MISO
PIU1202
100n SO/IO1
B PIC2702 WP/IO2
3
PIU1203
+3.3V B
GND NLSPI00MISO GND 7
SPI0_MISO HOLD/IO3 PIU1207
1 NLCS0NAND2
CS_NAND2
PIU1201
CS
GND
4
PIU1204
VSS GND
MT29F2G01ABAGDWB-IT:G TR
+3.3V COU13
U13
8
PIU1308
6 SPI0_SCK
PIU1306
VCC SCK
PI C2801 5 SPI0_MOSI
PIU1305
COC28
C28 SI/IO0
2 SPI0_MISO
PIU1302
100n SO/IO1
PIC2802 3
PIU1303
WP/IO2 +3.3V
7
PIU1307
HOLD/IO3
1 NLCS0NAND3
PIU1301
CS_NAND3
+3.3V CS
GND
4
PIU1304
VSS GND
PIR1802 PIR1902 +3.3V
COR18 COR19
R18 R19 MT29F2G01ABAGDWB-IT:G TR
2
C 47k 47k COCD2
CD2 PIR20 2 C
PIR210 PIR1801 PIR1901 COR20
R20
COR21
R21 10k
47k DAT2
PICD201
NLCS0SD1 CD/
PIR210 CS_SD1 DAT3
PICD202 SD CARD GND
PIR2 02 PIR2302 PIR20 1
1
COR22
R22 COR23
R23 CMD
SPI0_MOSI PICD203 DET NLSD10DETECT
PICD209
SD1_DETECT COU14
U14
47k 47k VDD PICD204
SW
PICD2010
4 PIU1404
15
PIU14015
CS_SD1
E1 Y0
1
1
PIR2 01 PIR2301 SPI0_SCK CLK PICD205
SHLD
PICD2011
5 PIU1405
14
PIU14014
CS_SD2
PIC2901 PIC30 1 NLE30MEM E2 Y1
VSS
PICD206
SHLD
PICD2013
6
E3_MEMPIU1406 13 CS_NAND1
PIU14013
COC29
C29 COC30
C30 E3 Y2
DAT0
PICD207
SHLD
PICD2012
12 CS_NAND2
PIU14012
PIC290 10µF PIC30 2 100nF Y3
2
2
DAT1
PICD208 SHLD
PICD2014
NLCS0MEM0
CS_MEM0 1 PIU1401 A0 Y4
11 CS_NAND3
PIU14011
NLCS0MEM1
CS_MEM1 2
PIU1402
10
PIU14010
NLCS0MEM2 A1 Y5
502774-0891 CS_MEM2 3 PIU1403
9
PIU1409
A2 Y6
7
PIU1407
Y7
GND GND
SPI0_MISO 16
PIU14016
8
PIU1408
+3.3V VCC GND
CD74HC138M
GND
D D
1 2 3 4
1 2 3 4
CRYSTALS + CONNECTORS
A A
32.768 kHz Crystal 12 MHz Crystal

32.768kHz +/-20PPM 7pF SMD
COXC1
XC1 COXC2
XC2
POXOUT32
XOUT32
NLXOUT32
XOUT32 PIJ102 PIJ101 PIXC101 PIXC102
NLXIN32
XIN32 POXIN32
XIN32 POXOUT
XOUT
NLXOUT
XOUT PIJ202 PIJ201
3
PIXC203
1
PIXC201
NLXIN
XIN POXIN
XIN
COJ1 COJ2 4
PIXC204
2
PIXC202
J1 PIXC103 J2
PIC310 PIC3201 PIC3 01 12.00MHz PIC3401
COC31
C31 COC32
C32 COC33
C33 COC34
C34
PIC3102 4.7p PIC320 4.7p PIC3 02 12p PIC3402 12p
B GND B
GND GND GND GND SMD-STRAP_0603_CLOSED GND
C C
EPS_3.3V
GND
NLSDA03 VNLSC 03 VNLIT02CEXP NLSPI0MSONLPI0MOSINLSPI0SCK NLTARGE0ST
SDA_3.3V
SCL_3.3V
INT_I2C_EXP
SPI0_MISO
SPI0_MOSI
SPI0_SCK
TARGET_RESET
PIR2402
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
COR24
R24 PIJ40A1 PIJ40A2 PIJ40A3 PIJ40A PIJ40A5 PIJ40A6 PIJ40A7 PIJ40A8 PIJ40A9 PIJ40A1 PIJ40A1 PIJ40A12 PIJ40A13 PIJ40A1 PIJ40A15 PIJ40A16 PIJ40A17 PIJ40A18 PIJ40A19 PIJ40A2 PIJ40A21 PIJ40A2 PIJ40A23 PIJ40A2 PIJ40A25 PIJ40A26 PIJ40A27 PIJ40A28 PIJ40A29 PIJ40A3 PIJ40B1 PIJ40B2 PIJ40B3 PIJ40B PIJ40B5 PIJ40B6 PIJ40B7 PIJ40B8 PIJ40B9 PIJ40B1 PIJ40B1 PIJ40B12 PIJ40B13 PIJ40B1 PIJ40B15 PIJ40B16 PIJ40B17 PIJ40B18 PIJ40B19 PIJ40B2 PIJ40B21 PIJ40B2 PIJ40B23 PIJ40B2 PIJ40B25 PIJ40B26 PIJ40B27 PIJ40B28 PIJ40B29 PIJ40B3
+3.3V 51k J3
1 COJ3 COJ4
J4
PIJ301
PIR2401 2
PIJ302
ESQT-130-02-G-Q-368
3
PIJ303
NLSWDIO 4
SWDIO PIJ304
D NLSWCLK 5
SWCLK PIJ305 D
C1
C3
C5
C8
D1
C2
C4
C6
C7
C9
D3
6
D2
D4
D5
D6
D7
D8
D9
GND PIJ306
PIJ40C1 PIJ40C2 PIJ40C3 PIJ40C PIJ40C5 PIJ40C6 PIJ40C7 PIJ40C8 PIJ40C9 PIJ40C1 PIJ40C1 PIJ40C12 PIJ40C13 PIJ40C1 PIJ40C15 PIJ40C16 PIJ40C17 PIJ40C18 PIJ40C19 PIJ40C2 PIJ40C21 PIJ40C2 PIJ40C23 PIJ40C2 PIJ40C25 PIJ40C26 PIJ40C27 PIJ40C28 PIJ40C29 PIJ40C3 PIJ40D1 PIJ40D2 PIJ40D3 PIJ40D PIJ40D5 PIJ40D6 PIJ40D7 PIJ40D8 PIJ40D9 PIJ40D1 PIJ40D1 PIJ40D12 PIJ40D13 PIJ40D1 PIJ40D15 PIJ40D16 PIJ40D17 PIJ40D18 PIJ40D19 PIJ40D2 PIJ40D21 PIJ40D2 PIJ40D23 PIJ40D2 PIJ40D25 PIJ40D26 PIJ40D27 PIJ40D28 PIJ40D29 PIJ40D3
C11
C21
C23
C12
C15
C16
C17
C18
C19
C22
C25
C26
C27
C28
C29
D11
D21
C10
C20
C24
C30
D13
D15
D18
D23
D25
D28
D10
D12
D14
D16
D17
D19
D20
D22
D24
D26
D27
D29
D30
555165-1
NLUTXDNLURXD
UTXD C13
URXD C14
GND
1 2 3 4
1 2 3 4
POWER
A A
+3.3V VDDCORE
PIC3502 PIC3602 PIC3702 PIC3802 PIC3902 PIC40 2 PIC4102 PIC420 PIC4302 PIC4 02 PIC4502 PIC4602 PIC4702
COC35
C35 COC36
C36 COC37
C37 COC38
C38 COC39
C39 COC40
C40 COC41
C41 COC42
C42 COC43
C43 COC44
C44 COC45
C45 COC46
C46 COC47
C47
PIC3501 100nF PIC3601 100nF PIC3701 100nF PIC3801 100nF PIC3901 100nF PIC40 1 100nF PIC410 100nF PIC4201 100nF PIC4301 100nF PIC4 01 100nF PIC4501 100nF PIC4601 100nF PIC4701 100nF
GND GND
COIC2
IC2 IN_3.3V
1
PIIC201
8
PIIC208
SOURCE1 DRAIN1_2
B 2
PIIC202 GATE1
7
PIIC207
B
COR25
R25 NLGate DRAIN1_1
PIR2501 PIR2502
Gate 3
PIIC203 SOURCE2
6
PIIC206
DRAIN2_2
PIC4802 22k 4
PIIC204
5
PIIC205
NLR0Sense
R_Sense
COC48
C48 GATE2 DRAIN2_1
PIC4801 3.3nF FDS3992
COJ5
J5
U.FL-R-SMT-1(10) GND
SIG
GND
GND
1
3
2
PIJ503 PIJ502 PIJ501 COU15
U15
Gate 10
PIU15010
9
PIU1509
R_Sense
GATE SENSE
EPS_3.3V IN_3.3V IN_3.3V PIR260
COR32
R32 1 8 COR26
R26
PIR3201 PIR3202 PIU1501 VIN VOUT PIU1508
PIR2702 6
PIU1506
7 100m +3.3V
20mOhm COR27 SHDN* FAULT* PIU1507
R27 2
PIU1502
PIR2601
PIU1605 PIU1604 200k UV
2
3
PIU1503
4
PIU1504
COR33
R33 OV RETRY
C PIU1603
PIR3302 PIR3301
NLPower0303V
Power_3.3V PIR2701 PIC4902 COC49
C49 C
OUT 5
RS-
100k PIC4901 220nF
RS+
PIU1505 GND
1
PIU1602
PIC50 1 COC50 PIR2802 11
PIU15011
GND C50 COR28
R28 EP(GND)
PIU1601
GND 1.3M GND
PIC50 2 1µF
COU16
U16 PIR2801 3V UV LTC4368CDD-1
MAX9938
GND PIR2902
GND COR29
R29
51k
PIR2901
3.6V OV
PIR30 2
COR30
R30
240k
PIR30 1
PIR3102
COR31
R31
10k
D PIR310 D
GND
1 2 3 4
1 2 3 4
A A
ADC + I2C BUS EXPANDER
+5V
+5V
+5V
2
P IR18
R1 9 02 PIR1802 COR18
COU10
U10
2
R19 0402SCL_5V
PIR20 COR20 COR19 NLSCL05V 19
PIU10019
1
PIU1001
NLSW1
SW1
R20 0402 NLSDA05V SCL P00 NLSW2
SDA_5V 20
PIU10020
2
PIU1002
SW2
0402 SDA P01 NLP02
3 P02
1
P02 PIU1003
P IR 1 80 18 4 NLP03
P03
1
PIU10018 PIU1004
A0 P03
Appendix B
COU9
U9 23
PIU10023
5
PIU1005
NLP04
P04
1
1
A1 P04 NLP05
17
PIU9017
24
PIU10024
6
PIU1006
P05
1
1
1
VDD +3.3V R21 A2 P05 NLP06
PIR201 PPIIRR129001 PIR210 COR21
18 PIC901 PIC10 1 7 P06
1
VDD PIU9018 COR22 P06 PIU1007
B 23 COC9
C9 COC10
C10 R22 0402 8 NLP07
P07 B
PIU9023 PIU1008
NLAN14 OVDD 10µF 100nF
PIR2301 COR23
R23 0402 P07
AN14 12 PIU9012
PIC902 PIC10 2
2
2
COTP1
TP1 NLAN0AN0 26
CNVST/AIN14
24 NLMISO
MISO 0402 NLLED1
10 LED1
PITP101 PIU9026 PIU9024 PIU10010
2
NLAN1 AIN0 DOUT PIR210 P10 NLLED2
27
PIU9027
11 LED2
PIU10011
2
5019 AN1 AIN1 P11
NLAN2
AN2 28
PIU9028
GND P I R 2 0 12 NLP12
P12
2
PIU10012
2
NLAN3 AIN2 PIR230 +5V P12 NLP13
AN3 1
PIU901
PIR120 13
PIU10013
P13
AIN3 COR12
R12 P13 NLP14
AN4
NLAN4 PIU9022 GND 14
PIU10014
P14
NLAN5 AIN4 10k P14 NLP15
AN5 3
PIU903
GND 15
PIU10015
P15
NLAN6 AIN5 P15 NLP16
AN6 4 PIU904
GND 16
PIU10016
P16
NLAN7 AIN6 NLINT P16 NLP17
AN7 5 INT PIR1201 22 17 P17
1
PIU905 AIN7 PIU10022 INT P17 PIU10017
NLAN8
AN8 6
PIU906 AIN8
AN9
NLAN9 PIU9077 25
PIU10025
AIN9 EP
Test PCB Schematics
AN10 8
NLAN10 PIU908 21
PIU10021
9
PIU1009
NLAN11 AIN10 +5V VCC GND
AN11 9 PIU909
+3.3V
AIN11
AN12 10
NLAN12 PIU9010 TCA9555RTWR
1
AIN12
AN13 11
NLAN13 PIU9011 PIR1 01 PIC1201
MOSI 21
NLMOSI PIU9021 AIN13 COTP2
TP2 AN1 COR11
R11 COC12
C12 GND
PITP201 PIR1102
DIN 3266W-1-104LF 100nF
13
PIU9013
PIC120
2
REF-/AIN15 5019
SPI_SCK 19
NLSPI0SCKPIU9019 PIR1 03
SCLK
C C
GND CS_ADC 20
NLCS0ADC PIU9020
CS
GND GND
NLEOC
EOC 25
PIU9025
EOC
+5V
15
1
+3.3V PIU9015 REF+
PIC1 01
2
2
COC11
C11 PIR902 COR9 PIR102 COR10
PIC1 02 470nF 29 R9 R10
PIU9029
2
EPAD 5.6k 5.6k
22
PIU9022
DGND
14
PIU9014
GND
GND 16 COU11
U11
1
1
GND PIU9016
NLSCL0303V 3
SCL_3.3VPIU1103
SCL1 SCL2
6 SCL_5V
PIU1106
PIR901 PIR10
MAX11128ATIT NLSDA0303V 4
SDA_3.3VPIU1104 5 SDA_5V
PIU1105
SDA1 SDA2
GND 8
PIU1108 EN
2
PIU1102
+3.3V VREF1
7
PIU1107
1
PIU1101
VREF2 GND
D PIR1302 D
COR13
R13 PCA9306DCURG4
200k GND
PIR1301
+5V
1 2 3 4
1 2 3 4
COJ1
J1
CONNECTORS NLSCL0303V
10 PA04 SCL_3.3V
PIJ1010
10 NLSDA0303V
9 PA03SDA_3.3V
PIJ109
COJ2 9 NLADVREF
J2 8
PIJ108
ADVREF
8
A 1
PIJ201
7
PIJ107
A
VBAT 1 7 NLSPI0SCK
2
PIJ202
6 PD22 SPI_SCK
PIJ106
NLTARGET0RESET +3.3V 2 6 NLMISO
TARGET_RESET 3
PIJ203
5 PD20
PIJ105
MISO
3 5 NLMOSI
4
PIJ204 4
PIJ104PD21 MOSI GND
+3.3V 4 4 NLCS1
5 3 PD25
PIJ103
CS1
+5V PIJ205 5 3 NLPC090LED
6
PIJ206
2
PIJ102
PC09_LED
6 2 NLCS2
7
PIJ207
1 PA05
PIJ101
CS2
7 1
8
PIJ208
Vin 8
SSQ-110-21-F-S
GND SSQ-108-21-F-S
COJ3
J3 COJ4
J4 GND
COTP3
TP3 COU12
PITP301
1
PD26PIJ301 8 PA02
PIJ408
U12
1 8 NLCS0M1
5019 2
PC31PIJ302 7 PC19
PIJ407
4
PIU1204
15 CS_M1
PIU12015
2 7 NLINT E1 Y0 NLCS0M2
B 3
PA19PIJ303 6 PD11 INT
PIJ406
5 14 CS_M2
PIU12014
B
3 6 NLCS0ADC
PIU1205 E2 Y1 NLCS0M3
4
PD30PIJ304 5 PD27 CS_ADC
PIJ405
6
PIU1206
13 CS_M3
PIU12013
4 5 +3.3V E3 Y2 NLCS0M4
5
PC13PIJ305 4 PA06
PIJ404
12 CS_M4
PIU12012
5 4 Y3 NLCS0M5
6
PE00PIJ306 3 PA00
PIJ403
1
CS0 PIU1201 11 CS_M5
PIU12011
6 3 A0 Y4 NLCS0M6
7
PE03PIJ307 2 PD30
PIJ402
2
CS1 PIU1202 10
PIU12010
CS_M6
7 2 A1 Y5 NLCS0M7
8
PE04PIJ308 1 PD28
PIJ401
3
CS2 PIU1203 9 CS_M7
PIU1209
8 1 A2 Y6 NLCS0M8
7 CS_M8
PIU1207
5 TARGET_RESET
3 PD22
1 PD20
PIJ50 PIJ503 PIJ501 Y7
SSQ-108-21-F-S SSQ-108-21-F-S
COJ5
J5 16 8
1
3
5
PIU12016 PIU1208
+3.3V VCC GND
HMTSW-103-23-F-D-237
CD74HC138M
6
4
2
GND
6
2
PIJ506 PIJ504 PIJ502
COJ6
J6 COJ7
J7
COTP4
TP4 1 8 PB01
PD21 4
PITP401
PD24PIJ601 PIJ708
1 8
5019 2
PA10PIJ602 7 PB00
PIJ707
2 7
3
PA22PIJ603 6 PD16
PIJ706
3 6
4
PE05PIJ604 5 PD15
PIJ705
4 +5V 5
C 5
PB13PIJ605 4 PD19
PIJ704
C
5 4
6
PD00PIJ606 3 PD18
PIJ703
6 3
7
PB03PIJ607 GND 2 PD27
PIJ702
7 2
8
PB02PIJ608 1 PD28
PIJ701
8 1
SSQ-108-21-F-S SSQ-108-21-F-S
+5V
GND
PC12
PA21
PA25
PB03
PD19
PB00
PA018
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
PIJ8035 PIJ803 PIJ8031 PIJ8029 PIJ8027 PIJ8025 PIJ8023 PIJ8021 PIJ8019 PIJ8017 PIJ8015 PIJ8013 PIJ801 PIJ809 PIJ807 PIJ805 PIJ803 PIJ801
COJ8
J8
1
3
5
9
7
31
21
11
33
23
13
35
25
15
29
27
19
17
SSQ-118-01-G-D
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
6
2
18
36
32
30
24
22
16
14
12
10
D PIJ8036 PIJ8034 PIJ8032 PIJ803 PIJ802 PIJ8026 PIJ8024 PIJ802 PIJ802 PIJ801 PIJ8016 PIJ8014 PIJ8012 PIJ801 PIJ80 PIJ806 PIJ804 PIJ802
PC14 34 D
PB04 28
PA24 26
PB02 20
PD18 8
PB01 4
NLCS0 NLEOC +5V

CS0
EOC
GND
1 2 3 4
1 2 3 4
FRAM
A +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V A
2
1
2
1
2
1
PIR102 PIC10 PIR20 PIC201 PIR302 PIC301

COR1
R1 COC1
C1 COR2
R2 COC2
C2 COR3
R3 COC3
C3
10k COU1
U1 PIC102 100nF 10k COU2
U3 PIC302 100nF
2
2
2
8
PIU108
8
PIU208
8
PIU308
NLCS0M1 VDD NLCS0M2 VDD NLCS0M3 VDD
CS_M1 1
PIR10 PIU101 CS_M2 1
PIR201 PIU201 CS_M3 1
PIR301 PIU301
1
1
1
CS CS CS
SPI_SCK 6 PIU106
GND SPI_SCK 6 PIU206
GND SPI_SCK 6 PIU306
GND
SCK SCK SCK
5
MOSIPIU105 2 MISO
PIU102
MOSI 5 2 MISO
PIU202
MOSI 5 2 MISO
PIU302
SI SO PIU205 SI SO PIU305 SI SO
7
PIU107
7
PIU207
7
PIU307
+3.3V HOLD +3.3V HOLD +3.3V HOLD
3
PIU103
3
PIU203
3
PIU303
+3.3V WP +3.3V WP +3.3V WP
4
PIU104
4
PIU204
4
PIU304
VSS VSS VSS
FM25V20A-DG FM25V20A-DG FM25V20A-DG
GND GND GND
B B
+3.3V +3.3V +3.3V +3.3V +3.3V +3.3V
2
1
2
1
2
1
PIR402 PIC401 PIR502 PIC501 PIR602 PIC601

COR4
R4 COC4
C4 COR5
R5 COC5
C5 COR6
R6 COC6
C6
10k COU4
U6 PIC602 100nF
2
2
2
8
PIU408
8
PIU508
8
PIU608
NLCS0M4 VDD NLCS0M5 VDD NLCS0M6 VDD
CS_M4 1 CS_M5 1 CS_M6 1
1
1
1
PIR401 PIU401 CS
PIR501 PIU501 CS
PIR601 PIU601 CS
SPI_SCK 6
PIU406
GND SPI_SCK 6
PIU506
GND SPI_SCK 6
PIU606
GND
SCK SCK SCK
5
MOSIPIU405 2 MISO
PIU402
MOSI 5
PIU505
2 MISO
PIU502
MOSI 5
PIU605
2 MISO
PIU602
SI SO SI SO SI SO
7
PIU407
7
PIU507
7
PIU607
+3.3V HOLD +3.3V HOLD +3.3V HOLD
3
PIU403
3
PIU503
3
PIU603
+3.3V WP +3.3V WP +3.3V WP
4
PIU404
4
PIU504
4
PIU604
VSS VSS VSS
C FM25V20A-DG FM25V20A-DG FM25V20A-DG C
GND GND GND
+3.3V +3.3V +3.3V +3.3V
2
1
2
1
PIR702 PIC701 PIR802 PIC801

COR7
R7 COC7
C7 COR8
R8 COC8
C8
10k COU7
U8 PIC802 100nF
2
2
8
PIU708
8
PIU808
NLCS0M7 VDD NLCS0M8 VDD
CS_M7 PIR701 PIU701
1 CS_M8 PIR801 1 PIU801
1
CS 1 CS
NLSPI0SCK
SPI_SCK 6
PIU706
GND SPI_SCK 6
PIU806
GND
NLMOSI SCK NLMISO SCK
MOSIPIU7055 2 MISO
PIU702
MOSI 5 2 MISO
PIU802
SI SO PIU805 SI SO
7
PIU707
7
PIU807
+3.3V HOLD +3.3V HOLD
3
PIU703
3
PIU803
+3.3V WP +3.3V WP
D D
4
PIU704
4
PIU804
VSS VSS
FM25V20A-DG FM25V20A-DG
GND GND
1 2 3 4
1 2 3 4
A
LEDs + SWITCHES + DIGITAL POTENTIOMETER A
NL ED1 NL ED2
LED1
LED2
1
1
+5V
PIR140 PIR150 PIC1301 PIC1401
2
COR14
R14 COR15
R15 PIR240 COR24 COC13
C13 COC14
C14 COU13
U13
500 500 R24 10µF COTP5
TP5
PIC1302 2
PIC140100nF 1
PIU1301
2
PIU1302 PITP501
2
2
0402 VDD A
B PIR1402 PIR1502 5019 B
NLSCL05V
SCL_5V 9 3
COTP6
TP6
PIU1309 PIU1303 PITP601
2
2
PID102 PID20 NLSDA05V SCL W COC15
GND 8
SDA_5V PIU1308 C15
1
COD1
D1 COD2
D2 PIR2401 SDA 5019
5 1
PIU1305
PIC1501
2
PIC1502
EXT CAP
10
PIU13010 ADDR 1µF
4
1
1
PIU1304
1
PID10 PID201 VSS
PIR2501 COR25 7
PIU1307
6
PIU1306
R25 RESET GND
0402 AD5272BRMZ-20
GND GND
2
PIR250
GND
C C
+5V
2
2
PIR1602 PIR1702
COR16
R16 COR17
R17
100k 100k
PIR160 PIR1701 COSW1

SW1
1
1
NLSW1
SW1 3
PISW103
2
PISW102
NLSW2
SW2 4
PISW104
1
PISW101
418117270902
GND
D D
1 2 3 4
Appendix C
Codes Git link
https://gitlab.uliege.be/A.Horbach/tfe
71
Bibliography
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Developers”
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SAMRH71 Datasheet. Rev.D. MICROCHIP TECHNOLOGY. May 2020.
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73

Development of An On-Board Computer For A Nanosatellite: Intelligent Robotics"

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Development of An On-Board Computer For A Nanosatellite: Intelligent Robotics"

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Development of an on-board computer for a nanosatellite

Auteur : Horbach, Amadis

Avertissement à l'attention des usagers :

Development of an on-board computer for

University of Liège - School of Engineering and Computer Science

Supervisor: Jean-Michel Redouté

Academic year 2020-2021

3.3.6 User task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4 Hardware and Software testing 52

A Final PCB Schematics 61

B Test PCB Schematics 67

C Codes Git link 71

1.1 Project’s presentation

1.2 CubeSat history and architecture

• Payload: it is the reason why the satellite is designed.

• Attitude Determination and Control System (ADCS): it controls the orien-

• Communication system: it handles the external communications of the CubeSat.

• Electrical Power System (EPS): it is responsible for the adequate distribution

• Antenna: it is used to send and receive CubeSat’s communications.

Figure 1.2.1: Representation of the different parts of a CubeSat.

1.2.3 On-Board Computer

1.3 Space conditions

Space conditions in LEO will now be explained in more detail.

components. These are known as Solar Particle Events (SPE).

Figure 1.3.1: Main sources of space radiation in LEO.

The two more common are:

• Single-Event Latchup (SEL): An ionizing particle from the radiation creates an

1.4 Power management

2.1 Choice of the microcontroller

(a) ATSAMV71Q21, the standard version (b) ATSAMV71Q21RT, the radiation-

(c) SAMRH71, the radiation-hardened version of the SAMV71

Figure 2.1.2: Block diagram of the ATSAMV71Q21 [4].

properties of the Cortex-M7 is the presence of a six-stage, in-order super-scalar pipeline

Tightly Coupled Memory (TCM) Interface

Figure 2.1.3: Flash Sector Organization [4].

The Two-wire Interface

Serial Peripheral Interfaces

Analog Front-End Controllers

Three Universal Synchronous Asynchronous Receiver Transceiver (USART) and five

Figure 2.1.4: Representation of UART with data bus [5].

Controller Area Network

Power Management Controller

2.1.1.4 Other characteristics

As far as reliability is concerned, the MCU features a Power-on-Reset, a Brown-out

2.1.1.5 Space characteristics

• It ensures an accumulated TID of 30Krad (Si) with latch-up immunity;

• It is nondestructive against heavy ions;

• It is completely immune to SEL below a Linear Energy Transfer (LET) Threshold

• It ensures an accumulated TID of more than 100 Krad (Si);

• It ensures no SEU below an LET Threshold of 62.5 MeV.cm2/mg at 125◦ C;

2.2 Selection of the other components

2.2.1.1 Volatile Memory

Feature SRAM SDRAM

2.2.1.2 Non-Volatile Memory

The first non-volatile memory technology investigated is the Read-Only Memory. As

Erasable Programmable Read-Only Memory (EPROM) is the next type of studied

Electrically Erasable Programmable Read-Only Memory is another type of memory

error correction codes (ECC).

It is also interesting to consider the differences in power consumption between these

Feature NOR NAND

Ferroelectric Random Access Memory (FRAM) is a non-volatile memory that uses

MT29F2G01ABAGDWB [15] is a 2GB NAND Flash memory that operates through