ISEN

2006

COURS DE DSP
(Digital Signal Processor)
Partie 2: architecture
Alain Fruleux
1- DEVELOPPEMENT A PARTIR DE DSP.

 1.1 Du µP au DSP Quelle famille!!!

 µP Microprocesseurs
 µC Microcontrôleurs
 DSP Digital Signal Processeur

 Risc/Cisc…..8/16/32/64 bits
1.1.1 µprocesseur story
1.1.2 Spécificités du DSP (MAC)
Add 1+2 = 3 Multiply 5*3 = 15

0001 0 x 8 x 0011 0000

1 x 4 x 0011 0011
+ 0010 0 x 2 x 0011 0000
1 x 1 x 0011 0011
0011 Shifted and
added =
5 multiple times 3

Most Common Operation in DSP MAC Operation

A = B*C + D
Typically 70 Clock Cycles With
E = F*G + A Ordinary Processors
..
.
Multiply, Add, and Accumulate Typically 1 Clock Cycle With
MAC Instruction Digital Signal Processors
2 - Structure d ’un Système à DSP (µP)

 2-1 Vision Globale du DSK/TMS320C5510 de TI

 2-2 Architecture d ’une carte DSP
 2-3 Voyage au centre du DSP
 et parallélisme

2-0 Vision Globale DSK/TMS320c5510 de
TI

? 
? 
?


? 
?
2-1 Vision Globale DSK/TMS320c5402 de TI
2-3 ARCHITECTURE D ’UNE CARTE µP
 2-3-1 Structure Générale/BUS


µP ou DSP
 2-3 ARCHITECTURE D ’UNE CARTE µP
 2-3-2 BUS de données (exemple sur 8 bits)


0= 0v

1= 5v (..)

tristate= rien

ou haute impédance
 2-3-3 BUS d ’Adresses (exemple sur 3 bits)
2-3-4 Mapping Mémoire
Organisation de la mémoire du TMS320C5510
0000h

2-4-3 Wait states
2-4-5 Temps pris par une instruction


portw *(a), 0h


p nombre de cycles d ’horloge pour waitstates mémoire programme

d nombre de cycles d ’horloge pour waitstates mémoire données

io nombre de cycles d ’horloge pour waitstates mémoire i/o
 2-3-5 Architectures d’un Calculateur (source TI)

Von Neuman Machine

A
STORED ARITHMETIC
PROGRAM INPUT/ A = ADDRESS
LOGIC
AND D OUTPUT
UNIT D = DATA
DATA

Harvard Architecture
A A
ARITHMETIC
STORED INPUT/ STORED
LOGIC
PROGRAM OUTPUT DATA
UNIT
D D
2-4 Voyage au centre du DSP 54x
System control Program address generation Data address generation
interface logic (PAGEN) logic (DAGEN)
ARAU0, ARAU1
PC, IPTR, RC, AR0-AR7
BRC, RSA, REA ARP, BK, DP, SP

PA
B
P
B Memory
and
CA external
B interface
C
B
DA
B
Peripheral
D interface
B
EA
B
E
B
EXP
encoder

X D A B

MUX

T register

T D A B A C D
A P C D T A B C D S

Sign ctr Sign ctr A(40) B(40) Sign ctr Sign ctr Sign ctr

Multiplier (17 y 17) MUX

0 Barrel
ALU(40)
A B shifter
A MU B
A B
Fractional MUX Legen
d: A Accumulator A MUX
B Accumulator B S
C CB data bus
D DB data bus
Adder(40) E EB data bus MSW/LSW
COM select
M MAC unit P
P PB program bus
S Barrel shifter TR E
ZERO SAT ROUND T T register
U ALU N
T
C
 C54x Architecture
Data Read A/D Bus (C)
Program A/D Bus (P)
Data Read A/D Bus (D)
PC
XPC MAC ALU
Addr
DP @x2 AR0-7
Gen
Decode A
B

Data Write A/D Bus (E)

MAC *AR2+, *AR3+, A ADD @x2, B ...

4
2-4-1 ALU/Registres et bus internes
CB15 - CB0

DB15 - DB0
T

A B T C D S Shifter output (40)

40 40
MUX MUX

SXM Sign ctr Sign ctr SXM

Y X OVM
A B
C16
C
ACC
ALU OVA/OVB
ZA/ZB
MUX TC
40
40 Legend:
A M U B A Accumulator A
40 B Accumulator B
C CB data bus
D DB data bus
MAC M MAC unit
output S Barrel shifter
T T register
U ALU
C5510 Architecture
2-4-2 Pipe-Line C5402

Loads PAB with Loads IR with the contents Loads DB with the data1
the PC's contents of PB read operand
Decodes the IR's contents Loads CB with the data2
read operand
Loads EAB with the data3
write address, if required

Prefetch Fetch Decode Access Read Execute/write

Loads PB with the Loads DAB with the data1 read Executes the instruction
fetched instruction address, if required and loads EB with write
word Loads CAB with the data2 read data
address, if required
Updates auxiliary registers and
stack pointer

Time
 C54x Pipeline
Program A/D Bus (P)

Ext’l A
Internal Data Read A/D Bus (D) External
Mem
Memory Data Read A/D Bus (C) I/F D Memory
Data Write A/D Bus (E)


Internal: Up to 4 accesses / cycle 
External: 1 access / cycle

up to 8M words program
Pipeline Phases
P - generate program address P F D A R X
F - get opcode P F D A R X
D - decode instruction P F D A R X
A - generate read address P F D A R X
R - read operands P F D A R X
X - execute
P F D A R X
Full Pipeline 6