NRC Publications Archive

Archives des publications du CNRC

Development of inkjet-printed inverters

Chu, Ta-Ya; Dadvand, Afshin; Graddage, Neil; Py, Christophe; Lang,
Stephen; Tao, Ye

For the publisher’s version, please access the DOI link below./ Pour consulter la version de l’éditeur, utilisez le lien
DOI ci-dessous.

https://doi.org/10.4224/23000711

NRC Publications Archive Record / Notice des Archives des publications du CNRC :
https://nrc-publications.canada.ca/eng/view/object/?id=4486bd0a-fde5-4309-afc4-cc8c53e6d270
https://publications-cnrc.canada.ca/fra/voir/objet/?id=4486bd0a-fde5-4309-afc4-cc8c53e6d270

Access and use of this website and the material on it are subject to the Terms and Conditions set forth at
https://nrc-publications.canada.ca/eng/copyright
READ THESE TERMS AND CONDITIONS CAREFULLY BEFORE USING THIS WEBSITE.

L’accès à ce site Web et l’utilisation de son contenu sont assujettis aux conditions présentées dans le site
https://publications-cnrc.canada.ca/fra/droits
LISEZ CES CONDITIONS ATTENTIVEMENT AVANT D’UTILISER CE SITE WEB.

Questions? Contact the NRC Publications Archive team at

PublicationsArchive-ArchivesPublications@nrc-cnrc.gc.ca. If you wish to email the authors directly, please see the
first page of the publication for their contact information.

Vous avez des questions? Nous pouvons vous aider. Pour communiquer directement avec un auteur, consultez la
première page de la revue dans laquelle son article a été publié afin de trouver ses coordonnées. Si vous n’arrivez
pas à les repérer, communiquez avec nous à PublicationsArchive-ArchivesPublications@nrc-cnrc.gc.ca.
Development of inkjet-printed inverters

Ta-Ya Chu, Afshin Dadvand, Neil Graddage, Christophe Py, Stephen Lang,
and Ye Tao
Outline

• Introduction

• Development of 3-layer-printed OTFTs

• Different types of printed inverter developed at NRC

 Enhancement-load PMOS inverter
 PMOS inverter (screen printed resistor)
 CMOS inverter

• Stability of printed inverter

 Challenges in printing process
2200
Organic light emitting
2000 Organic transistor
Printed transistor
1800 Challenges  yield, stability
1600
 Uniformity, Roughness
Number of publication

1400
 Interface interaction
1200
 Solvents compatibility
1000

800
 Drying process
600
 Printing platform
400

200

0
1985 1990 1995 2000 2005 2010 2015
Year

Thermal evaporation
Spin coating Printing process
Polymer based transistor backplane is required for
flexible/bendable electronics in the future

Polyera smartwatch using OTFTs Flexible Curved Foldable Bendable

Spin coated dielectric and sputtered gate electrode

NRC 3-Layer-Printed Organic Thin Film Transistors (OTFTs)

Inkjet printed layers

 No spin coating process
 Organic semiconductor
 Printing process in ambient air
 Dielectric
 Ag top gate electrode

Ag Organic
Dielectric Semiconductor
S D

PET Substrate

3-layer-printed OTFTs
Thin and uniform printed dielectric layer enabled by the
coffee ring effect
1000
Drop Spacing

 Transistor driving voltage is proportional to 800

15m
25m
35m

the thickness of dielectric layer 45m

55m

600

Height [nm]
 Difficult to achieve a pin-hole free of thin 400

dielectric layer by printing method

200

 Coffee ring effect is usually undesirable 0

-60 -40 -20 0 20 40 60

Width [m]
600
1 Nozzle
550 2 Nozzles
3 Nozzles
500
450
400

Height [nm]
350
300
250
200
150
100
50
0
-50
-300 -200 -100 0 100 200 300
Organic Electronics 29 (2016) 114-119
Width [m]
 3-layer-printed OTFTs mobility up to ~1 cm2/Vs at 15 V

Ag Dielectric thickness~ 250 nm

Dielectric
DPP-DTT
Max. Processing Temp. 140°C
S D

PET Substrate
Average mobility of 0.86 cm2/Vs (variation σ~15%) with
3-layer-printed OTFTs on/off ratio of 105 obtained at 15 V.
-4
10 10 70
VDS=-15 V VGS (V) 1.4 Standard deviation 0.15 (17%)
-5
10 60 -1
8
-3 1.2

Mobility (cm /Vs)

-6
10 50 -5
(10 A )
1/2

6 1.0
-7

2
-IDS (A)
-3

-7
40
-IDS (A)

10 -9 0.86
0.8
-11
4
1/2

10
-8 30 -13
(-IDS)

2 0.6
=1.0 cm /Vs -15
10
-9
2 20
0.4

10
-10 10
0 0.2

10
-11 0
2
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 18 20 420 OFETs (8 OFETs, 2%, mobility lower than 0.2 cm /Vs
are not counted for statistics)
-VG (V) VDS (V)

Channel length 5 µm, channel width 1 mm

Printed PMOS enhancement-load Inverter and relative
logic circuits

Simplest printing process and excellent stability

Lower output amplitude

Input
2 Output
0
Vdd -2

Vout -4

Vin -6

Voltage (V)
-8

-10

-12
Channel length L= 5 µm, -14
Channel width -16
 Drive transistor W=1 mm -18
 Load transistor W=200 µm, -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03
Time (sec)
Vdd=-20V, 100 Hz
 Printed logic gates NAND, AND, NOR and OR

0 Vin1 Table 1. Truth tables for NAND, AND, NOR and OR logic gates
Output for the different logic gates
-10
Vin 1 Vin 2 NAND AND NOR OR
-20 1 1 0 1 0 1
0 Vin2 1 0 1 0 0 1
-10 0 1 1 0 0 1
-20 0 0 1 0 1 0
0
NAND
Voltage (V)

-10 NAND NOR AND OR

-20
0 AND
-10
-20
0 NOR
-10
-20
0 OR
-10
-20
-0.03 -0.02 -0.01 0.00 0.01 0.02 0.03
Vdd=-30V Time (sec)
 Printed PMOS inverter using screen printed resistor

Screen printed carbon ink for resistor

Printed inverter (Inkjet printed OFET/ Screen printed resistor)
Input
2
Output
0
3.0
Vdd -2

-4
2.5
Vout -6

Voltage (V)
Vin
Delay time (ms)

2.0 -8

-10

1.5 -12

-14

1.0 -16

-0.15 -0.10 -0.05 0.00 0.05 0.10 0.15

0.5 Time (sec)
OFET (L=5m, W=1mm), Screen printed resistor
0 1 2 3 4 5 10
0
Resistance of the external resistor (M) 9
-2
8
-4 7
Vout (V) -6 6

Gain
-8 5
Delay time is dominated by the resistance -10 4

-12 3
2
-14
1
-16
0
-14 -12 -10 -8 -6 -4 -2 0

Vin (V)
 Development of printed CMOS inverter

3-Layer-Printed NDI2OD-T2
Ag
N type transistor SOG Dielectric
N-type semiconductor

S D

12 4.0 PET Substrate

0V
4V 1E-5
vDS=20 3.5
10 8V
12 V
1E-6
3-layer-printed OTFTs
16 V 3.0
20 V SQRT IDS (mA)
8
Log IDS (A)

1E-7 2.5
IDS()

6 2.0 Mobility Off-

1E-8 Dielect. Vth On-current
(cm2/Vs) current On/Off
1.5 Thick. (nm) (V) (A)
4 1E-9 @ bias=20 V (A)
1.0 800 0.01 12.8 2.5E-07 1.16E-12 2.1E+05
2 1E-10
0.5 450 0.05 10.9 3.2E-07 1.20E-12 2.6E+05

1E-11
300 0.05 9.7 5.0E-07 7.15E-12 7.0E+05
0 0.0
0 5 10 15 20 0 5 10 15 20 220 0.10 8.4 8.8E-06 6.24E-11 1.4E+05
VDS(V) VGS(V)
180 0.12 4.1 1.5E-05 6.70E-10 4.0E+04

Organic Electronics 29 (2016) 114-119

 Development of printed CMOS inverter

Difficulties
 Compatible processing condition for
both P and N type materials
 Compatible IV characteristics
 Stability between P and N

Vin DPP-DTT
P-type semiconductor
NDI2OD-T2
N-type semiconductor
P N Vin

Ag Ag
Dielectric Dielectric
Vdd P Vout N Ground

Vdd Vout PET Substrate

 Development of printed CMOS inverter

Printed CMOS driven at 10Hz (15V, exposed in air)

20
Initial
1 hr
 Full-swing output amplitude achieved 18 2 hrs
7 hrs
 Gain value of 24 obtained 16 80 hrs

 Air stability testing without encapsulation

14

12

Output (V)
10

8
24 24
10 V 6

21 15 V 21 4
20 V
2
18 25 V 18
0
-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3
15 15 20 Time (sec)
Gain

Output
Vds(V)

18 Input
12 12
16
After 80 hrs
9 9 14

12
6 6
Vout 10

3 3 8

6
0 0
25 20 15 10 5 0 4

Vgs(V) 2

0
0.0 0.5 1.0 1.5 2.0 2.5
Time (sec)
 Summary

 NRCSummary
developed printing process for 3-layer-printed OFETs, mobility of 1 cm2/Vs on
PMOS and 0.1 cm2/Vs on NMOS transistors have been achieved.

 Introduced coffee ring effect to achieve thin and uniform dielectric layer by inkjet
printing process.

 Gain value of 24 with a nearly full-swing of output voltage obtained from the printed
CMOS inverter.

 Demonstrated the air stable printed CMOS without encapsulation

Semiconductor

Printed circuits

Electrode Dielectric

Printed logic circuits for electronics integration

 Thank you for your attention!

Question?

Dr. Ta-Ya Chu

Research Officer
Tel: 1-613-949-7558
ta-ya.chu@nrc-cnrc.gc.ca
www.nrc-cnrc.gc.ca

15
16