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Circuits en VHDL
Réalisé par :
Youssef Hammami
library ieee;
use ieee.std_logic_1164.all;
entity REG is port (
CLK, IR,IL,S0,S1 : in std_logic;
I : in std_logic_vector (3 downto 0);
Q : out std_logic_vector (3 downto 0));
end REG;
architecture DEC of reg is
signal QS: std_logic_vector (3 downto 0);
Begin
Q <= QS;
process ( CLK)
begin
if (CLK'event and CLK ='1') then
if (S0='0' and S1= '0') then
QS<=QS;
elsif (S0='1' and S1= '0') then
QS<=I;
elsif (S0 ='0' and S1='1') then
QS(3)<=QS(2);
QS(2)<=QS(1);
QS(1)<=QS(0);
QS(0)<=IR;
elsif (S0 ='1' and S1='1') then
QS(0)<=QS(1);
QS(1)<=QS(2);
QS(2)<=QS(3);
QS(3)<=IL;
end if;
end if;
end process;
end DEC;
2) Écrire le code VHDL TestBench
library ieee;
use ieee.std_logic_1164.all;
entity testbench is
end entity;
architecture test of testbench is
component REG port (
CLK, IR,IL,S0,S1 : in std_logic;
I: in std_logic_vector (3 downto 0);
Q : out std_logic_vector (3 downto 0));
end component;
signal CLK : std_logic := '0';
signal IR : std_logic := '0';
signal IL : std_logic := '0';
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';
signal I : std_logic_vector (3 downto 0) := (others => '0');
signal Q : std_logic_vector (3 downto 0);
Begin
dut: REG port map (
CLK => CLK,
IR => IR,
IL => IL,
S0 => S0,
S1 => S1,
I => I,
Q => Q
);
CLK_process : process
begin
CLK <= not CLK ;
wait for 1 ms;
end process;
stim_proc: process
begin
S0 <= '0';
S1 <= '0';
IR <= '1';
IL <= '0';
I <= "0011";
wait for 4 ms;
S0 <= '1';
S1 <= '0';
wait for 4 ms;
S0 <= '0';
S1 <= '1';
wait for 4 ms;
S0 <= '1';
S1 <= '1';
wait for 4 ms;
end process;
END;
3)Le chronogramme de la simulation