THESE DE DOCTORAT DE

L'UNIVERSITE DE RENNES 1

ECOLE DOCTORALE N° 601

Mathématiques et Sciences et Technologies
Par
de l'Information et de la Communication
Spécialité : Electronique
SeungJae MOON
Par

« Seungjae MOON »
« Development of Inkjet Printing Technology for Fully Solution Process
Dedicated to Organic Electronic Circuits»
Thèse présentée et soutenue à Rennes, le 17/06/2020
Unité de recherche : UMR 6164
Thèse N° :

Rapporteurs avant soutenance :

Yvan Bonnassieux Professeur des universités, Ecole Polytechnique, Palaiseau
Louis Giraudet Professeur des universités, Université de Reims

Composition du Jury :

Président : France Le Bihan Professeur des universités, Université de Rennes 1

Examinateurs : Arnaud Stolz Maître de conférences, Université d'Orléans
Brice Le Borgne Maître de conférences, Université de Tours

Dir. de thèse : Emmanuel Jacques Maître de conférences, Université de Rennes 1

Co-dir. de thèse : ByungSeong Bae Professeur des universités, Hoseo University
Co-enc. de thèse : Maxime Harnois Ingénieur de recherche CNRS, Université de Rennes 1
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Invité(s)
 Résumé de thèse
Ces dernières décennies, des efforts de recherches considérables ont étés mis en œuvre afin
de répondre aux nouveaux défis sociétaux (i.e., énergie durable, utilisation efficaces de matières
premières, la santé, la mobilité…) ainsi qu’aux nouveaux modes de consommations (i.e., objets
connectés, écrans grandes surfaces voir souples…). Ainsi, devrait voir le jour dans un future
proche : i) des écrans et des panneaux photovoltaïques souples, transparent et couvrant de
grandes surfaces, ii) des capteurs connectés souples enregistrant des constantes physiologiques
aux plus près des patients… Les acteurs de l’électronique (i.e., multinationales et laboratoire de
recherches) s’efforcent de proposer de nouvelles technologies permettant de satisfaire ces
nouveaux besoins. L’une d’elle, développée depuis une décennie et communément
appelée « électronique imprimée », est un sérieux candidat pouvant répondre aux
problématiques actuelles citées précédemment.
L’électronique imprimée, met en œuvre des matériaux en solution (encres : polymériques,
semiconductrices, à base de nano-objets…) en utilisant des équipements déjà éprouvés dans
l’art graphique. Cependant, les savoirs faire acquis dans le domaine de l’impression doivent
être transférés vers « le monde de l’électronique ». Cette problématique, constituant un enjeu
majeur, a donné naissance à cette étude. En effet, la méthodologie de conception des
dispositifs électroniques imprimés est différente de celle utilisée en « électronique
conventionnelle ». Concrètement, un dispositif électronique imprimé est réalisé de façon
additive (chaque couche le constituant est déposée l’une après l’autre et ne nécessite aucune
étape de gravure) contrairement à un dispositif réalisé par photolithographie (procédé
communément utilisé en microélectronique). De plus, l’électronique imprimée peut adresser
d’autres challenges tels que : la réalisation à basse température d’électronique sur des substrats
non-conventionnels compatibles grandes surfaces (plastique, papier, biodégradable…). Des
premiers transistors entièrement imprimés ont étés réalisés en laboratoire, mais, à ce jour, aucun
produit n’a été commercialisé en utilisant cette technologie. En effet, de nombreux verrous
restent à lever tels que : la fiabilité et la reproductibilité des dispositifs.
Lors de précédents travaux menés à l’IETR, des transistors imprimés ont ainsi pu être réalisés
montrant la faisabilité d’utiliser l’impression jet d’encre pour la fabrication de dispositifs
électroniques intégrés. Les objectifs de cette thèse sont les suivants :
- Mieux comprendre la structure d’un transistor organique imprimé pour optimiser le
procédé de fabrication

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 - Améliorer les performances électriques des transistors organiques imprimés pour
les intégrer dans des circuits électroniques
- Etudier la stabilité électrique de ces transistors pour améliorer la fiabilité des circuits
- Fabriquer un circuit numérique avec cette nouvelle technologie d’impression jet
d’encre

La première partie de ces travaux de thèse ont consisté en l’amélioration de la structure

transistor organique par le procédé d’impression jet d’encre. Jusqu’à présent, uniquement les
électrodes de grille, de drain et de source était fabriquées par impression jet d’encre. En
microélectronique, les isolants de grille sont des matériaux de type inorganique et ne répondent
pas cahier des charges permettant leur impression. Un isolant de type polymère a donc été
étudié. La SU8 est une résine photosensible qui, du fait de ces propriétés physique, est
compatible avec un procédé d’impression jet d’encre. Cet isolant organique a, tout d’abord, été
étudié d’un point de vue électrique en la déposant en solution par spin-coating, technique
maitrisée dans le domaine de la microélectronique. Ces propriétés électriques se sont avérées
très intéressantes pour une utilisation en tant qu’isolant telles qu’un courant de fuite très faible
(I ≤ 10-9 A/cm2), un champ électrique de claquage élevé (4.5 MV/cm) et une constante
diélectrique =3,2.
La suite de ces travaux s’est donc tournée vers l’étude de l’impression de ce polymère. En
effet, l’impression d’un matériau en solution nécessite un contrôle précis des paramètres
rhéologiques des encres ainsi que l’étude du comportement de ces encres sur la surface sur
laquelle elles sont déposées.

Figure 1. Influence des recouvrements entre gouttelettes sur l’épaisseur des films à base de SU-8. (a)
Mesure profilométrique 2D de la morphologie de la SU8, (b) épaisseur en fonction du recouvrement des
gouttelettes.

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 La création de films uniformes, le contrôle de l’épaisseur de la couche isolante et l’étude de
la morphologie des films a constitué un travail technologique important au cours de cette thèse
(Figure 1). Comme le montre la Figure 2, l’impression d’une structure transistor nécessite le
contrôle précis de la couche imprimée en fonction de la couche précédente. L’impression des
électrodes de drain et de source a nécessité des modifications de surface de la SU8 imprimée
pour l’obtention de film continu. Après différentes tentatives d’impression de ces électrodes en
modifiant les paramètres d’impression comme dans le cas de l’étude précédente, l’étude de
l’impact d’une exposition du film SU8 à de l’UV Ozone a permis de modifier l’hydrophobicité
de la couche SU8 et de réaliser des films continues à base d’encre d’argent pour la réalisation
des électrodes drain/source.

Figure 2. (a) Structure du transistor organique imprimé, (b) impact de l’exposition UV Ozone de la
SU8 sur la continuité des lignes d’argent, (c) impact de l’exposition UV Ozone de la SU8 sur la création
d’électrodes d’argent.

La dernière étape pour la fabrication d’un transistor organique imprimé s’est concentrée sur
l’étude du semiconducteur organique du type fullerène (C60) déposé par évaporation thermique
lors de la dernière étape de la fabrication. L’impact des résistances d’accès entre les électrodes
en argent (drain/source) et le semiconducteur sur l’injection et le transport des charges à travers
le fullerène a nécessité un travail d’optimisation de cette couche en termes de cristallinité et
d’épaisseur. Cette étude sur l’optimisation des performances électriques du transistor organique
imprimé a débouché sur l’obtention de résultats au niveau de l’état de l’art (Figure 3). Ces
transistors ont été, ensuite, fabriqués en plus grande série pour des études de reproductibilité,
d’uniformité des performances et de stabilité électrique. En effet, ces éléments constituent la
base pour la conception de circuits électroniques à partie des transistors organiques imprimés.
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 Figure 3. Caractéristiques de transfert et de sortie de transistors organiques imprimés à base de
fullerène C60.

Ces travaux de thèse se sont ensuite concentrés sur la fabrication de circuits numériques
organiques en technologie jet d’encre. Un modèle électrique a été développé à partir des
caractéristiques électriques présentées sur la Figure 3 à l’aide du logiciel Aim-Extract. Des
circuits logiques de type inverseur, porte logique NAND, multiplexeur et bascule D ont été
simulés avec ce modèle à l’aide du logiciel Aim-Spice. Enfin, à partir d’une phase de
dimensionnement de ces circuits, ils ont été fabriqués avec la technologie d’impression jet
d’encre optimisé au cours de cette thèse. Un exemple de résultat d’une bascule D est présenté
sur la Figure 4.

Figure 4. (a) Mesure électrique d’une bascule D organique en technologie impression jet d’encre, (b)
Bascule D imprimée sur substrat flexible de type PEN (25µm), (c) Schéma électrique d’une bascule D.

En conclusion, les travaux menés lors de cette thèse ont permis de démontrer la faisabilité
d’un circuit numérique organique en technologie impression jet d’encre. Les résultats obtenus
démontrent aussi les compétences acquises par l’IETR sur des recherches technologiques de
pointe en partant du matériau pour aboutir la conception d’un circuit électronique complet.

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 General introduction
To date, silicon based electronic devices are mainly dominates the global market of
electronics. Conventional cleanroom manufacturing using photolithography method is a
method of choice to meet the standard of microelectronics industry in terms of accuracy and
resolution. However, even if complex devices are easily fabricated using this technology many
drawbacks can be listed such as: high temperature processing, the use of non-friendly chemical
reagents for environment, complex and expensive tools are mandatory, etc. Thus, it makes
sense to develop low cost alternative technologies to provide electronics for application dealing
with lower requirements in terms of performances than the silicon based one. For, instance
healthcare applications needing conditioning electronics to acquire sensors signal onto
wearable substrate could be a targeted one.
These past decades organic electronics have been deeply studied to answer this kind of issue.
Even if reported results show lower performances than silicon-based electronics, many
advantages can be listed: low production costs, low temperature deposition (under 200°C),
flexible or even stretchable and large processing, etc. Consequently, many devices using
organic electronic technology and proof of concepts have been developed including organic
solar cell (OPV), an organic thin-film transistor (OTFT), and commercialization of organic
light-emitting diode (OLED).
However, more research must be conducted on organic materials such as semiconductor
because there are often highly sensitive to moisture, temperature, etc. at the detriment of their
electrical stability. From process and development point of view, most of organic materials can
be put into solution. It can make a candidate of choice regarding inkjet printing technology
which has been originally developed in the field of graphic arts. These last ten years, this
technology has been considered to print functional materials such as conductive colloid,
polymer, organic semiconductor, etc. Printing technologies are considered as a prime candidate
to fabricate electronics with the following criteria: i) large area, ii) processing on various type
of substrates (flexible, stretchable, etc.), iii) eco-friendly, iv) low capital investment, low time-
lapse from idea to the fabrication, and v) easy process with low-cost accompanied by
minimized waste of materials (gas, fluid, etc.). An inkjet printing technology called Drop on
Demand (DoD) becomes more and more attractive (academics as well as industrials) due to its

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specificities especially, the low volume of required material, the reproducibility and the use of
a software design avoiding the need of a hard mask.
From these statements, the main objective of this work is to demonstrate the capability
of DoD inkjet printing technology to fabricate organic based digital circuits made of
Organic Thin Film Transistors (OTFT). This work benefited from the great experience of
IETR in thin film electronics, particularly in organic based transistors made by
photolithography. The present work continues this trend towards low cost and low temperature
processed electronics.
This thesis is organized in 4 chapters:
In the first chapter, a review of the printing technology is described focusing on their
advantages and drawbacks. As the Drop on Demand technology has been chosen for this study,
it has been deeply detailed. DoD consists of jetting picoliters droplets deposited onto a substrate
before it dries. Consequently, all the physical parameters (fluid rheology, fluid drying and
pattern formation) must be understood to obtain optimized patterns shape.
The second chapter is divided into two sections. The first one detailed the OTFT structures
as well as the characterization methodology used to extract the main parameters allowing the
design of electronic circuits. In the second subsection, a review of all the printable materials
allowing the fabrication of a printed transistor is detailed.
In the third chapter, materials and methods to fabricate fully additive OTFT are detailed.
An extensive study of jetting parameters for each printed material is presented. Su8 photoresist
used as ink that has already shown interesting insulating properties in a previous study dealing
with OTFT fabricated using photolithography process is printed. This section shows an
experimental protocol that can be performed to deeply study material from printed point of
view including: Jetting, Wetting, surface modification, etc. Interestingly, the impact of its
morphology onto OTFT has been analysed showing that inkjet printing is as efficient as a spin
coating to provide polymeric insulator. Processing parameters such as baking temperature
allowing semiconductor optimization are also detailed and constitute one of the main
parameters to fabricate OTFTs with electrical behaviour at the state of the art allowing their
integration in a circuit.
Finally, the fourth chapter deals with the simulation, the fabrication and the electrical
characterization of digital circuits made of printed C60 OTFT. A simple model of a single
printed OTFT has been used to predict electrical behaviour of more complex circuit. Single

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inverters made of printed OTFT have been studied to evaluate limitations of printed technology
such as minimum supply voltage and frequency limitation. Using Aim-Spice simulation, a 2:1
multiplexer and a D-latch have been fabricated and electrically characterized.

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Table contents
RÉSUMÉ DE THÈSE ...................................................................................................... 3

GENERAL INTRODUCTION ......................................................................................... 7

TABLE CONTENTS ......................................................................................................10

CHAPTER 1: SOLUTION PROCESS TECHNOLOGIES: BASIC CONCEPTS ..........15

I. Comparison of solution and vacuum process ....................................................................... 15

II. Introduction of solution process technologies ..................................................................... 16

Coating ..................................................................................................................................................................... 17
1. Spin-coating .................................................................................................................................................... 17
2. Meniscus – Guided Coating (MGC) ..................................................................................................... 19
Drop casting .......................................................................................................................................................... 25
Printing ..................................................................................................................................................................... 25
1. Contact - printing ......................................................................................................................................... 26
2. Non - Contact - printing........................................................................................................................... 32

III. Conclusion .................................................................................................................................... 45

CHAPTER 2: PRINTED ORGANIC THIN FILM TRANSISTOR ............................... 50

I. Organic Thin Film Transistor – Basis Concept ....................................................................... 50

A. OTFT Structure and Working Principle ..................................................................................................... 50
1. Working Principle ......................................................................................................................................... 50
2. TFT structure and geometry .................................................................................................................... 56
B. Electrical Characterization and Parameters Extraction....................................................................... 58
1. Electrical characteristics of TFTs ............................................................................................................ 58
2. Electrical parameters extraction ............................................................................................................. 60
C. Electrical Stability of OTFT .............................................................................................................................. 66
1. Why do we need to consider electrical stability of TFT for circuit applications? .......... 66
2. Origin of electrical instability in OTFT ................................................................................................ 67

II. Materials for Printed OTFT ....................................................................................................... 70

A. Context of this study ......................................................................................................................................... 70
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 B. Printed Conductive Layer ................................................................................................................................ 71
1. Conductive metal NP inks ........................................................................................................................ 71
2. Conductive Polymer .................................................................................................................................... 75
C. Printed Insulating Layer ................................................................................................................................... 76

III. Technical approaches to optimize TFT ................................................................................... 79

IV. Conclusion .................................................................................................................................... 80

CHAPTER 3: FABRICATION OF INKJET-PRINTED N-TYPE ORGANIC FIELD

EFFECT TRANSISTOR .....................................................................................................83

I. Material selection ....................................................................................................................... 84

A. Metal electrode: Ag nanoparticle ink ........................................................................................................ 84
B. Gate dielectric: Epoxy based ink (SU-8) ................................................................................................... 85
C. N-type organic semiconductor; Fullerene (C60) .................................................................................... 88

II. Inkjet printing methodology .................................................................................................... 89

A. Hardware for DoD inkjet printed OTFTs .................................................................................................. 89
B. DoD inkjet-printing methodology: The methodology of the printing process for this
study 90

III. Process optimization .................................................................................................................. 93

A. Printability optimization of functional materials .................................................................................. 93
B. Jetting parameters; optimization of Ag NP ink .................................................................................... 94
C. Jetting parameters; optimization of SU-8 ink........................................................................................ 95
D. Optimization process for film formation ................................................................................................. 96
1. Inkjet-printed Ag electrode ..................................................................................................................... 96
2. Inkjet-printed Gate dielectric (SU-8); morphology control ..................................................... 105
3. Summary of the Fabrication process of inkjet-printed n-type OTFT ................................. 108

IV. Optimization of electrical characteristics of inkjet-printed n-type OTFT ...................... 112

Non-optimized inkjet-printed n-type OTFT ........................................................................................ 112
Layer morphology effect .............................................................................................................................. 113
1. Gate morphology ....................................................................................................................................... 113
2. Processing and morphology study of Su-8 ................................................................................... 114
3. Optimization of n-type OSC; C60......................................................................................................... 117
Optimized inkjet-printed n-type OTFT .................................................................................................. 127
Reproducibility & Uniformity properties ............................................................................................... 128

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 Electrical stability .............................................................................................................................................. 130

V. Conclusion .................................................................................................................................. 132

CHAPTER 4: CIRCUIT APPLICATIONS USING INKJET PRINTED N-TYPE

ORGANIC THIN-FILM TRANSISTORS ...................................................................... 135

I. Inkjet-printed applications based on OTFTs ....................................................................... 136

Elementary circuits ........................................................................................................................................... 137
1. Logic inverter ................................................................................................................................................ 138
2. Logic NANDs ................................................................................................................................................ 143
3. Oscillator ......................................................................................................................................................... 143
Digital circuits .................................................................................................................................................... 146
1. Combinational circuits .............................................................................................................................. 147
2. Sequential circuits ...................................................................................................................................... 147

II. Development of inkjet-printed inverter based on n-type OTFTs.................................... 148

Inverter with a discrete load resistance ................................................................................................. 148
1. Output versus load resistance characteristics ............................................................................... 148
2. Channel length effect on the electrical performance of Inverter: 100 μm and 200 μm
…………………………………………………………………………………………………..154
Fully printed Inverter ...................................................................................................................................... 156
1. Model verification of electrical performance ................................................................................ 156
2. Evaluation of fully inkjet-printed inverter ....................................................................................... 159
Development of electrical characterization method ....................................................................... 162
1. Problem on electrical characterization system ............................................................................. 162
2. Load capacitance (CL) effect on inverter characteristics .......................................................... 164

III. Result and analysis of fully inkjet-printed NMOS circuits................................................ 165

Fully inkjet-printed Logic gates (Inverter and NANDs) .................................................................. 165
1. NMOS Inverter ............................................................................................................................................. 165
2. NMOS NAND ............................................................................................................................................... 167
Fully inkjet-printed Digital circuit application .................................................................................... 170
1. 2 to 1 Multiplexer based on n-MOS logic gates ........................................................................ 170
2. D-latch based on n-MOS logic gates ............................................................................................... 173

IV. Conclusion .................................................................................................................................. 178

GENERAL CONCLUSION ......................................................................................... 181

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REFERENCE ................................................................................................................ 186

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 Chapter 1: Solution process technologies:
basic concepts
Chapter 1 provides an overview of the solution process technologies divided into various
categories. The advantages and disadvantages of each technology are discussed.
Section 1 dealt with a comparison between the solution process and the vacuum process.
Section 2 described all kinds of solution-based coating, casting, and printing technologies.
Importantly, the sub-section dealing with printing technologies carefully described drop-on-
demand printing technology, as it is the main technique used in this thesis.

I. Comparison of solution and vacuum process

Generally, two different processing exist as manufacturing techniques in the field of
electronic fabrications, i.e., vacuum deposition (VD) and solution processing (SP). These two
deposition methods require specific materials properties, such as solubility and thermal
stability 1, 2.
To date, the vacuum process is a widely used technology for electronics, because the vacuum
deposition has several outstanding benefits from accuracy, easy fabrication of stacked
multilayers, etc. Therefore, the resulting thin films using vacuum deposition show generally
high quality providing a low density of defects. However, the vacuum deposition technique is
not easily compatible with the online process at high speed over a large area and leads to high
production costs. In general, the vacuum deposition takes place in the gas pressure range of
10−5 Torr to 10−9 Torr, depending on the level of gaseous contamination that can be tolerated
in the deposition system 3. Another major problem with vacuum processes compared to
solution processes is the complexity of the process.
For instance, in the manufacturing system of white OLED, as shown in Figure 1(a), the
fabrication process can be further simplified via the solution process technique. Recently, the
use of the solution process has drawn increasing attention in the research field to realize low-
cost fabrication onto the large area substrates with high performance 4. As shown in
Figure 1(b), the cost of manufacture for nozzle-printed OLEDs is projected to be about 30%
below the incumbent liquid crystal display (LCD) cost and almost 50% below equivalent
evaporated panels. When the costs of full Gen. 8 solution processing are compared to cut-down
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processing for evaporation, the difference increases to almost 60% 5. Moreover, depending on
requirements, the solution process not only has advancement for the cost, but it also can bring
more significant strengths than the vacuum process.

Figure 1. Comparison between the vacuum process (evaporation process on full and cut down (1-6)
substrates) and solution process. (a) Comparison of process complexity, (b) cost comparison for 55-
inch OLED fabrication 4, 5.

The selected method for solution processing is the main issue to expand commercialization
opportunities for organic electronics. To commercialize electronic devices, the challenge is to
find a suitable method to allow scale-up manufacturing at low production cost and fast
processing. Besides, requirements, such as adequate device performances, long-term stability
of the device at ambient conditions, and device homogeneity and yield in a wide range of areas,
are still actively researched. The solution process can compete with the vacuum process 6. Thus,
each deposition method of the solution process will be described in the following sections.

II. Introduction of solution process technologies

Solution process has already been used to fabricate the following devices: photovoltaic (PV),
thin-film transistor (TFT), organic light-emitting- diodes (OLED), electrochromic
devices (EC), radiofrequency identifications (RFIDs) and sensors. Most of them have now
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reached a maturity stage at the laboratory scale. Now upscaling and improving the processing
speed becomes the next development phase 7. In this section, we will introduce and draw a list
of processing methods compatible with organic and inorganic material in solutions. The
diversity of techniques attests to the versatility of solution-phase deposition, and we attempt to
give a representative list of methods discussed in the literature, including the background of
each process technique, advantages and disadvantages, technology application, prospect, etc.

Coating

1. Spin-coating
In general, the spin-coating method can be divided into four steps, as shown in Figure 2.

Figure 2. Illustration of steps of thin-film formation using spin coating of a small molecule (a)
dispense, (b) acceleration, (c) flow dominated stage and evaporation dominated stage, (d) formed thin
film after complete evaporation 8.

Spin coating is one of the most common techniques to deposit solution based thin film to
substrates. This coating method is commonly used in engineering and microelectronics
industries. By using this method, uniform coatings of organic/inorganic materials can be
deposited on a substrate 9. The spin coating method has been highlighted as an essential
solution process technique but also has already been used in conventional technologies such as
the photolithography patterning process. The most important advantage of the spin-coating
method is that it allows forming highly uniform and reproducible thin-film.

This process can be described as follows:

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 i. Dispense (Figure 2(a))
The initial step is the casting of the solution onto the substrate. This step can be divided into
static and dynamic dispersions. The static dispense is simply depositing a small amount of fluid
(ranging from 1 to 10 cc depending on wafer size) on or near the center of the substrate.
Dynamic dispense is the fluid spreading when the substrate is rotating at low speed (basically
starting from 500 rpm).

ii. Acceleration (Figure 2(b))

The substrate reaches the desired rotation speed – either immediately or following a lower-
speed spreading step. This step is usually characterized by fluid expulsion from the wafer
surface by the rotational forces. The spiral vortices are a result of the twisting motion, and it
occurs by the inertia on the top of the fluid layer. These phenomena are dependent on
acceleration.

iii. Flow dominated stage (Figure 2(c)

The fluid begins to be thinner, as viscous forces dominate. This step is characterized by
gradual fluid thinning. Fluid thinning is generally quite uniform using solutions containing
volatile solvents. It is often possible to see interference colours “spinning off” when the
thickness decreases 10.

iv. Evaporation dominated stage (Figure 2(d))

As the prior step advances, the fluid thickness reaches a point where the viscosity effects
yield only slightly a minor net fluid flow. At this point, the coating effectively “gels” because
as these solvents are removed the viscosity of the remaining solution rises freezing the film 11.
However, the spin coating technique has common defects such as comets, striations,
environmental sensitivity, and wafer edge effects 8, which occur at the detriment of the film
quality.

Spin-coating is mostly used to deposit a photoresist layer. It can also be used to deposit
functional layers such as semiconductor and dielectrics or even a mixture of both. Thus vertical
phase segregation can be exploited to separate semiconductors from polymers to fabricate
efficient semiconductive layers 12. Recently, several groups have reported novel spin coating

18
methods. These modifications of conventional spin-coating have been used to fabricate high-
13
performance devices. For instance, Yuan et al. have developed a method called off-center
spin coating (OCSC). Where the target substrate was placed 20 to 40 mm away from the
rotation axis. They successfully demonstrated an organic thin-film transistor (OTFT) with
transparency > 90 % in the visible range and recorded high hole mobility of 43 cm2V-1s-1. The
obtained very high hole mobility mainly results from highly aligned crystalline grains with a
slightly reduced in-plane intermolecular spacing. Moreover, they used PS blended dielectric
with semiconductor, and vertical phase segregation was formed. Indeed, the PS segregates from
the semiconductor leading to reduce interfacial traps.
Advantages and disadvantages of the spin coating technique may briefly be organized as
follow: concerning the advantages, spin coating is a relatively simple process. It allows to
provide thin and uniform films.
One drawback of spin coating is that it is a single substrate process and therefore has a
relatively low throughput compared to other methods (see the description in the following sub-
chapter). It still has another issue to overcome: difficulties to provide uniform coating onto
non-flat surfaces/substrates (i.e., flexible). The actual amount of material used in a spin coating
process is low. However, 90 % fluid off goes from the side of the substrate and wasted. While
this is not usually an issue for research environments, it is showed that it is dramatic for the
industry.
High velocity is mandatory to fabricate a micrometer thick film leading to fast solvent
evaporation. When a functional film such as an organic semiconductor is used, it can be a
drawback. Indeed, in general, the more the solvent evaporates slowly, the more the
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semiconductor gains are big, the more the devices are efficient . Despite these drawbacks,
spin coating technology is generally the starting point for the manufacturing system in medium-
cost. Besides, it is a convenient technique for most academic and industrial processes that need
a thin and uniform coating.

2. Meniscus – Guided Coating (MGC)

MGC technology gained attention as a technology that can efficiently utilize materials with
excellent throughput. The superior throughput of MGC means a continuous process method
suitable for the production of large-scale applications. Also, the most important factor is with

19
a high material consumption of over 99 %. In other words, it means that MGC is a technology
that can address the drawback of the spin coating, as aforementioned in the previous section.
It is a relevant continuous process flow that can be applied for large-scale applications.
Notably, the most important factor is that the amount of material is utilized more than 99 %
(i.e., the amount of waste) 15. The term “meniscus-guided” refers to the fact that a meniscus is
translated across a substrate under a coating head. Thus, viscous and capillary forces guide and
control the film deposition.

Figure 3. Summary of the variety of fluid flow mechanisms and gradients that affect the polymer
nucleation, aggregation, and alignment in solution at the front flow meniscus 16.

The various fluid flows and gradients that affect the polymer nucleation, aggregation and
alignment of the solution in the front meniscus are summarized in Figure 3. Complex fluidic
mechanism occurs during the process (e.g., Marangoni flow, capillary flow, etc.) Even if
physics is not fully described up to date, this technic is often used by academics and industries.
Almost of MGC techniques rely on contact between the solution and the part of the coating
equipment so that the meniscus is the liquid-air interface, where the solution, substrate, and air
16
form a three-phase contact line also called triple line . Immersion/dip coating, knife-over-
edge or blade coating, and slot-die coating are part of the MGC techniques.

a. Immersion/dip-coating
Immersion/dip coating is the most fundamental and simplest coating application. They are
classified as free-meniscus coating, which is done by withdrawing the substrate after its
immersion in the liquid that has to be coated. Even if dip-coating is a very usual technique to

20
form thin films onto the substrate, it is still a widely used method and one of the most efficient
ways to coat low viscosity soluble materials.
The thickness of the coated layer is the result of a balance of various forces acting on the
dynamic meniscus when the substrate is withdrawn from the liquid 17. Forces govern the shape
of the dynamic meniscus, and the thickness of the film due to the withdrawing velocity, liquid
rheology, and the surface tension of the fluid 18.
Dip coating can be separated into five steps, (a) immersion, (b) dwelling, (c) withdrawal, (d)
drying, and (e) curing (optional). Withdrawal and drying steps are the most critical. They
determine the quality of the coated film, as shown in Figures 4(a-d). The withdrawal step of
the dip-coating process allows the interaction of two categories of forces: draining and
entertaining forces. The balance between these sets of forces determines the thickness of the
wet film coated onto the substrate. The formation of the wet film can be broken into four
regions, as shown in Figure 4(e).

Figure 4. Schematic description of the dip-coating process (a) immersion, (b) dwelling, (c)
withdrawal, (d) drying, (e) four distinct regions that formed a dip-coated film.

Advantages and disadvantages of dip-coating technique may briefly organize as follow: Dip-
coating is a suitable technique to coat liquid for both sides of the substrate at once. It can be
used in research on protein, a protection layer, etc. The dip-coating technique can form a very
uniform thin film with nano-scaled roughness. However, this technique is limited to flat
substrates, and material shrinkage causes the films crack. Dip coating requires a reservoir of
21
solution for the substrate to be immersed. Furthermore, the variation of the withdrawal velocity
during the process allows obtaining a thickness gradient of the coated film.
To achieve a uniform coating, the volume of the solution must be far higher than the volume
of the substrate. In this way, dip coating can lead to a high quantity of solution wastage. As an
issue to overcome these limitations, the following knife-over-edge and blade coatings were
suggested.

b. Blade coating (Blading)

Blading techniques include doctor blading, bar coating, and knife-over-edge coating. These
techniques are popular solution-based coating methods in terms of cost and simplicity. All
blade coating processes have similar working principles. At first, the solution fluid is put in
front of the fixed blade or knife. The solution is spread-over by this fixed knife or the blade on
the substrate. In knife coating, a liquid material is deposited on the substrate, and the final
thickness of the coating layer is controlled by the small gap between the bar and the substrate.
The viscoelastic properties of the solution and the speed of the coating step will affect the final
thin film thickness. As shown in Figure 5, there are several blading variants called blade-over-
air or floating knife, which are slightly modified blade coating techniques.

Figure 5. Various types of blade (knife) coating, (a) floating knife coating, (b) knife over roll coating,
and (c) air-knife coating 19.

i. Floating knife coating (blade over the air) (Figure 5(a))

They are one type of knife coating, the substrate moving under the fixed knife by rollers. In
this variant, the knife touches the substrate. The doctor blade presses and moves over the upper
22
 20
surface of the substrate pushing the solution to be coated as a layer on the substrate. . The
sharpness of the blade, the alignment angle, and the distance between the knife and the substrate
influence the amount of coated materials 21,22.

ii. Knife-over-roll coating (Figure 5(b))

Unlike the floating knife coating, the knife-over-roll coating does not touch the substrate
because it is suspended above a roller. Precision thickness control is a great advantage of this
technology. However, poor thin film uniformity is a remaining issue to be solved 19,21,22.

iii. Air-knife (Figure 5(c))

The air-knife uses the interaction between the air jet and the liquid to control the film
thickness. This method is suitable for coating a rough surface with a low-viscosity solution.
Moreover, air knife coating has fewer contamination issues than the other blade coating
techniques because it is a non-contact technique.

Doctor blading is a well-suited technique for large-scale coating as well as the dip-coating
process. Moreover, this technique shows the following advantages: scalability, versatility, and
simplicity. Therefore, the doctor blade can entirely be used in industries and a wide range of
research fields (e.g., battery technology ceramics, thin-film electronics, etc.).
Note that, advantages and disadvantages of the blade coating technique may briefly be
organized as follow: first of all, the advantage of the blade coating technique is that the material
wastage during coating is less than dip-coating or spin coating. So, this technique could be used
to provide an inexpensive thin film at an industrial scale with high throughput. Moreover, the
technique is not constrained by the substrate, unlike the spin coating or the dip coating. In other
words, the solution material can be coated on rigid or flexible substrates. However, using
conventional doctor blade technology, the coated film cannot be patterned. Films thicknesses
< 10 μm cannot be easily reached.

c. Slot-Die coating
Slot-Die coating has excellent tolerance to ink viscosity with high throughput. The use of
slot die for coating processes is a prominent MGC technique for industry. As depicted in
Figure 6, an orifice (the slot) permits the flow of material through the die head onto a moving
substrate placed below. One advantage of slot die coating is that it is a pre-metered, continuous
23
process. The speed, and ink flow rate (e.g., controlled by a pump) determines the resulting thin
film thickness 16. The material is only deposited when a continuous pumping forms a meniscus.
In other words, the slot-die coating technique is totally controlled by a well-fitted meniscus
guide, and it is possible to regulate the thickness accurately.

Figure 6. Schematic illustration of slot-die coating relying on the meniscus formed between a coating
head with a slot in which ink is supplied forming a continuous (or striped) wet film 6.

Slot-die coating is a powerful technique that allows for the simultaneous deposition of tightly
grouped homogeneous stripes at speeds up to 100 m/min. The achievable thickness of the
coating thin-film is a function of solution viscosity, surface tension, coating speed, pumping
rate, and die head geometry 23. A key concern is determining the window of operating limits in
such vast parameters space 24.
Slot-die coating can be used for both development and manufacturing. The slot-die has
mostly been applied to photovoltaics (PVs) and light-emitting diodes (LEDs). Recently, the
double slot-die coating has emerged. To date, only OPVs have been addressed by a double slot-
die coating system. The double slot-die coating technique is a more low-cost process because
it reduces the processing time. Furthermore, it allows the deposition of two inks at the same
time. Up to date, this method is limited to two materials that can be deposited at the same
time 25.
The advantages and disadvantages of the slot-die coating technique may briefly be organized
as follow: the scalability of slot-die coating is a significant advantage. Additionally, it can be
used in R2R processing allowing an excellent uniformity of the coated film. The flow of
solution is very well-controlled with low waste. The slot-die coating technique can also be
24
applied to rigid or flexible substrates. Process speed is fast and accurate. However, this
technique is significantly more complex than the others because many parameters govern
deposition. As a result, process optimization requires the investigation of multiple parameters.

Drop casting
Drop-casting relies on the deposition of high-volume droplets with a controlled size that
spread and wet the surface upon impact. The drop-casting technique is a simple method to
deposit fluids onto a substrate. The evaporation step is a key factor in controlling the
morphology of the resulted film. This step is hard to control.
A variety of modifications that rely on the control of internal droplet flow have been
developed to enhance the quality of the deposited crystals and thin film, such as crystallization
26, 27
by ultrasonic substrate vibration-assisted drop-casting (SVADC) , solvent evaporation
control using mixed solvents, azeotropic mixtures 28, sealed chambers 29, 30, saturated solvent
environments 31, inert gas purging 32, and surface treatment 33.
The advantage of drop-casting is that no complex equipment is needed apart from a very
horizontal working surface. Indeed, the procedure is to cast a solution onto a substrate followed
by a simple drying process. It is possible to prepare films with good quality and thick films.
However, the technique suffers from a lack of film thickness uniformity along with its profile.
Such an effect will be deeply discussed in the section dealing with the drop on demand inkjet
printing.

Printing
The term « printing » must be used with care because it exists many variants of printing
technologies. However, they have a common goal that is to fabricate patterns using the solution
process at high throughput over a large area. Printing can be classified into two types, as shown
in Figure 7.

25
 Figure 7. Classification of printing technologies.

Contact and non-contact printing: in contact printing, the patterned structure and the ink
surface have physical contact with the substrate. For non-contact, the solution is dispensed
through aperture (e.g., nozzles), and the patterns are defined by moving the stage (substrate
holder) or the print-head. The most common contact printing techniques are screen, gravure,
offset, and flexography printing, while the most common non-contact printing techniques are
aero jet printing and inkjet printing.

1. Contact - printing

a. Screen printing
Screen printing consists in the deposition of material on a substrate through a meshed screen
by squeezing 34. The fluid ink is pressed through the open mesh and squeegee applies a physical
force that forces the ink to pass through the open mesh. Screen printing is also called: stencil
process. Fine meshes, such as natural silk, plastic, or metal fibers/threads, are used as the screen.
Screen printing is extensively used in electronics since it has been adapted from graphic art to
fabricate conductive patterns (typically using silver pastes), resistors (using carbon films),
capacitors (using polyimide dielectrics), etc. It is mainly used for printed circuit boards 35.
The screen printing process enables ink deposition onto rigid surfaces as well as a flexible
substrate. Inks must be selected accordingly to the surface characteristics (mainly surface
roughness and surface tension) of the printing substrates 36. Low viscosity ink cannot be used
in the screen printing process, because it easily escapes from the screen by capillarity. Thus,
ink requirements should have a high viscosity (typically > 1000 cP) and a low boiling point
solvent Additionally, the ink can be classified into four types; evaporative (solvent-based),

26
oxidizing, catalytic, and UV inks. Thus, many inks can be used according to the previously
mentioned drying conditions.
37
In practice, the screen printing technique is categorized into three methods , shown in
Figure 8:

- The flat-to-flat method (flatbed): the printing plate and the printing substrate are both
flat; the ink is transferred through the mesh apertures onto the printing substrate by the
movements of a squeegee, (see in Figure 8(a)).

- The screen printing on a curved surface: the printing plate is flat, while the printing
substrate is fixed or wrapped around a rotating cylinder. The ink that passes through the
mesh apertures using a squeegee as for flatbed, (see in Figure 8(b)).

- The round-to-round method (rotary printing): the printing screen is cylindrical; the
printing plate, printing substrate, and pressure cylinder move synchronously. The ink is
transferred through the cylindrical printing plate and onto the substrate, (see in
Figure 8(c)).

Figure 8. Schematics of screen-printing processes. (a) flat-to-flat method (flatbed screen printing),
(b) screen printing on curved surface, (c) round-to-round method (rotary screen printing) 6.

The advantages and disadvantages of the screen printing technique can be summarized as
follow: screen printing is not only used for electronic fabrications but has been also used in
various industries proving the versatility of this technology. The most significant advantage of
screen printing is that almost any substrates can be used, including paper, plastic foils, textiles,
27
wood, metal, ceramics, glass, and leather. In theory, there are no ink losses during printing.
However, screen printing is mainly limited by the viscosity of the ink. Polymer binders are
added to provide high viscosity ink. However, it can be a critical issue for the electronics,
because binders can damage semiconductor introducing excessive leakage and dissipation in
dielectrics, or degrading the conductivity 38. Moreover, the sub-micrometric thick layer cannot
be achieved. Indeed, in standard processing conditions, the typical film thickness is several
tenths of micrometers.

b. Gravure printing
Gravure printing is one of the oldest printing technologies as screen printing. Generally, the
gravure printing equipment consists of the following components: the gravure cylinder, the
impression cylinder, the doctor blade, the coating bath. Schematic description of the gravure
printing process is shown in Figure 9.

Figure 9. Schematic description of the gravure printing process 6.

Printing is carried out directly from the image carrier, which is called a gravure cylinder. A
concave shape has been engraved at the surface of the gravure cylinder. The ink is transferred
from the engraved micro-scaled open hole and not from the concave shape. These micro-scaled
open holes, embedded in the gravure cylinder, form the printing patterns. A second impression
cylinder, made of soft material, pushes the substrate against the gravure cylinder. Thus, the ink
is transferred from the open holes to the substrate through appropriate surface energies choice
between the ink and the substrate. Note that the gravure cylinder is partially immersed in the

28
coating bath and as it rotates before printing, the entire surface of the gravure cylinder (both
the printing and the non-printing elements) is inked. Furthermore, a doctor blade removes any
excess of ink from the areas of the non-image elements, so only ink remains in the open hole 39.
The engraved patterns shape and thickness mainly control the amount of material deposited
to the substrate. Using gravure printing more ink can be transferred than in most of the other
printing technologies. Various patterns can be fabricated such as regular dot, net structured,
40
rhomboid patterns, etc. Gravure printing is highly governed by the ink viscosity and the
rotating speeds of both cylinders. Low ink viscosity (5-25 cP) is mandatory and high printing
rates up to 15 m/s can be reached.
The advantages and disadvantages of the gravure printing technique may briefly be
summarized as follow. Gravure printing allows high printing quality and speed. Moreover, it
41–43
is a simple printing process, accurate and low consumption of the ink is required . Thus,
this technique is in agreement with ‘fully additive’ printed electronics for mass production.
Moreover, gravure printing technology allows the deposition of various film thicknesses in a
single run. Due to the cylinder cost, gravure printing is less competitive in terms of production
costs than the other printing technologies, especially when a low amount of device fabrication
is targeted.

c. Flexographic printing
Flexographic printing technique is an example of a convex direct printing. Generally, the
printing unit of the flexographic machine consists of a plate cylinder, pressure cylinder, anilox
roller, fountain roller, and doctor blade (see in Figure 10). The flexography is similar to the
gravure printing except that the printed image stands up on the printing roller, the surface of
which is typically made from rubber 44. The process can be described as follow.

29
 Figure 10. (a) schematic description of the flexography printing process, the ink transfer from (b)
anilox cylinder to printing plate cylinder, (c) printing plate to substrate 6.

Inking is carried out by a fountain roller that is partially immersed in an ink bath. The ink is
transferred from the bath to an anilox roller (a roller that has engraved patterns everywhere).
The anilox roller is engraved and controls the amount of ink that is delivered to the printing
plate cylinder. The excess of ink from the surface of the anilox roller is removed by a doctor
blade and leaves open holes filled with ink. Likewise, the anilox roller plays a crucial role. It
is typically fabricated using chrome-coated ceramics or stainless steel. When the anilox roller
and the printing plate cylinder are in contact, ink is transferred from the anilox roller to the
surface of the printing plate cylinder by surface tension. Next, the printing plate cylinder prints
the patterns to the substrates because the impression cylinder presses the substrates onto its
surface.
In flexographic printing, the substrate is flexible and requires a well-regulated pressure
between the substrate and the pressure cylinder to prevent damage. It is called “kiss impression.”
If the pressure is too high, it can lead to a "halo" phenomenon. The halo effect refers to a
phenomenon where the desired patterns are surrounded by an area depleted or void of ink that
is surrounded by a fringe of ink excess 45. On the contrary, insufficient pressure in the printing
area causes a lack of contact between the printing plate and the substrate, and as a result, the
pattern is not printed 46. The selection of an appropriate ink is crucial to determine the printing
quality. In the flexography printing process, two kinds of inks are available: solvent-based ink
30
and UV-curable inks. Generally, the ink for the flexography printing process uses a low-
viscosity (0.05-0.5 cP) ink, and high-solvent content except for UV-curable inks.
The advantages and disadvantages of flexographic printing technique may briefly be
organized as follows:
Flexographic printing is well-known as a convenient technique for high-speed production.
Various kinds of ink can be used as well as flexible substrates, including plastic, metallic films,
paper, etc. Flexographic printing allows an extremely thin printed layer, with a thickness of
0.04-2.5 μm and throughput from 3 to 30 m2/s. High production volumes and the fast process
runs with the in-line processability leading to significant in cost reduction. On the downside,
flexographic printing cannot produce complicated printed electronic circuit, compared to
gravure printing. Besides, as above-mentioned that the flexography is very susceptible to halos
phenomena due to ‘donut’ shape printing rather than a ‘dot.’ Even if flexography is a promising
technology, up to date, only a few works are reported in the literature. As a consequence, only
a few applications such as sensing 47, RFID tags 48,49 have been reported in electronics.

d. Offset lithography printing

The term ‘offset’ comes from “set-off,” which symbolically shows the method of
transferring the patterns to the substrate directly from a silicon blanket. In other words, the
plate cylinder is not directly in contact with the substrate, as shown in Figure 11.

Figure 11. Schematic description of offset lithography printing process 42.

31
 The offset printing technique can be described as follow: basically, the first step in the offset
printing process is to pattern two physically/chemically different areas on a printing plate
cylinder: a nonprinting one (oleophobic) and a printing one (oleophilic), respectively. They are
provided thanks to different physical/chemical surface properties, playing with surface
engineering (e.g., omniphobic coating) 50. The difference of surface energy between
nonprinting and printing areas allows depositing water and ink onto the plate cylinder
selectively. Thus, the ink on the printing plate is directly transferred to the silicon blanket, and
finally, from the silicon blanket to the printing substrate.
Offset printing inks can be dried purely physically (absorption and vaporization), purely
chemically (polymerization through ultraviolet (UV) emission, polymerization through
electron or oxidation by atmospheric oxygen) or both 51. Offset printing inks are highly viscous.
Offset printing is a fast printing process that gives high throughput and excellent resolution.
Also, the printing plate has a longer lifetime than contact printing, such as screen printing,
because there is no direct contact between the plate and the printed surface. Properly developed
plate cylinder used with optimized inks and fountain solution can allow reaching more than a
million impressions. Thus, offset printing is the cheapest method to produce high-quality
patterns. The advantages are much more than the disadvantages. These include the cost related
to the fabrication of the printing plates. Finally, the printing plate cylinder is made of anodized
aluminum, making it vulnerable to chemical oxidation, so they need some extra care and
maintenance.
Offset printing is a widely used method for mass-production. For instance, it has been
52
intensively used to make color filters for the OLED display . Nowadays, it has gained
attention because of its capability to reach high pattern quality with a thin and smooth surface.
Furthermore, this technology has been improved and combined with other printing techniques
to give birth to novel innovative technologies, also called: reverse offset, screen offset,
gravure offset, etc.

2. Non - Contact - printing

a. Aerosol jet printing (spray deposition)

The aerosol jet printing (AJP) is an emerging technology based on the spray deposition
working principle, and this technique is part of non-contact printing technology. AJP is
32
considered as a counterpart printing technology to the inkjet printing (IJP) technology because
of its main characteristics: the direct writing onto a wide range of substrates. The term ‘aerosol’
is, by definition, a solid (particle) or liquid (droplet) dispensed in a gas phase.

Figure 12. Schematic of the aerosol jet printing system using pneumatic atomization 53.

As shown in Figure 12, AJP uses a directed aerosol stream to provide material deposition at
a nozzle-substrate distance of 1 to 5 mm 53. The AJP utilizes a focusing technique, so-called
Aerodynamic focusing, which makes the use of two nitrogen (N2) flows. The atomizer gas
stream carries the aerosol from the atomizer to the nozzle 54, 55. A secondary N2 flow allows a
coaxial stream at the nozzle. Moreover, the print-head can be motorized along with 4 axes (x,
y, z, and theta) allowing the material deposition in 3D (see the Optomec© equipment). Two
different aerosol generators (atomizers), pneumatic or ultrasonic, can be implemented into the
printing equipment.
The pneumatic atomizer is described in Figure 12. It can use inks with viscosities in the
range of 1000 cP, but the uniformity in terms of particle dispersion of the resulting aerosols is
poor in this case and requires additional flow purification steps before the deposition. The
ultrasonic atomizer can also produce very uniform aerosols when using low fluid volume, but
56
the required ink viscosity is in the range of 10 cP . Due to the high number of crucial
experimental parameters (e.g., surface tension, viscosity, evaporation, the density of materials,
etc.), the aerosol printing technology is hard to master and thus remains a challenging technique.
In the case of pneumatic atomization, liquid surface tension, viscosity, volatility, and density

33
of the material determines the range of droplet sizes. The aerosols with ultrasonic atomizer
typically have a dispersity and a volume of a droplet ranging from 2 to 5 μm 57.
Additional key points can affect the film formation of the AJP, including the apparatus, the
process, and the design, the substrate and the environmental factors that are more challenging
to control. These factors have been investigated, and they are recently more clearly defined 58–
60
. Moreover, the focusing ratio (FR) of the sheath gas flow rate to the carrier gas flow rate is
61,62
a key printing parameter to achieve fine-line features . If the FR is low, the line is broad
and not accurately defined. Increasing the FR improved the deposition quality, yielding to lines
with more accurate edges. In this way, an optimum window for deposition could be
determined 59.
The advantages and disadvantages of the aerosol jet printing technique may briefly be
organized as follow. The main advantages of AJP include fine pattern control enabling the
precise deposition of micro-scaled patterns. In other words, it means that the AJP has the
highest resolution compared to the other solution processes technologies. Indeed, AJP can
reach resolutions that are almost 2-4 times higher than inkjets (the AJP processed features can
be as small as 10 μm). In terms of the ink viscosity, AJP can be considered as a versatile
technology because a wide range can be used (ranging from 0.5 to 1000 cP).
As already discussed, due to the distance between the nozzle and the substrate, AJP is
compatible with nonplanar (i.e., non-flat, non-smooth) substrate. It allows printing on stepped
or curved surfaces. In addition to these many advantages, AJP is also suitable for thick layer
printing. The edge sharpness of the deposited layers is often low, because of the satellite
droplets, due to the unstable focusing ratio of AJP, in comparison with inkjet printing. Also,
this technique has difficulty in securing adequate performance, especially for large-area
processing due to the satellite droplets. Above all, AJP is much more expensive than other
technologies, especially inkjet printing, due to the additional components required to generate
the droplet mist and focused carrier gas streams.
The state of the art of the AJP has been reported as a fabrication technique for the printed
electronics such as flexible displays 63, thin-film transistors 64, circuits 65, multilayer ceramic
capacitors (MLCCs) 66, and biological sensors 67.

34
 b. Inkjet printing
Inkjet printing (IJP) is an emerging technology currently one of the most studied techniques
for producing low-cost printed electronics onto a wide range of substrates. The IJP technique
has belonged to the category of non-contact printing as well as the Aerosol-jet printing
technology. It allows the deposition of materials only at the desired location using a digital
design. In other words, the IJP technique is the most effective printing technology for enabling
direct writing, and it has a suitable technology for a solution-based additive process. The two-
dimensional pattern relies on a pixelated drawing where each pixel is either left blank or
receives an ink drop. In specific cases, it is also possible to work in 3D by printing multiple
layers 68. IJP technology is the adopted technology in this thesis. This section will introduce in
detail: IJP system, basic principle (advantages & disadvantages), key printing parameters,
methodologies, etc.

i. Inkjet printing system (drop after drop)

Figure 13. Classification of various Inkjet printing technologies.

This technology can be classified into two different types according to the drop generation
method, as shown in Figure 13, the continuous inkjet (CIJ) type and drop-on-demand (DoD)
inkjet type can be distinguished.
CIJ printing technique supplies a continuous stream of ink droplets that are charged upon
leaving the nozzle and then deflected by voltage plates. The applied voltage governs the
location of the droplets on the substrate, and part of droplets are recycled through a gutter 69.
The CIJ printing, it still widely used due to its useful advantages in an industrial environment.
However, the droplets generated using the CIJ printing technique have very large drop-size,
35
droplet diameter of approximately 100 μm, the printing area is limited, and the printing
resolution is relatively low. Moreover, the ink can be re-used. Furthermore, the initial costs for
the CIJ printing machine are relatively expensive.
By using electrostatic forces as the droplet deflection method, the ink droplets are deposited
at the desired position. The CIJ printing system can be divided into four different types: such
as the binary deflection, multiple deflections, Hertz and microdot printing. In the binary
deflection system, the ink droplets are either charged or uncharged. For multiple deflections
CIJ printing, each droplet has different electrical charges. Thus, when different ink droplets
pass through a fixed electric field, they are deflected in multi-directions. The uncharged
70,71
droplets returned to a gutter and are reused (re-circulation) . In this way, the multiple
deflection system can perform faster processes than a binary deflection system. More detailed
about Hertz CIJ printing and Microdot CIJ printing, which is another classification of CIJ
printing, can be found in literature 71.

Figure 14. Schematic of inkjet printing technology and its film formation methodology.

The term “DoD” refers to the fact that the droplets are ejected from the nozzles using
pressure pulse allowing drop jetting when it desired (drop by drop). This technique can be
classified as a function of the mechanisms of ink ejection from the nozzles: thermal,
piezoelectric, electrostatic, and acoustic inkjet printing 72–75.
Among these types of DoD IJP technologies, piezoelectric IJP is the most commonly used,
as it is suitable for the wide range of printing materials, including polymers, colloids in
36
suspensions, biomaterials, etc. The piezoelectric transducer is placed on top of a membrane, in
the print-head. In other words, the print head uses a piezoelectric ceramic actuator to dispense
the ink out of the nozzle drop by drop 68,76.
As shown in Figure 14, an applied voltage pulse: the so-called ‘firing voltage,’ governs the
deformation of ink droplets. The firing voltage is applied to the piezoelectric actuator and then
induces a pressure wave within the ink chamber and dispenses a droplet of ink out of the
nozzle 77. Compared with thermal nozzles, piezoelectric actuated nozzles generally have better
advantages, excepting the cost. For instance, the resolution is relatively better, it provides a
low-temperature process. In conclusion, the piezoelectric IJP has sufficient features to address
key issues in the field of printed electronics. Unlike thermal nozzles, the material is not
recycling (no-recirculation), so that no ink degradation occurs.

To summarize, the main advantages and drawbacks of IJP technique 78 can be listed as follow:

< Advantages of IJP technique >

- IJP technology can be easily applied at any production scale, from rapid circuit
prototyping on small substrates to large areas for large-scale production.

- The IJP is a digital technique. Easy and quick, the patterns design is simply carried out
via software. This feature can make excellent economic benefits, especially in
comparison with other technology such as gravure printing or conventional
photolithography, where hard masks are mandatory.

- This technology is quite an eco-friendly process. It is characterized by the feature of low

consumption with less waste of materials. In general, the average volume of cartridge
for an inkjet printer is in the range of a few mL (at a laboratory scale). Moreover, the
typical volume of one droplet is a few pico-liters. In terms of the use of the cartridge, it
can be free from considerations about ink degradation, comparison with the re-cycling
printing techniques (e.g., gravure).

37
 < Drawbacks of IJP technique >

- As the other printing technologies, despite their great potential, the IJP technique has
suffered from a lower resolution than aerosol printing. The reason for the low resolution
of the IJP technique is due to the diameter of typical droplets within the range of the tens
of micrometers. Generally, the low viscosity and surface tension of the inks cause the
drop to spread after being deposited on the substrate, which limits the resolution of
inkjet-printed patterns (30-50 µm, typically).

- Additionally, printing speed is slower than many printing technologies such as gravure
44,79
printing , and it is related to the low throughput speed of this technique. However,
this throughput is corresponding to the case of using only a single nozzle. To date, IJP
already has a solution to overcome the limitation of throughput using multiple cartridge
disposition print-head. However, its complexities the equipment.

ii. Key steps of inkjet printing; Jetting, spreading, wetting, and drying.
In this thesis, Ceraprinter X-series (from CERADROP©) is used as a DoD inkjet printer. It
uses a piezoelectric system. In the following description, we will present the key steps of this
process. The typical IJP process can be divided into three steps; 1) generation and ejection of
the droplet, 2) interaction of the droplets and the substrate, 3) drying of the droplet and
formation of the solid materials.

① Generation and ejection of the droplet

The ejection of a droplet is governed by the shape of the voltage pulse signal (i.e., the jetting
waveform), which is applied to the piezoelectric transducer on the nozzle. However, the factors
for achieving a fine-droplet include not only such jetting waveform but also the physical and
chemical properties of the solution (ink) such as viscosity, surface tension, density, etc.
Stable drop formation without satellite droplets after ejection from the nozzles is essential to
achieve high quality printed patterns. Droplet generation is controlled by a jetting waveform
defined by amplitude (± applied voltage) and times applied onto the piezoelectric. The shape
of the jetting waveform defines droplet formation, ejection speed, drop volume, etc., but it also
can be optimized into a complex waveform depending on the properties of the ink. In the initial

38
state, the ink in the nozzle is at equilibrium. When the ink is pushed out from the cartridge due
to the volume expansion induced by the piezoelectric system, an in-flight droplet is jetted after
the pressure inside the cartridge reaches a threshold (i.e., enough force to be jetted).
Figure 15 shows the typical jetting waveform used throughout this study. This jetting
waveform can be divided into four steps.

Figure 15. Typical form of the voltage signal applied to piezoelectric elements to form a drop: the
evolution of the working voltage as a function of time.

Droplet is formed on positive actuation voltage (trise + tdwell) in step 1. Then, droplets are
dropped with the actuation voltage decreases from positive to negative (tfall) in step 2, the
droplet splits and begins to be jetted from the nozzle. Negative actuation voltage-time (techo)
has been fixed at twice of tdwell to avoid residual deformation waves after ejection of each drop
(step 3). Ejection is then stopped, and the suction effect immediately occurs, pushing the
additional ink back towards the nozzles. Then, negative actuation voltage increases to positive
actuation voltage (trise) to allow another droplet formation in step 4. In this final step, the voltage
returns to its original value (= V0), which induces the relaxation of the piezoelectric element.
Note that tfall and trise should be as short as possible not to disturb the formation of the drop and
avoid excessive volumes. Jetting waveforms affect the maximum jetting frequency and
reproducibility of a stable droplet formation. In addition to the jetting waveform, jetting
frequency is also a crucial parameter that must be considered for stable drop generation and

39
ejection. Drop misalignment during jetting, satellite droplets, spraying, etc., were frequently
reported as non-desirable phenomena mainly due to inappropriate jetting parameters.

② Fluids requirements for printable ink

As mentioned above, the physical-chemical properties of the solutions (inks) also have a
strong influence as well as the jetting waveform and frequency. Optimized ink formulation
leads to stable ejection and improves the accuracy of the patterns. The well-formulated inks
allow the formation of droplets without unstable droplet configurations as a satellite or long
filament. Moreover, this understanding can also prevent nozzle clogging, resulting in
reproducible processing conditions.
The printability of ink is primarily governed by three physical parameters: surface tension,
density, and viscosity. Their correct values also depend on the print-head and nozzle geometry.
The usual ranges of the viscosity and surface tension of the ink are suitable for piezoelectric
ink-jet printing range from between 5-20 cP and 25-35 mN/m, respectively. The behaviour of
drops can be predicted by dimensionless numbers based on the Navier-Stokes equation 80. The
Reynolds (Re), the Weber (We), the Capillary (Ca), and the inverse Ohnesorge number (Z) are
frequently used to characterize the droplet formation.

𝑖𝑛𝑒𝑟𝑡𝑖𝑎𝑙 𝑓𝑜𝑟𝑐𝑒 𝜌𝜈 2 𝑑2 𝜈𝜌𝑑 …................... Eq. 1.1

𝑅𝑒 = = =
𝑣𝑖𝑠𝑐𝑜𝑢𝑠 𝑓𝑜𝑟𝑐𝑒 𝜂𝜈𝑑 𝜂

𝑖𝑛𝑒𝑟𝑡𝑖𝑎𝑙 𝑓𝑜𝑟𝑐𝑒 𝜈 2 𝜌𝑑 2 𝜈 2 𝜌𝑑 …................... Eq. 1.2

𝑊ⅇ = = =
𝑠𝑢𝑟𝑓𝑎𝑐𝑒 𝑡𝑒𝑛𝑠𝑖𝑜𝑛 𝛾𝑑 𝛾

𝑣𝑖𝑠𝑐𝑜𝑢𝑠 𝑓𝑜𝑟𝑐𝑒 𝜂𝑣𝑑 𝜂𝑣 …................... Eq. 1.3

𝐶𝑎 = = =
𝑠𝑢𝑟𝑓𝑎𝑐𝑒 𝑡𝑒𝑛𝑡𝑖𝑜𝑛 𝛾𝑑 𝛾

√𝑖𝑛𝑒𝑟𝑡𝑖𝑎𝑙 𝑓𝑜𝑟𝑐𝑒 × 𝑠𝑢𝑟𝑓𝑎𝑐𝑒 𝑡𝑒𝑛𝑠𝑖𝑜𝑛 √𝛾𝜌𝑣 2 𝑑3 √𝛾𝜌𝑑 ...................... Eq. 1.4

𝑍= = =
𝑣𝑖𝑠𝑐𝑜𝑢𝑠 𝑓𝑜𝑟𝑐𝑒 𝜂𝑣𝑑 𝜂

Where the symbol ρ is the density of the ink (kg/m3), d is the diameter of the nozzle (m), ν
is the travel velocity of the ink (m/s), η is the dynamic viscosity of the fluid (cP = Pa.s), and γ
is the surface tension of the ink (N/m), respectively. Z has been identified as the standard for
40
defining the range of ejection stability. For instance, the stable drop formation can be observed
81
at Z > 2 in the case of DoD inkjet printing . If the Z value is less than 1 (Z < 1), droplet
formation is not possible. Ink with too high Z values resulted in low-quality printed structures
as well. Consequently, finding the most appropriate Z value and ensuring the conditions of
printable fluid through experimental analysis are the methods to ensure accuracy and high
resolution. Thus, it can be established map in a parameter space that can be used to predict if
the fluid is printable, as shown in Figure 16 80.

Figure 16. Schematic illustration of mapping in parameter space, with coordinates Re and We, to
define fluid properties that are usable in DOD inkjet systems. (The limiting value of Z is equal to
1/Oh) 80.

③ Interaction of the drop and the substrate (spreading, wetting and drying)

- Spreading

Figure 17. Schematic representation that different stages of the interaction between a drop and a
substrate, and selected snapshots are referred from 82.
41
 When the droplet comes into contact on a dry solid surface, 4 steps can be distinguished.
This impact process sequentially deforms a droplet, and this deformation can be divided into
the three phases, as shown in Figure 17;
The drop has a diameter (D) after ejection from the nozzle after ejection (Figure 17(a)), and
these in-flight drops falling to a substrate with relatively high velocity (υ) and make contact
(Figure 17(b)) in the 1st phase. After impact, the droplet immediately deforms, flattens, and
spreads on the substrate in a 2nd phase. Consequently, the final droplet diameter is higher than
the initial one (D1). Moreover, the drop diameter is related to the surface wetting and the impact
conditions. Furthermore, periodically rapid radial fluid flows regularly followed by interfacial
vibrations are inherent properties of the phase (depicted in Figure 17(c)). For the final phase
of the impact process, the fluid stops spreading and stay at rest or recoils. Finally, the drop
finishes the deformation with the diameter (D3) and starts to evaporate solvents, which has an
equilibrium shape and position on the substrate (because it minimizes its energy), as shown in
Figure 17(d) 80.
Drop spreading influences the thickness of the layer, the lateral resolution of materials, and
the accuracy of the printed patterns. Drop spreading can be estimated using the following
Equation 1.5 83.

…..................... Eq. 1.5

𝐷𝑀𝑎𝑥 𝑊𝑒 2 + 12
= √( )
𝐷 4𝑊𝑒 2
3(1 − cos 𝜃) +
√𝑅𝑒

Where Dmax is the maximum drop radius, D is the in-flight drop radius, θ is the contact angle
of the drop-in equilibrium shape the static contact angle. We are the Weber number, and Re is
the Reynolds number.

- Wetting

Wetting properties are related to the ability that the droplet can be spread up to a certain
point: “the equilibrium.” Wetting is an important parameter that defines the resolution of the
printed pattern. To understand the relationship between drop and substrate in each phase,
Young-Dupre`s law can be used. The following Equation 1.6, can be applied for a system
composed of a substrate, air, and liquid.

42
 S = 𝛾𝑆 − (𝛾𝑆𝐿 + 𝛾𝐿𝑉 ) …..................... Eq. 1.6

Where S is the spreading parameter, γS, γSL, γLV are the interfacial tensions of solid/air,
solid/liquid, and liquid/air, respectively.

Figure 18. Different behaviour of a drop on a substrate by the function of surface tension. The high
surface tension of (a) complete wetting, the low surface tension of (b) partial wetting and (c) non-
wetting.

Figure 18 describes three behaviours of droplet wetting, such as complete wetting, partial
wetting, and non-wetting. The drop has different spreading according to its wetting properties,
and it can be distinguished by contact angle and droplet radius. As a result, the surface tension
of the droplet and surface energy of the substrate can affect the wetting. Wetting behaviours
can be described as follow:

✓ S > 0, “complete wetting”: in complete wetting behaviour, the surface energy is

high and contact angle θeq approximately equals 0. In other words, the substrate has
a high surface energy that forces the fluid to wet the surface totally. In the case of
complete wetting, it is easy to print ink because it is firmly pinned to the surface.
However, the printing has a poor resolution (the higher DMAX.).

✓ S < 0, “partial wetting”: partial wetting behaviour, can be divided into two different
regimes. The drop only partially spreads and equilibrates to have a semi-spherical
shape or quasi-spherical shape according to the contact angle θeq formed at the
interface between the air, the liquid, and the substrate, as shown in Figures 18(b)
and 18(c).

43
  In the case of ~20 ° < θeq < 90 °; the wetting surface is suitable, and the liquid
spreads widely over the surface. In other words, the substrate is hydrophilic, and
this partial wetting condition is suitable for the printing process with excellent
uniformity. However, it also can lead to low resolution because of the high spreading
(i.e., high droplet diameter).

 On the other hand, in the case of 90 < θeq ≤ 180 °; the substrate ranging from
hydrophobic to super-hydrophobic, and this condition is qualified as non-wetting.
This non-wetting condition results in a high contact angle leading to small droplets
diameter. Therefore, this condition can cause a discontinuous layer because of
pattern dewetting (i.e., when the droplet baseline is generally not firmly pinned).

Various surface treatments can control these wetting conditions. In physical surface
treatment, O2-plasma or UV-ozone (UVO3) treatments are typically used to make suitable
surface energy for the printing process. In chemical surface treatment, a self-assembled
monolayer (SAM) can also be used to reach the desired surface energy for the printing process
as a hydrophilic/hydrophobic surface.

- Drying

The transforming liquid (inks) to the solid phase is called: the drying step. This step is crucial
to understand the morphology of the resulting in printed patterns. Drying can be described in
more detail, including evaporation, solidification, polymerization, chemical composition.
The printed drops are begun to dry on the substrate. When the drops are dried, they are
actively governed by a well-known phenomenon called: the coffee-ring effect. The principle
of the coffee ring effect is illustrated schematically in Figures 19(a-c). For instance, the results
of the coffee ring effect according to the heating temperatures are shown in Figures 19(d-g).
The coffee-ring effect occurs when printed drops contain particles (solution materials). The
solvent in ink evaporates, the droplets tend to shrink because droplet volume decreases and at
the same time, the droplet minimizes its energy. Consequently, particles are transported by a
radial flow, which is induced by liquid that evaporates from the center of the drop towards the
edge of the drop. For the next step, the transported materials tend to concentrate on the edge of
the drop, and this concentration makes a thicker edge. Consequently, the center of the drop has
relatively less amount of particles and thinner thickness. As a result, this dried drop forms the
44
well-known coffee ring-shape. Note that, the coffee ring effect occurs only the droplet edge
(the triple line) is pinned.

Figure 19. Schematic representation of the coffee ring effect (a) evaporation of the solvent, (b)
transporting materials (recirculation flow), (c) formation of coffee ring-shape. Drop morphology
control using heating temperature. Dried Su-8 (polymer) as a function of the heating temperatures of
the substrate: (d) 25 °C, (e) 37 °C, (f) 50 °C, and (g) two-dimensional profile of each morphology, refer
from 84.

The coffee ring effect can be cause poor resolution due to the morphological change, such
as non-uniform device and non-fine (not continuous) pattern. However, temperature control
(heating or cooling) of the substrate can minimize the evaporation rate of the solvent. After
drying, the deposit must be sintered (in the case of metallic particles) to develop the desired
microstructure and electrical properties by heating.

III.Conclusion
A general overview of different types of solution processes has been described in Chapter 1,
including drop-casting as well as various types of coating and printing technologies. The future
development of all solution process represents promising possibilities for new electronics, such
as rigid/flexible electronics at low cost fabricated over the large area at high throughput. The
advantages and disadvantages of the solution process have been organized and compared. This
chapter also describes a crucial aspect to consider for the definition of inks associated with
physicochemical properties and rheological behaviour.
45
 Among these solution processes, DoD inkjet printing technology is chosen for a remarkable
and suitable technology for the fabrication of printed electronics. Additionally, inkjet printing
is far cheaper than the other printing technology which is a target for the industry.
Moreover, this chapter has also been devoted to the study of the theories of the inkjet printing
process, including a classification of the types of the inkjet printing process. Furthermore, the
various inkjet printing techniques are classified according to the method of drop generation.
Moreover, both of upper categories, as CIJ and DoD inkjet printing, are described and
compared. In this work, DoD as chosen for the more suitable inkjet printing technique to
fabricate printed electronics. In the next part, materials and device processing will be deeply
studied according to the three key steps of inkjet-printed drops. The jetting, spreading, wetting,
and drying behaviour of drop has also been studied to highlight the crucial allowing to fabricate
a well-defined pattern.
In particular, the non-contact printing techniques have been highlighted due to their definite
possibilities such as low wastage and low consumption of materials, fast and straightforward
process, a better implementation for the pattern with higher resolution, easy control, and
adaptability to the commercialized process. All kinds of contact and non-contact printing
technologies with their advantages and disadvantages are summarized in Table 1.

46
 Table 1. The main advantages and disadvantages of different printing techniques. Printing
techniques are defined by contact type and non-contact type printing 19,41,53,56,58,60,72,74,76,78.

Printing Advantages Disadvantages

techniques
- Substrates can be either flexible or - Only highly viscous or paste-like
rigid. inks can be used.
- Repeatable and precise printing of - High surface roughness.
Screen electrical components. - Complex setups and preparations
- Suitable for mass production of before printing; high initial cost
printing
patterning components on large area - Low resolution.
substrates.
- Thick layers can be reached (>10
μm)
- Fewer limiting constraints compared - Planar printing process, not suitable
to offset lithography or flexographic for printing on non-planar surfaces.
printing. - Materials with compressible and
- Mechanically straightforward flexible properties are more
Gravure process. preferred, thick and rigid substrates
Contact type printing

- High speed may not be applicable.

printing
- Well-suited for the mass production
of printed electronics.
- Capable of printing different ink
layer thicknesses on the substrate in a
single run.
- Allows compressible substrates
surfaces, pressure-sensitive foils, and
metalized films to be printed.
Flexographic
- High printing speed.
printing
- Complex setups and preparations
prior to printing; high initial cost.
- Planar printing process, not suitable
for printing on non-planar surfaces.
- Flexible and thin substrates are
preferred, thick, and rigid substrates
may not be suitable.
- Complex setups and preparations
prior to printing; high initial cost.

- High printing speed. - Not practical for small quantities

- Good image resolution. productions as the printing plate
- Suitable for mass production. cylinder had to be fabricated for
- High throughput. every unique print job.
- Planar printing process, not suitable
Offset
for printing on non-planar surfaces.
lithography - Flexible and thin substrates are
preferred, and thick and rigid
substrates may not be suitable.
- Complex setups and preparations
prior to printing; high initial cost.

47
 - Contactless, mask-less, and digital - Sheath gas required in the printing
method. process, and this may increase the
- Do not require pre-manufactured operating cost.
master printing plates. - Lower throughput as compared to
- Decrease the possibilities of conventional printing techniques.
contamination and damage of the - Nozzle clogging.
printed materials.
- No issues regarding the clogging of
nozzles. Wide material options
Aerosol jet (metal, dielectric materials,
graphene, carbon nanotubes.
printing
- High-resolution printing.
Non-contact type printing

- Printings on orthogonal and non-

planar surfaces are possible.
- Substrates used can be either flexible
or rigid. They are allowing multi-
materials and multilayer printing
designs.
- A wide range of inks viscosities can
be printed, typically in the range of
1–1000 cP.
- Contactless, digital, and mask-less
method.
- Do not require pre-manufactured
master printing plates.
- Lower contamination and damage to
printed devices.
- Low material waste.
Inkjet
- Substrates used can be either flexible
printing or rigid. Allows multi-materials and
multilayer printing designs
- Clogging of nozzles is one of the
common problems.
- Only low viscosity ink and a specific
range of surface tensions are allowed.
- Multiple layers must be printed in
order to achieve the desired
thickness.
- Unfavorable to non-planar substrates.
- Incapable of operating at extremely
high frequencies applications due to
inkjet printing’s resolutions.
- Lower throughput as compared to
conventional printing techniques.
- Coffee-ring effects are hard to
control.

48
49
 Chapter 2: Printed Organic Thin Film
Transistor
Chapter 2 focuses on Printed Thin Film Transistor. Each section is dedicated to give general
information about thin film transistors and a review on recent progress on materials used in
inkjet printing technology.
Section 1 is dealing with the theoretical elements of TFTs. This section will start with the
electronic structure and working principle of TFT. It also presents the electrical characteristics
of TFTs and the important electrical parameters to determine TFT performances. Particular
attention is drawn to the importance of interfaces, as well as the origin of electrical instability.
Section 2 is devoted to the material used to fabricate solution-processed TFTs with a
particular attention to the printing processed TFTs with the advanced progress in literature. The
available materials are listed for printed electronics with their advantages and drawbacks.
In conclusion, we will summarize the overview of printed electronics presented in this
chapter.

I. Organic Thin Film Transistor – Basis Concept

A. OTFT Structure and Working Principle

1. Working Principle
Organic Thin Film Transistor (OTFT) is very similar to the classical Thin Film Transistor
(TFT). The major difference comes from the use of organic materials instead of inorganic
material such as silicon. Thin film transistors (TFTs) are a well-known and a fundamental
building block of modern integrated circuits. The basic architecture is composed of a gate,
source and drain electrodes, a gate dielectric layer and a semiconducting layer. Several layers
can be added to the main structure to optimize electronic properties of the device and/or for
specific requirements of the technological process. This electronic device is a field-effect
transistor (FET) comparable to a metal oxide field-effect transistor (MOSFET). Thus, TFTs
and MOSFETs follow similar standards of operation with some differences in semiconductor

50
behaviour under electrical polarization. In these devices, an electric field is applied to regulate
the electrical conduction of a channel located at the interface between the dielectric and the
semiconductor. The gate electrode is isolated from the semiconductor by an insulating layer.
The gate contact controls the mobile charge in the channel by capacitive coupling, called
field effect.
The transistor operates under the influence of two voltages. One is applied between the gate
and the source (VGS) and the other is applied between the drain and the source (VDS). A
field effect transistor (FET) operates as a conducting semiconductor channel with two ohmic
contacts (i.e., the source and the drain) where the number of charge carriers in the channel is
controlled by a third contact (i.e., the gate). The schematic illustration of the main device
structure of a TFT and structural difference of MOSFET and TFT is depicted in Figure 1.

Figure 1. Structural difference between (a) MOSFET, and (b) TFT.

When a bias voltage is applied between the gate and the source, a charge carrier transport
across the dielectric layer is prevented due to the infinite resistance of the gate dielectric layer.
The applied voltage induces charges at the interface between the semiconductor and the gate
dielectric. In other words, gate-source voltage modulates the charge carrier density in the
semiconductor when the drain-source voltage induces charges movement through the
semiconductor from the source to the drain. Overlap capacitances are also formed according to
the applied voltage in the same region. These capacitances were coming from overlap areas
between the gate/source electrodes and gate/drain electrodes, called overlap capacitances of
CGS and CGD.
Considering the case of n-type MOSFET, four regimes occur at the interface between
dielectric and semiconductor based on the positive/negative voltage biases. These regimes are
called accumulation, depletion, inversion and strong inversion. In n-type MOSFET and without
polarization voltages, the channel is a p-type material. When a negative voltage is applied
between the gate and the source, the bands bend upward and causes an accumulation of holes
51
near the dielectric-semiconductor interface. It is called the accumulation regime. When a low
positive voltage is applied, holes are repelled from the insulator/semiconductor interface so a
depletion layer is formed, this regime is called depletion regime. A third regime is called
inversion regime. The inversion regime occurs when an applied positive voltage between gate
and source becomes more significantly large, and bands bend even more downward and the
fundamental level eventually crosses the Fermi level. In the inversion regime, the density of
the holes is less than the density of the electrons because an accumulation of electrons occurs
at the insulator/semiconductor interface. Finally, when the voltage between the gate and the
source becomes higher than the threshold voltage VTH, electrons density becomes higher than
the holes density in the initial state of the p-type material. This regime is called strong inversion.

Figure 2. Band diagram of an ideal MIS structure for n-type organic semiconductor. (a) Depletion,
(b) flat band, and (c) accumulation regimes.

Here, the difference between the organic TFT and the inorganic MOSFET will be discussed.
The organic transistor operates in an accumulation regime. This is the major difference from
the conventional inorganic transistor. The conductive channel is formed by an accumulation of
majority carriers in the layer and not by an inversion of minority carriers. When no polarization
is applied between the source and the drain, the transistor can be considered as an MIS
capacitance. If a voltage is applied between the gate and the source the
gate/insulator/semiconductor stack becomes polarized. Figure 2 shows the different regimes
for an ideal metal/insulator/OSC (MIS) structure as a function of the gate voltage.
We consider here an organic semiconductor leading to an n-channel transistor. When a
negative voltage is applied to the gate, the transistor is in depletion regime (Figure 2(a)) and
the insulator/semiconductor interface will become depopulated with electrons. In the flat band
regime, the gate voltage cancels the curvature of the semiconductor bands. Conversely, a
positive voltage generates the accumulation of electrons at the insulator-semiconductor

52
interface. The transistor is then in an accumulation regime (Figure 2(c)). In other words, the
VGS voltage modulates the Fermi level of the organic semiconductor.
Organic semiconductors (OSC) have a low density of free carriers at room temperature due
to their high gap value. Consequently, to observe the accumulation of charges at the
insulator/semiconductor interface, it is necessary that the charge carriers can be injected from
the source towards the organic semiconductor. The origin of the charge induced by the gate
voltage can then be explained from the simplified diagram of the energy levels in Figure 3 85.
Figure 3(a)) shows the positions of the highest occupied molecular orbital/lowest occupied
molecular orbital (HOMO)/ (LUMO) levels of the organic semiconductor with respect to the
work function of the drain/source electrodes. The principle of forming an n-type channel is as
follows: When a positive potential is applied to the gate, the fermi level of the semiconductor
will shift towards the LUMO level under the effect of the electric field (Figure 3(b)). If the
gate electric field is large enough, the interaction of the LUMO with the metal work function
allows the injection of electrons from the source to the OSC. The charge injected per unit area
is simply given by Qs ≃ - Ci.VGS, where Ci is the capacitance of the insulator layer. Then, there
are mobile electrons at the OSC/insulator interface which, when submitted to VDS voltage, lead
to a current flow between the source and the drain (Figure 3(c)). The charges accumulated at
the interface form a conductive channel between the source and the drain whose conductivity
is proportional to the VGS field.

Figure 3. (a) Idealized energy level diagram of an organic TFT at VGS = 0 and VDS= 0, (b) charge
injection and accumulation, (c) charge conduction (transport). Adopted from ref. 85.

53
 This theory is known as a band-like transport model but, in the case of organic
semiconductors, several charge transport mechanisms can occur. According to the degree of
order in the crystal structure of the semiconductor, these theories can be divided into several
typical categories. These charge transport mechanisms in organic semiconductors are presented
and illustrated in Figure 4 86.
Figure 4(a) shows a summary of charge transport theories. The theories are classified
according to the crystallinity or the structural disorder of the semiconductors.

Figure 4. (a) Summary of charge transport theories in organic semiconductors, and schematic
representation of transport mechanisms for (b) Band-like transport, (c) VRH, and (d) MTR. Adapted
from ref. 86.

This work is not dealing with charge transport but with the technological process
development of OTFT. Nevertheless, we briefly present the most commonly accepted charge
transport theory in organic semiconductors.

54
 - Band-like transport

A classical mechanism, which is mainly expecting for single crystalline materials or some
conjugated polymers with extremely low torsions of a chain. In organic semiconductors, the
mean free paths of carriers are often comparable or less than the intermolecular spacing.
(Figure 4(b)).

- Variable range hopping (VRH) model

In amorphous or disordered semiconductors, as organic semiconductors, charge transport

mainly occurs by hopping or tunnelling among localized states. It is the most commonly used
model. The hopping of charge carriers and the hopping distance are mainly affected by the
energy distribution among the trap states. The charge carriers only transfer by hopping
behaviour in nearest neighbour hopping or to the smallest barrier sites (variable range/energy
hopping). The relevant carrier mobility is strongly dependent on the position of Fermi level in
the band due to the existence of a hopping barrier. This feature often accounts for the gate-
voltage or carrier-density dependent mobility in amorphous and polycrystalline organic
transistors (Figure 4(c)).

- Multi-trap & release (MTR) model

For polycrystalline OSCs with a low extent of structural disorder, the mobility edge model
is applicable and it is related to the MTR model (Figure 4(d)). A large quantity of traps exists
in the bandgap because the OSCs are mostly amorphous or polycrystalline. The carriers move
in the delocalized states band as band-like transport. However, the heavily present traps at the
edges induce a degradation. As a result, it reduces the apparent or average carrier mobility due
to the carriers are dynamically trapped into and released from the trap sites. The MTR model
can determine the density of states (DOS). The mobility in an organic transistor could be
explained by the MTR transport mechanism with a power law dependence on the gate voltage
and a thermal activation behaviour.

Generally, structural order in OSC is not a single crystal but a polycrystalline or amorphous
structure. However, it is very difficult to form a perfect purity polycrystalline state OSC. The
periodic possibilities of the network and trigger failures are modified by crystal imperfections

55
(impurities or defects). The VRH and MTR models are frequently considered as the
microscopic mechanisms to describe for OSCs in a polycrystalline state. Consequently, the
VRH and MTR models account for the low mobility of OTFTs and could explain that charge
transfer present degraded properties such as non-uniformity and electrical instability. The
difficulty to control defects in OSC materials can act as limiting factors as well as the degree
of energetic disorder and delocalization.

2. TFT structure and geometry

TFTs have several geometric structures depending on the order of the deposited layers.
Therefore, as shown in Figure 5, four different geometries are usually used on the common
TFT structures. The differences are distinguished by the location of the S/D contacts and the
gate dielectric layer. At first, they can be classified into two configurations, called bottom
contact and top contact. Both configurations are further categorized as bottom-gate and top-
gate structures. In a bottom-contact configuration, the source-drain contacts and gate dielectric
layer are fairly located in the same region of the channel, while in a top-contact configuration,
the source-drain contacts and insulator layer are oppositely located with the channel.

Figure 5. Schematic illustration of four different geometry for common TFTs.

These structural differences can influence the carrier injection property of the source and
drain/channel interface. Usually, the processing method and the materials will dictate the
choice of structure.
For instance, the bottom-gate bottom-contact (BGBC) structure, which is the employed
device in this thesis, has been widely used in laboratory research due to its cost effectiveness
56
and simple fabrication. Because of feature merit of simple process, the bottom contact
structures are preferred for circuit integration of OTFTs. It is because of the process difficulty
of depositing source and drain electrodes onto the OSC layer with precise patterning. In this
geometry, the metal/semiconductor interface is, from a physical point of view, a
metal/accumulation channel interface. The BGBC structure has a drawback. The OSC layer
has contact with two different materials: gate dielectric and S/D metal electrodes. Thus, the
morphology of underlying layer can affect the OSCs. For example, if the morphology of the
underlying gate dielectric layer in contact with the semiconductor or the wetting/dewetting
behaviour is not suitable, the deposition of the upper film is disturbed. As a result, a
functionalization step is required to adjust a sufficient surface tension before semiconductor
deposition. In case of the OTFT with this structure, the use of encapsulation is inevitable
because the OSC is exposed to the atmosphere. The presence of traps may degrade the injection
properties at the metal/semiconductor interface through the well-controlled fabrication
technology (evaporation, spin coating, or printing). Besides, the use of the optional process for
a specific OTFT structure will depend on the best way to achieve a trap-free interface 87.
The top-contact structure typically shows a better electrical performance than those of the
bottom-contact structure, in electrical characteristics of OTFT. The top-contact OTFT has been
proved that mobility of a bottom-contact OTFT can be 1-2 orders of magnitude lower than that
88–90
of a top-contact device . It is on account of lower contact resistance RC that caused by
morphological disorders around the interfacial area of contact-semiconductor surface 90.
Moreover, the top-contact structure can provide an effect of encapsulation thanks to the gate
dielectric layer and gate electrodes over the sensitive layer. However, there are not many
polymer dielectrics for the gate insulator, which are compatible enough. The literature provides
several reasons for the lack of a compliant gate insulating film, including the solvent in the
meaning of the solubility 91 or mechanical strength due to the surface tension 92. The substance
in contact with the OSC must consider ensuring solvent orthogonality and avoiding the
dissolution of OSC by dielectric solvents for stable solution processes. The use of deposition
processes should be carried out at low temperatures (typically < 200 °C) to prevent deformation
and degradation of the semiconductor layers.
For these reasons, the bottom-gate bottom-contact structure was chosen in this thesis, among
the presented four structures, for the easy printing process and to the exclusion of other
influences (e.g., influence of solvent from upper/underlying layer). The TFT structure has been

57
modified to create other TFTs, such as the double-gated, the vertical channel and the cylindrical
OTFTs 93, thus exploiting all the potentials of this device for specific applications 78.

B. Electrical Characterization and Parameters

Extraction

1. Electrical characteristics of TFTs

Electrical characteristics of TFTs can be investigated by two types of measurement. One is
the transfer characterization method and the other is the output characterization method, as
shown in Figure 6.

Figure 6. Electrical characteristics of the n-type TFT, (a) transfer characteristics (VGS - ID at constant
VDS), (b) output characteristic (VDS - ID at constant VGS).

The transfer and output characteristics can be presented as the following expressions:

- Transfer characteristics (Figure 6(a)): the transfer curve is an electrical characteristic

corresponding to the measurement of drain current ID as a function of gate-source
voltage VGS at a constant drain-source voltage VDS. In general, the ID value is expressed
via the linear or logarithmic scale. This measurement is carried out with low and high
VDS thus electrical parameters can be extracted in linear and saturated regimes.

- Output characteristics (Figure 6(b)): the output curve is an electrical characteristic

corresponding to the measurement of drain current ID as a function of drain-source
voltage VDS at constant gate-source voltage VGS. In general, the ID value is expressed
58
 via the linear scale. The operating mode of TFTs and contact resistance can be
determined by this method. Output characteristics can also discriminate the linear and
saturation regions. Moreover, the intersections of both the output and active charge
curves can be used to estimate the circuit performance.

From the transfer characteristic, three regimes can identify (Figure 6(a)):

1) VGS < VTH (cut-off): In the cut-off region, the drain current results from the intrinsic
conductivity of the n-type material without any electron accumulation. The drain
current is called IDOFF and is proportional to the drain-source voltage. Drain-source
voltage is keeping constant to measure transfer characteristics.

2) 0< VGS < VTH (Subthreshold regime): When the gate-source voltage increase with a
positive value, electron are accumulated in the semiconductor/insulator interface
leading to a fast increase of the drain current ID. Depending on the interface quality, the
drain current increases more or less quickly. In OTFT case, drain current is usually not
increasing linearly in this regime.

3) VGS > VTH (on regime): Drain current ID is increasing linearly with the gate source
voltage VGS.

From the output characteristics, two regimes can be identified (Figure 6(b)):

1) VDS << VGS-VTH (ohmic/linear): When VGS is constant, drain current ID increases
linearly with the drain source voltage VDS. The channel is then uniform and the
resistance RDS is constant. In a digital circuit, this is the regime when the transistor is
in the on state (low VDS/VGS = VDD).

2) VDS >> VGS-VTH (saturation): When VGS is constant, drain current ID keeps constant
value (ideal case). The free carrier density is constant even the drain-source voltage
increases. The resistance RDS increases with VDS. In a digital circuit, this is the regime
when the transistor is in the off state (high VDS/VGS = 0). In the non-ideal case as for
many OTFT, ID still increases with VDS.

59
 2. Electrical parameters extraction
To evaluate an electrical performance of fabricated TFT, several key electrical parameters
can be extracted. The main electrical parameters are the field-effect mobility in linear regime
(μFE_lin.) and in saturation regime (μFE_sat.), the threshold-voltage (VTH), the on-set voltage
(VON), the subthreshold slope (SS), the ratio between on and off drain current IDON/IDOFF and
the contact resistance (RC).

a. Field-effect mobility (μFE)

The field-effect mobility is a main feature of merit for TFTs because it represents the free
carrier velocity of charge transfer of a transistor under a given electric field. To present the
field-effect mobility, “cm2V-1s-1” is used as a unit to define the operating frequency when the
transistor is integrated into a circuit. A higher mobility will provide stronger current at a fixed
bias and a shorter switching cycle 94.
However, since the mobility property is easily affected by a plurality of external factors, it
is not easy to extract an accurate value (e.g., impurities intervention and structural defect during
fabrication, quality of the interface, in particular, the OSC/dielectric interface, etc.). For
instance, the mobility in the case of organic semiconductors is typically a very low level
comparing to inorganic semiconductors. However, the established results of the value extracted
from the equations could be underestimated due to the presence of contact resistances. The
contact resistances induce a fall-of potential in the electrode region, and thus a lower effective
source-drain voltage than VDS along the channel. Therefore, the field-effect mobility of the
carriers does not correspond to the real value in the OTFT channel. To summarize, the apparent
mobility depends on the charge transport in the channel but also on the injection at the drain-
source contacts.
In general, it is extracted from the transfer curves and it is measured in the linear and
saturated regimes. To evaluate the field-effect mobility of the TFTs in two different regimes,
two different methods are used for the extraction of μFE_lin and μFE_sat.

At first, in the linear regime (VDS ≤ VGS-VTH), the drain current is given by:

𝑊𝐶𝑖 ….................. Eq. 2.1

𝐼𝐷 = 𝜇 (𝑉 − 𝑉𝑇𝐻 )𝑉𝐷𝑆
𝐿 𝐹𝐸_𝑙𝑖𝑛 𝐺𝑆

60
 Where W and L are the channel width and length, respectively. Ci is the capacitance per unit
area of the insulator, μFE_lin is the field-effect mobility in the linear regime, respectively. VGS
and VDS are the gate-source voltage and drain-source voltage, respectively and VTH is the
threshold voltage. Therefore, the field-effect mobility in the linear regime can be expressed by:

𝐿 ∂𝐼𝐷 𝐿 ….................. Eq. 2.2

𝜇𝐹𝐸_𝑙𝑖𝑛 = = 𝑔
𝑊𝐶𝑖 𝑉𝐷𝑆 ∂𝑉𝐺𝑆 𝑊𝐶𝑖 𝑉𝐷𝑆 𝑚

Where gm is the transconductance. The gm is the maximum value obtained by plotting

derivative function of ID = f (VGS).
To evaluate the field-effect mobility in the saturation regime (VDS ≥ VGS-VTH), the drain
current is given by:

𝑊𝐶𝑖 ….................. Eq. 2.3

𝐼𝐷 = 𝜇 (𝑉 − 𝑉𝑇𝐻 )2
2𝐿 𝐹𝐸_𝑠𝑎𝑡 𝐺𝑆

Therefore, the field-effect mobility in the saturation regime can be expressed by:

2𝐿 𝜕√𝐼𝐷 2 …..................... Eq. 2.4

𝜇𝐹𝐸_𝑠𝑎𝑡 = × ( )
𝑊×𝐶 𝜕𝑉𝐺𝑆

Therefore, to calculate this mobility, √ID is plotted as a function of VGS. From this graph,
we calculate the derivative and then we deduce the mobility μFE_sat in saturation regime.
Experimentally, the field effect mobilities in the linear regime are lower than those obtained in
the saturated regime. This can be explained by the presence of high contact resistance (RC). At
low VDS (linear regime), the potential drop induced by RC is significant compared to VDS. On
the other hand, for high VDS value (saturated regime), the voltage drop becomes negligible.
Linear mobility, being calculated at lower VDS, will therefore be underestimated and lower than
saturated mobility. A second possibility to explain this difference is the mobility dependence
to VDS for disordered materials. Saturated mobility is measured at high VDS and can therefore
benefit from the emission of carriers trapped by the electric field. Finally, there is also an
increase in mobility with VGS. This phenomenon can be explained using the MTR and VRH
models discussed in the previous section.

61
 b. Threshold-voltage (VTH) and On-voltage (VON)
The threshold voltage (VTH) is the minimum gate-source voltage (VGS) needed to create a
conducting path (i.e. channel) between the source and drain contacts. In a MOSFET structure,
VTH Corresponds to the VGS value, where the channel is converted from weak inversion to
strong inversion. As shown in Figure 7, the I-V characteristics show that a very low currents
occur at a low VGS in the linear region (Figure 7(a)).

Figure 7. Inspection of extracting the threshold voltage in (a) linear, and (b) saturation regime.
Adopted from ref. 94.

The gate voltage dependent mobility reduces the IDON/IDOFF ratio and increases the
subthreshold slope. As a result, VTH extracted from linear transfer characteristic for an OTFT
could be discussed. In literature, the linear regime is more frequently used to extract VTH as
well as the field effect mobility 94. Thus, we applied the same extraction method to be able to
compare our own results to other works.
The turn-on voltage (VON) is the point where the mobile carriers begin to be accumulated in
the channel. It can be extracted from the slope of the transfer curve in logarithmic scale, as
shown in Figure 8.

62
 Figure 8. Extraction of electrical parameters in the linear region from the transfer curve on a log and
linear scales, (b) output characteristics of n-type transistors with extracted transition voltage (VTR) and
saturation drain current (IDSat.) with specified VGS, to evaluate contact resistance RC. Adopted from
ref. 95.

The VON exhibited a much smaller variance than the linearly fitted VTH 96, not only in the
linear regime but also in the saturation regime. Generally, the VTH and VON do not have the
same values, as shown in Figure 8(a) 95.
In ideal model of MOSFETs, VON and VTH have the same value. In OTFT, these values are
different due to the electron traps existing in the OSC or at the dielectric/OSC interface. The
traps are playing a role of disturbing channel formation of OTFTs. Another reason that explains
the difference between VTH and VON is that OSCs laver inherent free charges.
. Therefore, the VTH is extracted by the intersection between the horizontal axis and the linear
regression of the curve in the linear regime of the transfer curve, as shown in the black straight
line in Figure 8(a). The VTH in an ideal accumulation type of organic TFTs is zero. It is
because, in the absence of localized states, originating from donors, acceptors or traps, all
induced charge is necessarily mobile. However, in the real case, VTH, in an accumulation type
of organic TFTs, is not zero.

c. On and OFF drain current ratio: IDON/IDOFF

Any switch including the electronic devices working as switches has two states, the off sate
and the on state. On current (IDON) and Off-current (IDOFF) are simply defined as the ratio of the
maximum and minimum currents (IDON/IDOFF) recorded within a given VDS in the logarithmic
plot of the transfer curve.

63
 Figure 9. Impact of gate leakage on IDOFF, (a) typical transfer characteristics obtained with/without
gate leakage on linear and logarithmic scales, (b) experimental example to compare an impact of gate
leakage on IDOFF. Both figures are adopted from ref. 97.

As mentioned above, higher mobility will provide stronger current at a fixed bias, the shorter
switching cycle (e.g., frequency response). Likewise, IDON depends on field effect mobility,
channel dimension (W/L) and insulator properties. IDON/IDOFF ratio is often present a significant
97
leakage current. Singh and Mazhari et al. propose a specific measurement to evaluate
transistors transfer characteristics and parameters. The impact of the gate leakage is clearly
noticeable for small values of VDS in their results, as shown in Figure 9 (a). In addition, an
adopted experimental result (Figure 9 (b)) shows the comparison of transfer characteristics
obtained at different VDS for a device in the presence of gate leakage current. If the gate leakage
current is large, the IDOFF current may increases during the current in off state. Increases of
IDOFF are occasionally observed at reverse gate voltages and can be attributed to minority carrier
activation by electric fields.

d. Subthreshold Slope (SS)

The subthreshold slope (SS) is a feature of a MOSFET`s current voltage characteristics and
is one of the most critical performance metrics for MOSFETs and logic applications. In other
words, the slope below the threshold indicates, how the transistor transition quickly changes
from off state to on state. To present the SS, “V/decade” is used as a unit to define and
corresponds to the change in gate potential required to increase drain current to a decade. It can
be determined by taking the reciprocal of the slope of the transfer characteristics, as a red
straight line shown in Figure 8 (a). It is highly desirable to have value as small as possible.

64
Assuming that trap density of states (Ntrap) in the dielectric/semiconductor interface of TFTs
can be expressed as following Equation 2.7 98:

𝑘𝑇𝑙𝑛(10) 𝑒2 ….................. Eq. 2.5

𝑆𝑆 = (1 + 𝑁𝑡𝑟𝑎𝑝 )
𝑒 𝐶𝑖

Where k is the Boltzmann constant, T is temperature, e is the elementary charge, and (Ci =
ε0εr/e) is the intrinsic capacitance, respectively. The lower limit of the subthreshold current is
determined by the leakage current that flows from source to drain, when the transistor is in the
off state 99. Furthermore, the slope below the threshold is simply a measurement of the number
of defects. The high trap density can induce that the speed of channel formation becomes
slower, and then, the SS is increased. Therefore, a high capacitance per unit area and a small
number of defects are desired to obtain transistors that operate at low voltages

e. Contact resistance (RC)

Contact resistance (RC) is a good way to evaluate the injection of charges into organic
semiconductors. In OTFTs, the charge carriers are injected from contacts into OSCs through a
Schottky junction where an injection barrier increases the contact resistance, since higher
voltage (or potential drop) is needed 94. The resulting in RC can have a significant influence
on the electrical characteristics of the device in the on-state (i.e., above the threshold
voltage) 85.
The effect of RC depends on the architecture of the device. In the case of bottom-contact
structure, the carriers must across the metal/semiconductor interface, where high density of
traps exists. In the case of top-contact structure, the carriers must across the semiconducting
layer, where the bulk conductivity is very low. Both contributions are factors that increase RC.
In previous works, several works have reported that the bottom-contact structures have, much
higher RC than top-contact structures (as a top-contact). It is because of the large number of
traps resulting in small grains (or void) coming from the contact, where disturbing a molecular
ordering. Another reason is the different charge injection barrier according to the differences
in architecture. In addition to these reasons, there are various factors that affect the contact
resistance of a TFT, such as the interfacial dipole, dependence of mobility on the gate voltage,
etc.

65
 The total resistance of the transistor (RON) is composed of the sum of the serially connected
contact resistance (RC) and channel resistance (RCH). Therefore, the RON can be expressed as
following Equation 2.8:

R on = R S + R D + R ch = R C + R ch …..................... Eq. 2.6

Therefore, the RC is given by the following Equation 2.9 of the drain-source resistance
(RDS):

𝑉𝐷𝑆 𝐿 1 …..................... Eq. 2.7

𝑅𝐷𝑆 = = 2𝑅𝐶 + ( )
𝐼𝐷 𝑊𝜇𝐶𝑖 𝑉𝐺 − 𝑉𝑇𝐻

The RC assumed similar value for both source and drain contacts 100.

C. Electrical Stability of OTFT

1. Why do we need to consider electrical stability of TFT

for circuit applications?
In the field of TFT research, improving the electrical stability of the devices led to
successfully implement practical applications, such as AMLCD or AMOLED displays. The
TFT instability is, most part of the time, related to field effect mobility and threshold voltage
variation. A highly stable device would consist of a transistor does not exhibit significant
variations in VTH (ΔVTH) upon prolonged operation and no significant field effect mobility
degradation 101.
Electrical instability has not only impact on the device (i.e., TFTs), but it can also induce
abnormal circuit performances. Besides, it is also related to reliability of electronic devices.
Mainly, the VTH shift has a critical impact on circuit operation and the circuit cannot work in
the case of a significant VTH shift. The negative VTH shift for inorganic-based TFTs has been
extensively studied. Notably, the electrical instability issue of oxide-based TFTs upon
application of a gate bias stress is a major drawback. This major drawback can make a
significant problem when it is used to control active matrix displays. For instance, organic light
emitting diodes (OLEDs) need a very stable current. This current is driven by applying gate
voltage on TFT. The current flowing through the TFT channel has then to be very stable under
66
constant polarization. In other words, this highlights that electrical stability is an important
matter.
On the other hand, organic-based TFTs have a short history and, in organic research fields,
the electrical stability is behind the performance improvement of the devices, mainly for the
mobility. However, today, the field requires researchers to turn their attention to other issues
that are essential to this commercialization: the stability of the transistor when operating in the
air or when subjected to DC polarization.
There are several factors considered as a reason for electrical instability, such as defect
generation (quality of semiconducting layer), trapping charges, interface mechanism in device
architectures (molecular organization), tunnelling effect within the insulating layer, etc. The
unstable current caused by electrical instability is proportional to the current transferred to the
transistor.
The goal of this thesis is related to the circuit implementation. Therefore, understanding
electrical stability has valuable importance to implement reliable circuits.

2. Origin of electrical instability in OTFT

As mentioned above, there are many factors that can affect the electrical stability of OTFT.
The bias stress (BS) effects are closely related to the electronic structure. In this section, the
electrical instability that can occur in the structural problems of TFT is discussed.
As shown in Figure 10, based on the BGBC structure of TFTs, electrical instability could
come from four locations. The origin of electrical stability on the TFT architecture could come
from:

i. Trapping of charges and dynamic creation of traps in the organic semiconductor.

ii. Trapping of charges at the OSC/insulator and OSC/source and drain electrode
interfaces.
iii. Injection or trapping of charges in the insulator.
iv. Formation of bipolarons in OSC.
v. Presence of mobile ions in OSC/insulator.

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 Figure 10. Four different origin of electrical instability, (a) semiconductor, (b) interface between gate
dielectric and semiconductor, and (c) interface between source/drain electrodes and semiconductor,
and (d) gate dielectric.

a. Electrical instability from the semiconductor

Electrical instability of organic semiconductors is given by the following reasons:

- Reversible decomposition of semiconductor structures due to strong electric field

102
(dynamic generation of electron traps) : The strong electric field of the transistor
can effectively result in the formation of new shallow electronic states. The new state
acts as a trap, shifting the critical voltage and at the same time reducing the effective
transfer. It induces the degradation of OSC structures (e.g., bond brakes).

- Low mobility due to the formation of a pair of polarons (bipolarons): Street et al. 103–
105
proposed that the formation of bipolarons in semiconductor is one source of bias-
stress effect. A slow, carrier-induced meta-stable structural change can occur in the
semiconductor and leads to a corresponding increase in trap density 106. The bias stress
removes mobile holes from the channel at a rate proportional to the square of
concentration. Therefore, the formation of these bipolarons due to the bias stress follows
the same mechanism to remove the mobile charge storage in the channel and reduces
the current. Consequently, the bipolarons induce current degradation (i.e. electrical
stability). This phenomenon means that the stabilization of the bipolar material is
affected by structural obstacles and emphasizes the importance of semiconductor
deposition.

68
 - Charge trapping in pre-existing localized levels 107: The trapped charge density (i.e.,
trap density of state) forms a charge distribution that blocks the electric field induced by
VGS. At constant polarization, the decrease of drain current is caused by a decrease of
the field-effect. In the case of gate bias stress, once the gate field exceeds the electrostatic
shading, the transistor characteristics will be similar to those obtained results before the
stress. This mechanism leads to threshold voltage shift without reducing mobility.

b. Electrical instability from the interface between gate

dielectric and semiconductor
The interface between gate dielectric and semiconductor is the most critical origin of
electrical instability. This interface is related to the morphology/structural ordering of the
organic semiconducting layer and the charge transport. The grain size of a semiconducting
layer on a gate dielectric layer is highly dependent on the surface of dielectric layer. Therefore,
an unstable surface of dielectric can occur the molecular disordering and increase the surface-
trap density. As in the semiconductor case, a VGS field is blocked by the distribution of the
generated trapped charges, resulting in reduced field effects. The extended VGS field is leading
to an alignment of the dipoles and thus to an increase of the dielectric capacitance per unit
area (Ci). In addition to morphology/structural ordering, surface energy, surface polarity and
dielectric constant have been widely discussed as factors that can affect device instability.
Several solutions have been widely studied in response to its importance. The alignment and
grew of crystalline domains via an annealing procedure and the use of double gate dielectric
layers are typical proposed solutions 108,109.

c. Electrical instability from the interface between source and

drain electrodes and semiconductor
Only a few results deal with the instability from the interface between source/drain
electrodes and semiconducting layer. These studies have been carried out for transistors in
bottom gate top-contact configuration. They have shown an increase of contact resistance
during electrical stress. Thus, the decrease of the drain current at constant bias comes, on the
one hand, from the variation of the channel resistance and, on the other hand, from the change
of the contact resistance.

69
 d. Electrical instability from gate dielectric
Two phenomena due to the insulator can be at the origin of the electrical instabilities in the
transistor. The first is the injection and trapping of charges in the volume of the insulator. In
the same way as for the semiconductor, the gate electric field VGS is screened by the distribution
of trapped charges leading to a reduction in the electric field effect.
The second phenomenon can occur when the insulator has dipoles. The application of a
prolonged gate electric field VGS leads to an alignment of the dipoles and therefore to an
increase in the capacitance of the dielectric. The typical example is that of parylene-based
108
transistors . At constant polarization, there is an increase in the drain current caused by an
increase of the electric field effect. For gate bias stress, the shift of the threshold voltage is
inverted (opposite sign) with VGS.

II. Materials for Printed OTFT

A. Context of this study

The main goal of this section is to present printed materials reported in the literature. In this
thesis, we made the choice to focus on fully additive process with printed gate, source and drain
electrodes and printed insulating layer. Because we have adopted a Bottom-Gate Bottom
Contact structure, the semiconducting layer is deposited at the last step of the process. The
development of a printed semiconducting layer is, to our own opinion, a very complicated task.
In order to prove that inkjet printing technology could be used to achieve a complete electronic
circuit, we focused our effort on developing printed OTFT structure with evaporated
Fullerene (C60). This choice has been made from our previous experience on this material.
Indeed, using photolithography to fabricate OTFT with C60 as semiconducting layer has
demonstrated the possibility to obtain organic transistor with interesting electrical
performances such as a field effect mobility about 1.5 cm²/V.s, a threshold voltage VTH of 6.3
V, a subthreshold slope SS of 1.4 V/dec 95.
As we are looking for fully additive process to fabricate organic electronic circuits, the use
of fullerene at the last process step fulfilled our requirements. Thus, in this section, works
reported in the literature will focus on conductive printed materials and on insulating printed
materials. First, nanoparticles (NP) metal ink will be presented following a brief list of
70
conductive polymers. In the second part, some examples of printed polymers used as insulating
layer in OTFT will be described.

B. Printed Conductive Layer

Several types of conductive materials include colloidal materials of nanoparticles (NPs),
conductive polymers, and organometallic compounds in solution. Whatever the conductive
material or solvent used, these inks will often contain other constituents such as dispersants,
110
adhesion promoters, surfactants, thickeners, stabilizing agents and other additives . One of
the main challenges of the conductive liquid phase, as ink, is a material with high conductivity
with suitable processability of the ink, and thus the main function of the processing methods.
In the case of printing process, the desired requirements should fulfil the improvement of
printability. Both ink and print-head are equally responsible. The intrinsic properties of the
soluble ink should be compatible with the inkjet printing hardware (e.g., equipment), such as
viscosity, potential hydrogen (PH), surface tension, and wettability. The processability, such
as process adhesion with substrate or underlying layer, thickness, accurate pattern, etc., can be
determined by ink properties.
A brief description of the most common types of conductive inks, including Silver (Ag),
Copper (Cu) and gold (Au) are provided in following sub-sections.

1. Conductive metal NP inks

NP inks have attracted attention due to their electrical, optical, and thermal properties. These
metal NPs are NPs diluted either in water or an organic solvent. The solvent chosen must
readily be evaporated once deposited but not so quickly that it dries out at the nozzle when idle
for short periods and forms a viscous film that prevents drop ejection 110. Most conductive inks
are based on metal NPs. For the reason, the resistivity of these materials is 2-3 times higher
than bulk material, as opposed to conductive polymers whose resistivity is higher. The various
metal elements can be used as NP ink, such as silver (Ag), copper (Cu), gold (Au),
aluminium (Al), platinum (Pt), carbon (C), etc.

71
 a. Ag-based NP ink
Ag is the most commonly used metal as conductive ink for printed electronics. Among these
conductive metal NP inks, Ag-based inks are highly conductive and offer excellent flexibility.
In case of the bulk-Ag, it has a conductivity of 6.28 × 107 S/m and a resistivity of 1.59 × 10-6
111
Ω·cm at room temperature (RT). Chou et al. reported that spin-coated Ag NPs on a glass
substrate as a thin film would exhibit low resistivity of 2.4 × 10−5 Ω∙cm after sintering at the
temperature of 250 °C for 30 min. Higher sintering temperatures above 400 °C cause the
growth of pores in the film, and it led to discontinuities in the conducting lines. As a result, the
conductivity of the Ag NP thin film was decreased, and smaller Ag NPs had a similar reaction
at lower temperatures. Generally, the reported sintering temperature is typically required at
100-300 °C to burn-off the organic additives present in NPs inks and to realize a more densely
packed silver layer and form a conductive film of low resistivity. Even a better performance of
Ag NP inks can be expected, but changes of pore`s morphology by increasing the sintering
temperature should be considered (Figure 11).

Figure 11. Scanning electron microscopy (SEM) images of Ag nanoparticles (NPs) at different
temperatures and of changes in pore`s morphology by increasing the sintering temperature; (a) 100
°C, (b) 200 °C, (c) 250 °C, (d) 300 °C, (e) 350 °C, (b) 400 °C. Adapter with from 111.

72
 Li et al. 112 synthesized stable Ag NPs with particle size is less than 10 nm. The Ag NP inks
showed high conductivity at low sintering temperature of 140 °C and it can be used to provide
a promising application as printed source/drain in organic thin film transistors (OTFTs).
113
Kim et al. show directly printed different sizes of Ag NPs on a plastic substrate. In
Figure 12(a), the resistivity variation of the Ag films, composed of two different sized particles
as a function of temperature, has been shown. In their result, the resistivity variation of Ag
films showed a gradual decreasing at the temperature range of 100-150 ºC. Besides, an inter-
particle necks is observed during sintering temperature above 150 ºC. This indicates that
smaller particles make the film densified at lower temperatures. These results have been
improved conductivity, as shown in Figure 12(b).

Figure 12. (a) decreasing the resistivity, and (b) improved conductivity of the thin film composed of
Ag NPs (with different size of 21 and 47 nm) by increasing the sintering temperature. Adapter with
from 113.

Dearden et al. 114 reported the formulation of silver-based inks with good conductivity values
(2-3 times higher theoretical resistivity of bulk silver) at the relatively low temperature of
150 ºC. As we investigate in literature, therefore, it is essential to identify the most favourable
between the sintering time, sintering temperature and the resultant conductivity. Another
suggested challenge to improve the conductivity of Ag NPs thin film is to explore optimum
conditions for the quality of the fine patterns.
115
Zhang et al. reported the development of an effective and facile approach to print a
conductive pattern using coffee-ring effect. They were successfully fabricated on hydrophilic
116
glass surface with an average line width of 5-10 µm. On the other hand, Kim et al. have
investigated the direct metal NPs printing for the production of conductive patterns avoiding
the coffee ring effect. The conductance of the conductive line is strongly influenced by the
uniformity of printed patterns. The coffee ring effect is one of the most influential factors for
73
electrical performance. The addition of a high boiling point solvent with lower surface tension
can improve the film quality of the ink-jet printed patterns as well as the conductance. Kim
calculated specific resistivity at 300 °C considering the cross-sectional area is about 3.5 × 10-6
Ω·cm and Ag NPs showed great potential as electrodes for organic transistor devices. The
electrical performance of Ag NP-based ink is compatible with a low-cost effective material.
However, Ag NPs based inks have a drawback relating to the particle size (diameter in the
range of 40-60 nm) 117, which is an important factor in terms of uniformity and productivity.

b. Cu-based NP ink
Copper (Cu) NP is also a widely used material as well as Ag NP–based inks. In case of the
bulk-Cu, it has a conductivity of 5.96 × 107 S/m and a resistivity of 1.68 × 10-6 Ω·cm at room
temperature (RT). Cu has emerged as an alternative material to Ag due to the electromigration
resistance of Ag needs to be further improved in order to be comparable to Cu 118. Generally,
Cu has benefit from cost and abundance, when it is compared with Ag NPs or Au NPs.
Moreover, solution-processing methods are suitable for the preparation of Cu NP thin-film.
However, the drawback is that Cu is easily oxidized, the oxidized copper has an insulating
feature resulting in less conductivity as it oxidizes. Hence, Protective agents that can delay the
oxidation process are very important in the formulation of these inks. However, it can cause
the increasing cost and complexity of the processing step. As an alternative to long term
oxidation of copper, the deposited copper pattern is protected by overcoat. Cu can be printed
and exhibited metal-like appearance, and it has conductivity after sintering as the other
conductive metal NPs thin-films. High conductivity value close to that of the bulk material
requires a sintering temperature of about 350 °C. An ideal sintering temperature for Cu NPs
thin film has been reported at 250 °C. Li et al. 119 reported the calculated conductivity of inkjet
printed Cu line and it was 1.8 × 106 S/m. the obtained conductivity is equivalent to about 1/30
of that of bulk Cu metal. Besides, the process temperatures lower than 160 °C can be used for
plastic substrates to achieve the various applications.

c. Au-based NP ink
Au NP based thin film formation is also roughly comparable with Ag NP based thin films
with high conductivity of 4.26 × 107 S/m at room temperature. When the conductivity of Au NP
based thin film compared with the Ag and the Cu based thin films, Au is only slightly behind

74
aforementioned materials. Moreover, Au is inherently the most non-reactive metals being
unaltered by factors like heat and humidity. This material never makes a corrosion,
degradation, and oxidation due to the general resistivity to oxygen. The advantages of the
solution process Au NP are typically acceptable with the lower sintering temperature and
simpler than the film-formation of bulk Au thin film. From another point of view, decreasing
the sintering temperature of Au NP based thin film can be achieved by controlling the size of
the Au NPs. A high conductive Au film with a low sintering temperature of 150 °C by
controlling the size, and length of the organic-encapsulated Au NPs with a sheet resistance is
less than 0.03 Ω/sq. The obtained sheet resistance is indicating a conductivity of approximately
70 % of bulk gold. In the case of inkjet printed Au line, Naghdi et al. 120 reported that the molten
Au NPs were condenced and formed a continuous film with a specific electrical resistivity of
1.4 × 10−5 Ω∙cm, after sintering process. Moreover, Au NPs based thin film has work function
of 5.1 eV, and serves as the single most reliable metal in the field. However, despite these
advantages, the biggest drawback of Au NPs thin film is the high cost for industry. Au is a
highly expensive material, and it is prone to market fluctuations due to the rarity of Au in the
earth`s crust.

2. Conductive Polymer
Conductive polymers such as PEDOT:PSS, poly-pyrrole and doped polyaniline have also
been used with solution process techniques. The demand of conductive polymers comes from
a critical need for the future development of a low-cost, stable and environment friendly
material. Additionally, conductive polymer is seen as a solution for the drawbacks of
conductive metal NP materials. Because the conventional conductive metal NP materials need
a high sintering temperature to increase the conductivity and cost effective in case of several
materials.
PEDOT:PSS is one of the most widely used conductive polymer as electrode materials for
capacitance, and in printed circuit boards and microactuators. PEDOT:PSS provides many
advantages due to its ease of processability, commercial availability. Moreover, PEDOT:PSS
attractive attention because of its physical properties, such as good mechanical strength, superb
thermal stability, high optical transparency in visible light and excellent atmospheric
stability 121.

75
 Another approach to improve PEDOT:PSS is synthesizing with inorganic material such as
carbon nanotubes (CNTs). However, a major drawback is origin of PEDOT:PSS has a typically
low conductivity below 103 S/m. Therefore, two different approaches to improve the electrical
conductivity of PEDOT:PSS has been presented. First approach to enhance electrical
122–124
conductivity of PEDOT:PSS is adding a small amount of solvents . Another approach,
which is a more widely used method, is synthesizing conductive fillers into PEDOT: PSS.
The carbon nanotubes (CNTs) have attracted attention because of solution processable
formulations with improved properties. Transparent and conductive patterns of carboxyl
functionalized single-walled carbon nanotubes (SWCNT -COOHs) and the composites of those
with PEDOT:PSS have been deposited on various substrates. Moreover, depositing those
125
materials by inkjet printing technique are often presented in literature. Denneulin et al.
mixed PEDOT:PSS with poly(ethylene glycol) (PEG) functionalized single wall carbon
nanotubes (SWCNTs) to produce a much more conductive film compared to the original
PEDOT:PSS film 126. They evaluated the performances of several CNTs and sheet resistances
ranged from 10 Ω/sq. to 225 Ω/sq. Nowadays, the most promising CNT based conductive
polymer is PEG-SWCNT as the best candidate for printed electronics with sheet resistances as
low as 225 Ω/sq.

C. Printed Insulating Layer

The electrical properties of dielectric for electronics devices have a profound impact on the
development of organic devices and applications. Moreover, the high electrical performances
127
required high capacitance, low leakage current, excellent breakdown strength , and low
defect densities between dielectric/semiconductor interfaces. Most of the works in organic
semiconductor-based devices have shown the efforts to improve its interface using various
trials of methods and materials, such as exploring suitable dielectric materials as a polymer
dielectric, surface treatment on a deposited dielectric layer before semiconducting layer, etc.
Ideal insulating films (e.g., the well-known thermal SiO2) have been used for both organic and
inorganic TFTs. However, Si-based insulating layers are including such a clear disadvantage.
It is incompatible with flexible and large-area electronics because it generally deposited with
high temperatures. Above all, to reduce the cost of developing TFTs and increase their

76
applicability, much more research has been done in the field of the solution-processed
dielectric.
Polymer dielectric materials have been argued as a versatile alternative of SiO2. These
dielectrics can be deposited by a wide range of solution processing techniques, including spin
coating, spray coating, inkjet printing, and dip-coating. Such a polyvinyl alcohol (PVA),
poly(methyl methacrylate) (PMMA), benzocyclobutene-based (BCB) polymers, poly-4-
vinylphenol (PVP), CYTOP, SU-8 and other fluoropolymers are existed as an attracted
substantial attention because of their excellent film formation, high solvent resistance,
flexibility and stability. Several dielectric materials and corresponding dielectric constant are
shown in Figure 13 128,129.
As classified in Figure 13, typical polymer dielectrics have relatively lower values of
dielectric constant k (< 5) than high-k metal oxide dielectrics. In addition, some dielectric
materials showed a high capacitance result, while forming pinhole-free films at a thickness
below 50 μm 130.

Organic Dielectric Materials Dielectric constant (k) Inorganic

Dielectric constant (k) Organic
S
M
P

PD

PE

PS
PV
PI

25 10

8
Dielectric constant (k)

20
Dielectric constant (k)

15 6
Organic
Inorganic

10 4

5 2

0 0
F
O
O

2
2

fO
2
2 O
3

D
Si
Zr

PV
H
l
A

Inorganic Dielectric Materials

Figure 13. Comparison of dielectric constant for inorganic and organic materials, adapted from
Ref. 128,129.

However, polymers are more extensively used as dielectric materials with those attractions,
as mentioned above. So, enhancing the dielectric constant of polymer dielectrics is closely
related to the development of device performances with good potential applicability. Polymer
dielectrics inherently have suitable features for a low-cost solution process.
77
 To date, PVP is a representative polymeric substance, as widely used as organic dielectrics,
due to its good electrical properties and excellent to smooth surface before semiconductor
deposition in OTFT devices. The outstanding electrical properties of PVP have been
highlighted, such as a dielectric constant of pristine PVP in a range from 4.0 to 5.2 131 and low
leakage current density below 10-8 A/cm2 132
. However, this material also has been suffered
from such drawbacks, especially high cross-linking temperatures of 200 °C. Several
alternatives have been proposed as the solution to reduce the cross-linking temperature,
including UV-light combination, changing the cross-linking agent and get some aid by using
additional catalysts. The transistor has poor performance than the thermally cross-linked PVP.
Moreover, it has more permissive to hysteresis problems, especially the OTFTs operate in the
atmosphere due to the internal hydroxyl groups 133,134.
The emerging substance of SU-8 (MicroChem, Westborough, MA, USA) for polymeric gate
dielectrics in organic field-effect transistors can meet most of the demands of cross-linking
temperature problems. The SU-8 has proper physical features to use for the polymeric dielectric
layer, and it is a cross-linked material with the low temperature at around 100 °C. This
polymeric material is a negative photoresist so that SU-8 polymerization is performed under
UV light. High resistance against a wide range of chemicals and high optical transparency (low
propagation losses at 365 nm) are also the features of this dielectric material. Besides, SU-8 is
an out-of-the-box material, which means that it can be processed as received without additional
modification or mixing steps. The outstanding electrical properties of SU-8 have been
highlighted 135, with low leakage current densities (≤ 10-9 A/cm2), a high breakdown voltage of
136,137
4.5 MV/cm, and a dielectric constant of 3.2 . Including the spin-coating method, SU-8
has significant properties for the inkjet printing process. As described above, the un-crosslinked
photoresist properties are suitable for performing fine patterned films through inkjet printing
processes. Moreover, concerning the printing requirement, SU-8 can be used as an ink and this
material can take advantage of low molecular weight (~ 7000 ± 1000 Da) and small molecular
size to improve jettability behaviour of inkjet printing. Additionally, wetting properties
combined to microfabrication technology allows the fabrication of super-hydrophobic surfaces,
this hydrophobic surface of SU-8 is controllable by using plasma treatment or UV-ozone
irradiation to make a suitable surface energy for the film formation. These attractive physical
properties already widely reported in the literature combined with printing technology, and
those results will allow for the widespread use of SU-8 inks as a polymeric dielectric layer.

78
 III.Technical approaches to optimize TFT
There are several specific methods to optimize TFT via technical approaches, such as self-
assembled monolayer, various types of post-annealing methods, a downscaling technique for
short channel (i.e., laser ablation, self-alignment, etc.).
An idea of using self-assembled molecules as a dielectric layer can present its challenges in
the deposition, as well as in achieving high molecular density. Typical SAM treatments are
used to provide sufficient surface properties using a way of the dipping in solution or vapour
exposure, which have been conducted only on inorganic gate dielectric or bottom electrodes.
Independently of printing speed, selective deposition, and large area processability are also
included in this approach. The SAM treatment has inherent benefits from the use of ultra-thin
covalent bonded dielectrics so that its importance needs to be emphasized. The reported
capacitance has been recorded greater than 1 μF/cm-2 128. This value is two orders higher than
the specific capacitance value corresponding to a 200 nm SiO2 dielectric of 17.3 nF/cm-2 138.
Chung et al. 139 suggested a single-step SAM treatment that is effective for both inkjet-printed
poly(4-vinylphenol) polymer (PVP) dielectric and Ag S/D electrodes simultaneously. By
adding polystyrene (PS) brush layer into the channel, well-ordered crystals of organic
semiconductors can be obtained, and reduce the interfacial trap and contact resistance. As a
result, improved electrical performance and stability of the inkjet-printed OTFTs, including the
field-effect mobility, on/off current ratio, SS, operation voltage, and stable VTH under several
gate voltage sweeps were confirmed.
Besides, Halik et al. 140 demonstrated using their results that large operating voltages are not
an intrinsic feature of transistors. They use a thickness of 2.5 nm. This dielectric provides a
gate capacitance near 1 μF/cm-2. As a result, the TFTs can be operated with low voltages of 2
V with a low gate current densities 10-9 A∙cm-2. The operating voltage and power dissipation
of devices can be dramatically reduced by exploiting the self-assembly of silane-based
molecular dielectrics. The current density through a SAM dielectric has been shown to increase
upon deposition of the organic semiconductor, prompting the search for a monolayer with a
higher packing density, which was achieved by using a phenoxy-terminated molecule to
increase the π- π interactions between molecules and create a pseudo second layer. And then,
they used a monolayer of phenoxy-terminated trichlorosilane on an oxygen plasma treated

79
silicon wafer with a pentacene semiconductor, which is deposited by thermally evaporation
system. All these results are shown in Figure 14.

Figure 14. (a) molecular structure of (18-phenoxyoctadecyl)trichlorosilane (PhO-OTS), (b) Molecular

structure of pentacene, (c) Schematic of a OTFT with SAM dielectric, (d) Transport characteristics (left)
and transfer characteristics (right). Adapted with from Ref. 140.

IV. Conclusion
Chapter 2 is divided into two sections. In the first section, detailed information about OTFT
is described to understand the working principle as well as the characterization methodology
to extract the main electrical parameters of TFTs. Studies on the structure and electrical
parameters, mainly for an organic transistor, are purposed to optimize printed electronics
through better understanding. In particular, a study of electrical stability for reliable and
successful implementation of circuit applications has been highlighted.
The second section mainly provides a review of printable materials focusing on conductive
materials and insulating materials via the over the last few years of literature. Besides, the cases
of enhancement on TFTs through technical approaches, such as SAM treatment, needed to
activate or stabilize the electrical properties have been briefly provided.
Steadily increasing demonstrations of organic electronics reflect the continuous interest of
this technology to implement electronics. Recent advances in inorganic materials for printed

80
electronics have shown excellent electrical performances with high-quality semiconductors.
Unfortunately, printed inorganic electronic still restricted due to the highly required process
temperature and solubility of inorganic materials. Despite the high performance of the printed
inorganic electronics, there remains a problem that loses competitiveness when compared with
the conventional, vacuum processed, inorganic electronics under the same conditions.
As an alternative, printed organic electronics through various derivatives are studied in the
area of developed transistors. Although its electrical performance is not as good as that of
printed inorganic electronics, the excellent solubility, low-temperature processable, and low
141,142
young's modulus of organic materials have made a constant interest in research field .
Moreover, several remarkable results demonstrate the crucial aspect of the printing process by
interesting examples of complete circuit applications as proofs-of-concept. The printing
technology has been highlighted due to its benefits from the suitability for low-cost in an eco-
friendly process. In this regard, given the fact that the transistor is one of the central electronic
circuit building blocks, the manufacturing system toward the future electronic will be addressed
through the printed organic technologies. Moreover, the intrinsic physical/chemical properties
of organic semiconducting material must be extended for the implementation of next-
generation electronics as well as low-cost processes.

81
82
 Chapter 3: Fabrication of Inkjet-Printed n-
Type Organic Field Effect Transistor
Chapter 3 deals with the optimization of evaporated C60-based OTFTs in bottom gate bottom
contact (BGBC) configuration, manufactured using Drop on Demand (DoD) inkjet printing
(IJP) technology. This chapter aims at:

- Describing the fabrication process of an OTFT as well as its materials.

- Highlighting the factors influencing the electrical performances of the inkjet-printed
transistor.
- Developing a high-performance n-type OTFT allowing its integration into a circuit with
optimal electrical characteristics.
- Ensuring a uniform and reproducible OTFT process conditions for reliable and complex
circuit operation.
- Using a fully additive process.

There are several strategies to reach these goals:

-

- Well-chosen materials (electrodes, dielectric, OSCs).

- Optimizing printing parameters to achieve a stable printed layer`s morphologies and
patters accuracy.
- Defining factors related to inkjet printing process that affects the electrical properties of
devices.
- Avoiding using additional and complex chemical treatments to improve the device's
electrical characteristics, such as self-assembled monolayer of gate dielectric or drain
and source electrodes, etc.

The previously mentioned strategies will be described in depth in the following and will
constitute the subsections of this chapter.

83
 I. Material selection

A. Metal electrode: Ag nanoparticle ink

Silver nanoparticles (Ag NP) ink (Silverjet DGP 40LT-15C from ANP, Korea) has been
chosen as the conductive material for the metal electrodes in this study. The conductivity of
Ag NP inks can be optimized varying the sintering temperature 143.

Figure 1. Various suitable electrical properties of Ag ink. (a) High electrical conductivity (obtained
by drop on demand printing), (b) the stability of synthesized Ag nanoclusters in air. The synthesized
silver nanoclusters show high stability in ambient conditions, at least after 24 hours of exposure to air.
Adapted from ref. 144, (c) schematic energy level diagram of commonly used material in hole/electron
transport materials. Ag and C60 showed proper energy-level alignment. Adapted from ref. 145.

Silver is the most commonly used metal for conductive inks in the field of printed
electronics (PEs). Its conductivity can reach 107 S/m, thus gate, source and drain electrodes as
conductors can be printed. However, it is an important task to identify optimum conditions

84
between sintering time, temperature, and the obtained conductivity. Indeed, as shown in
Figure 1(a), conductivity is highly dependent on sintering temperature.
It is highlighted that the sintering temperature of approximately 120 °C, compatible with a
flexible substrate, is enough to reach conductivities allowing the fabrication of conductive
electrodes.
The electrical stability is another reason why Ag is a prime candidate as the metal electrode.
144
Farrag et al. reported results dealing with the air-stability of Ag NP inks at least after 24
hours of exposure to air, as shown in Figure 1(b). From this work, the high stability against
the air of Ag nanocluster-based ink has been demonstrated. Moreover, it is necessary to
compare the LUMO of the C60 (-4.5 eV) with the Fermi energy level (Ef) of the electrode. As
shown in Figure 1(c), the Ag shows a great alignment with C60 OSC in terms of its energy
level (-4.7 eV) 145. The work function of Ag is ≈ 4.3 eV 146.
As mentioned above, the suitable electrical properties of Ag inks (i.e., high conductivity,
high stability to air, and well-matched energy level alignment to OSC) led to a competitive
material in comparison with the other metallic materials. Thus, the Ag NP ink was selected
along in this study as the conductive material of OTFT.

B. Gate dielectric: Epoxy based ink (SU-8)

We selected SU-8 (MicroChem©, Westborough, MA, USA) ink as the organic dielectric
material, it has already been reported as a printable material 147. This epoxy based photoresist
is compatible with many solution process techniques, including spin-coating for
photolithography 148, inkjet printing 147, 149, 150, etc151. Gate dielectric materials must respect the
following requirements to be considered as a suitable dielectric layer for transistors. Several
representative criteria can be listed as follows:

 Strengths against chemical solvent and physical strengths against temperature.

 Purity and low surface energy allow obtaining gate dielectric with low trap density.
 High-dielectric constant with high-breakdown electric-field.

The first criteria avoid the dissolution or swelling effects between the gate dielectric and the
second printed layer (S/D electrodes in our case). Such harmful effects can lead to interfacial
intra-layer mixing. As mentioned in Chapter 2, the interface relating to the gate dielectric can

85
induce poor electrical performances of the transistors such as electrical instability due to the
charge trapping, for instance. The suggested solution for this criterion is the use of a crosslinked
152
underlying layer to avoid undesired impurities diffusion and trapping chemical groups .
Another approach is to use orthogonal solvents between layers of the device.
Sirringhaus et al. 153 suggested this solution via their experimental results, and this approach
has demonstrated the improvement of field-effect mobility. In addition, the gate dielectric
roughness must be as low as possible.
Another criterion is related to the use of high dielectric constant. The high dielectric constant
means high-k dielectric material. For a given thickness of the dielectric, a high-k dielectric is
preferable to a low-k dielectric for a transistor application that allows to exhibit a high drive
current at low drive voltage (i.e., power consumption) 154.
Un-cross-linked SU-8 2000 series negative-photoresist is an oligomer formed of eight
benzene rings and eight epoxy groups with low molecular weight (≈ 7 kDa) diluted in
cyclopentanone as a major solvent, as shown in Figure 2(a). Concerning the printing
requirements, SU-8 based ink has various physical advantages, as shown in Figure 2(b). One
of the advantageous physical properties of SU-8 is low sintering temperature under 115 °C
with low Young`s modulus (3.8-5.4 GPa).
In addition, the SU-8 provides: 1) excellent resistance against a wide range of chemical
products, 2) tunable wettability, 3) low leakage current density, 4) dielectric constant about 3,
and 5) a high breakdown electric field (evaluated value at 3 mV·cm-1) 147.

Figure 2. (a) molecular structure of the monomer that constitutes the SU-8 photoresist, (b) promising
physical and inkjet printing characteristics.

Moreover, the initial state of the SU-8 is un-crosslinked. To initiate the crosslinking reaction,
the printed SU-8 (un-crosslinked) is baked. The post-baking process is used to complete the

86
polymerization of deposited SU-8. By this combination of low-temperature and UV-light, the
cross-linked SU-8 can be used as a gate dielectric layer. A measured leakage current density is
obtained below 10-9 A/mm2, a dielectric strength of 4.5 MV/cm, and a dielectric constant
of ~ 2.75 155.

Figure 3. Comparison of leakage current densities for PVP and SU-8 dielectrics. Adapted from ref. 149.

Figure 3 shows a comparison between SU-8 and poly (4-vinyl phenol) (PVP). The PVP is
a heavily used dielectric material in the field of inkjet printing. The SU-8 showed a better
insulating behaviour than the PVP regarding the leakage current. It is more than one order of
148
magnitude higher than the PVP dielectrics for the same electrical fields . Consequently, it
can be assumed that SU-8 is a good candidate as an inkjet printed gate dielectric. Note that, at
the beginning of this study, only a few works used SU-8 as the gate dielectric layer. To date,
more and more results are reported certainly due to these interesting properties. Consequently,
for the rest of this study, all the experiments were performed using SU-8 as a printed dielectric.
The inkjet printing compatibility of SU-8 is related to its small molecule and low molecular
weight ink. In the case of high molecular weight inks, they can frequently form long filaments
(over 500 kDa for polymer inks). The long filaments lead to the formation of residual droplets,
156
which can clog nozzles . In contrary to high molecular weight inks, low molecular weight
inks can allow stable printing under a wide range of printing conditions.
The surface wetting properties of SU-8 is hydrophobic. Materials with low surface energy
provide high water contact angle and are generally suitable materials to obtain OTFT with high
mobility. Furthermore, a hydrophobic surface can allow to fabricate fine patterns.

87
 Consequently, the physical and chemical properties of SU-8 allow considering this material
as a promising candidate for the inkjet-printed OTFT fabrication due to its versatile properties.

C. N-type organic semiconductor; Fullerene (C60)

The development of high-performance n-type OTFTs is a crucial task as well as p-type OSC.
The task is not only important for the implementation of p-n junction applications (e.g., such
as OLEDs, sensors, PVs, etc.), but it is also mandatory to fabricate complementary organic
metal-oxide-semiconductor (CMOS). However, the electrical performance of solution-
processable n-type OSCs with carrier mobility and stability is lagging behind the performances
of p-type OSCs. It remains a significant challenge. Therefore, improving the electrical
performance of n-type OSCs is essential for further progress of organic electronic devices 157.
Since 1985, fullerene has been heavily studied as a promising n-type organic semiconducting
material. Fullerenes have interconnected carbon atoms in 20 hexagonal and 12 pentagonal rings,
and average bond length is 1.4 Å. The features of fullerene are having attracted attention due
to its high electron affinity (i.e., high electron conduction), high yield, and low price compared
to other organic materials. We already described the features and reported results of C60 in
Chapter 2. Solubilized C60 fullerene derivative, phenyl-C61-butyric acid methyl ester (PCBM),
has emerged as one of the most successful derivatives. Thus, fullerenes are excellent candidates
for soluble OSC materials that can be applied to inkjet printing processes through good
solubility. Moreover, C60 is expected to continue to be available for the development of its
properties. The physical properties of C60 are as follow 158:

 Density (g·cm-3): 1.65

 Refractive index (600 nm): 2.2
 Boiling point: Sublimation occurs at 800 K
 Resistivity (Ω·m-1): 1014 (at room temperature)
 Vapor pressure (Torr): 5 × 10-6 at room temperature, and 8 × 10-4 at 800 K

As we previously mentioned above, the LUMO energy level of C60 has a great energy level
alignment with the selected metal element of Ag. Note that, the differences in energy level is
typically ~1 eV. 159. Therefore, we expect that the C60 can be used as a promising n-type OSC

88
for high-performance inkjet printed OTFTs. Consequently, the evaporated C60 is used for the
fabricated OTFTs.

II. Inkjet printing methodology

A. Hardware for DoD inkjet printed OTFTs

The inkjet printing equipment used in this study is a piezoelectric jetting system produced
by MGI group© named Ceraprinter X-series. It is an all-in-one advanced materials deposition
inkjet tool for printed electronics and smart 3D printing. The Ceraprinter equipment is a very
accurate multi-material deposition system with on-line multi-cure technology. In-situ
characterization facilities are built-in, and high-precision deposition in each pass with curing
of the entire area can be performed. An optical picture of the printing equipment is shown in
Figure 4(a).

Figure 4. Optical picture and scheme of the equipment used for DoD inkjet printed OTFTs. (a) DoD
inkjet printing equipment (Ceraprinter X-series, MGI group© ). Inset showing working principle of
printing, (b) thermal evaporation system. Inset showing optical picture of evaporation system.

The printing equipment configuration used in this study has two printing heads allowing the
deposition of two different materials. Therefore, there is no need to take the substrate out of
the machine during processes. Heads configuration has been chosen to take into consideration
the following criteria:
The first head is 256 nozzles (Q class sapphire from Konica Minolta). This semi-industrial
print-head is dedicated to silver ink printing. The second head is more convenient for research
needs. Indeed, it allows plugging 16 nozzles cartridges from Dimatix©. Thus many materials
89
can be tested because the cost of the cartridge is only 45$ (≈ 40 €). In this study, SU-8 will be
printed by Dimatix© cartridge (cartridge capacity = 1.5 ml). Furthermore, for each print-head,
nozzles are controlled independently by printing parameters, such as firing voltage, frequency,
etc. (see the section inkjet printing technology in Chapter 1). In addition, the user can choose
the number of activated nozzles at the same time.
For most of the experiments in this study, only one nozzle is activated during printing (mono-
nozzle printing). However, if necessary, multiple nozzles can be simultaneously activated
depending on needs. A vacuum is applied under the substrate during printing, and the substrate
can be heated up to a maximum temperature of 60 °C. In addition, the substrate with a large
scale up to 305 mm × 305 mm can be used and the maximum distance between the printing
heads and stage up to 10 mm allows processing a wide range of substrate. The substrate
alignment ≤ ± 5 μm can be reached for high precision devices. Thus, the printing accuracy is
more restricted by the droplet jetting quality than the mechanical capabilities of the equipment.
Thermal evaporation (Figure 4(b)) was utilized to deposit the n-type C60 material, as OSC.
For organic small molecules and oligomers that are insoluble or which do not form uniform
films directly from solution, the vacuum thermal evaporation is a convenient processing
technique. The thermal evaporation system has the advantages of high film uniformity and
good “run-to-run” reproducibility. The thermal evaporation system has already been used for
the organic small molecule-based OLED process. In the future, the evaporated OSC can be
replaced by soluble fullerene derivative, as the PCBM, to realize fully inkjet printed transistors
and circuit.

B. DoD inkjet-printing methodology: The

methodology of the printing process for this
study
As mentioned above Chapter 1, the following four steps (Figure 5) were systematically
carried out as DoD inkjet printing methodology to print a thin-film layer:

90
 Figure 5. Schematic illustration to descript a film formation process of inkjet printing technology.

① Drop ejection from the nozzle

② Positioning, spreading and coalescence of droplet
③ Solvent evaporation
④ Dried film formation

Figure 6. Schematic illustration of drop distances in DoD inkjet printing process optimization to
fabricate accurate patterns. (a) simulation of printed patterns (design), (b) controlling wettability for
printing line via UV-ozone treatment, (c) microscopic view of a pattern formed with isolated
droplets(without overlap) and the measured size of droplets, (d) a printed pattern formation with a
desired overlap and design, (e) an undesired printed pattern formation due to excess of materials in
constant area.

91
 Each step must be carefully studied to fabricate optimized patterns shape. The two first ones
are crucial to optimize the in-plane (X; Y) pattern size and shape as well as the height. The
solvent evaporation mainly governs the morphology of the pattern along the z-axis
(evaporation flow).

 Ink jettability evaluation and optimization (Figure 6(a)): Overdrop is relative to

droplets spacing that coalesces to form a line. Overline is parameter that relative to
line spacing to form a square-shaped pattern.

 Controlling wettability via UV-ozone treatment (Figures 6(b to c)): The

spreading of a drop on a substrate depends on parameters such as the surface tension
of the inks and the surface energy of the substrate. Therefore, it is necessary to
determine, for each ink and substrate, the diameter of a drop to fix the distance (D)
between drops (overlap), allowing the fabrication of continuous patterns. For a non-
wetting surface, it is possible to carry out surface treatments to improve the
uniformity of the patterns. Various surface treatment techniques exist in chemical
or physical methods. In this work, optimization was performed through an
investigation of UV-ozone treatment, which was suitable and straightforward in a
low-cost process.

 Pattern design assisted by printing simulation (Figures 6(d to e)): A pattern is

made of adjacent droplets that coalesce. The drop distance between center to center
of each drop following the printing direction is called “overlap distance.” The
defined overlap can be divided into two types: they are called “dropoverlap” and
“lineoverlap.” When droplets coalesce along X-axis, they form a line. Lines coalesce
along Y-axis and form a film. To obtain suitable printing parameters (e.g., overlaps
along the X- and Y-axis), we design a pattern consisting of different geometries and
call it the “Vector test” pattern, as shown in the bottom of Figure 6(a) and Figures
6(d to e). The vector test is printed at first varying the overlap distance to optimize
pattern shape. It is composed of: I) an isolated droplet, II) line along X-axis, III) a
line along Y-axis and IV) a film (i.e., several coalesced lines). Note that “Vector
test” patterns have to be printed on the same surface as the final device. In

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 conclusion, printing the “vector test” before printing the final desired patterns is the
best way to adjust overlap to avoid printing errors and obtained the desired printing
pattern (see Figure 6(d)). An undesirable pattern formation can be due to the drying
behaviours, insufficient surface energy, not sufficient dropoverlap and lineoverlap (see
Figure 6(e)).

In this work, this protocol has been following to fix our printing parameters for each ink and
surface.

III.Process optimization

A. Printability optimization of functional materials

Figure 7. 3D scheme showing the working principle of DoD inkjet printing for square-shaped
patterns.

Stable jetting behaviour of the ink must be reached for great printability to form stable
printing patterns (Figure 7). Thus, it must be controlled by at least two jetting parameters:
jetting frequency and firing voltage. In addition, when customized ink is designed, the jetting
windows exploration can be performed to determine if the ink is versatile from the printing
point of view. Such a study has been conducted for Ag NP and epoxy based inks that have
motivated our choice for the electrodes and gate dielectric ink. In this work, the jetting
behaviour of each ink will be discussed in detail.

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 B. Jetting parameters; optimization of Ag NP ink
This section will present a result dealing with the droplet ejection, called “jettability,” of Ag
NP ink varying voltage and jetting frequency. Note that, jetting velocity is typically few meter
per seconds. Commercial Ag NP ink is used in this study and does not require additional
formulation. Consequently, only the firing voltage and jetting frequency can be used to
optimize the jetting behaviour. The firing voltage or the jetting frequency determines the
stable/unstable drop ejection. Indeed, these jetting parameters are related to the amount of ink
ejected from each nozzle and printing velocity.

Figure 8. Silver ink drop ejection at 50 V of firing voltage according to different frequencies (a) 1 kHz,
(b) 3 kHz, (c) 5 kHz.

Figure 9. Silver ink drop ejection at 3 kHz of jetting frequency according to different firing voltages
(a) 50 V, (b) 60 V, (c) 70 V.

Figures 8 and 9 show the impact of the firing voltage and jetting frequency on the drop
ejection. The effect of jetting frequency has been investigated with three different values equal
to 1, 3, and 5 kHz at a fixed firing voltage of 50V (the droplet ejection cannot be observed from
the nozzle under the firing voltage of 50 V). As shown in Figures 8(a) and 8(b), when the
jetting frequency is in the range of 1-3 kHz, a unique and isolated droplet without tails was

94
observed. These jetting behaviours highlight an excellent jettability due to their accurate and
stable jetting. However, when the jetting frequency exceeds 3 kHz, a drop with an undesired
small drop is observed at a jetting frequency of 5 kHz, as marked in the small red boxes. This
phenomenon is called “satellite droplet.” (Figure 8(c)) It is an unstable jetting configuration:
the satellite drop has a significant impact on the inaccuracy of printed patterns. In other words,
this type of instability can cause short circuits due to undesirable patterns, especially, for
source/drain electrodes, in the case of printed transistors. Consequently, the jetting frequency
can be chosen between 1-3 kHz.
Figure 9 shows the impact of firing voltage that has been investigated with three different
values equal to 50, 60, and 70 V, at a fixed jetting frequency of 3 kHz. When the firing voltage
exceeds the threshold of 50V, unstable drop ejection was observed with many satellite drops,
as shown in Figures 9(b) and 9(c).
Jetting frequency and firing voltage were optimized at 50 V and 3 kHz, respectively.

C. Jetting parameters; optimization of SU-8 ink

Figure 10. SU-8 drop ejection at 50 V of firing voltage according to different frequencies (a) 1 kHz,
(b) 3 kHz, (c) 5 kHz.

Figure 11. SU-8 drop ejection at 1 kHz of jetting frequency according to different firing voltages (a)
50 V, (b) 60 V, (c) 70 V.
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 As for Ag ink, the firing voltage and the jetting frequency were used as printing parameters.
Figures 10 and 11 show the impact of the firing voltage and jetting frequency on the drop
ejection of SU-8 ink.
The effect of jetting frequency has been carried out using three different values equal to 1,
3, and 5 kHz at a fixed firing voltage of 50V, as shown in Figure 10. When the jetting frequency
was at 1 kHz, a unique and isolated droplet without tails was observed, as shown in
Figure 10(a). However, satellite droplets were observed at jetting frequencies in the range of
3 to 5 kHz (Figures 10(b) and 10(c)). Therefore, the optimized jetting frequency for SU-8 ink
was fixed at 1 kHz.
Figure 11 shows the impact of firing voltage. It was investigated using three different values
equal to 50, 60, and 70 V, at a fixed jetting frequency of 1 kHz. As a result, when the firing
voltage exceeds the threshold of 50V, unstable drop ejection was observed with many satellite
drops, as shown in Figures 11(b) and 11(c).
The jetting parameters (e.g., jetting frequency and firing voltage) for SU-8 ink show similar
behaviour to the Ag ink. Therefore, the jetting parameters for the SU-8 ink were fixed at 50 V
and 1 kHz, respectively.

D. Optimization process for film formation

1. Inkjet-printed Ag electrode

a. Printing electrode on the glass substrate

In the BGBC OTFT structure, the first layer printed on the glass substrate is the gate
electrode. The prepared substrate is well-cleaning and well-dried through the dry oven step
(note that, the substrate cleaning is described in the summary of process fabrication), the
surface energy of the glass substrate has a well-adapted property (hydrophilic) to form a
continuous film in the X-Y plane, as shown in Figure 12.

Figure 12. Optical microscopic image of an inkjet-printed gate electrode on the glass substrate.

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 When continuous patterns are successfully fabricated, investigation on the thickness and the
morphology of the gate electrode must be performed for a better understanding of the working
behaviour of devices.

i. Thickness and morphology behaviour depending on Drop overlap parameter

In general, in a BGBC structure, the thickness of the gate electrode must be as thin as
possible. It is because a thick electrode can affect the other layer morphologies, which are
deposited on top of the gate electrode (gate dielectric and S/D contact in our case).
As shown in Figure 13, the thickness and morphology of the inkjet-printed Ag electrode can
be controlled by drop overlap in the X- and Y- plane.

Figure 13. Two-dimensional cross-section profile of inkjet-printed Ag electrode on the glass

substrate as a function of drop overlap varies from 50 to 20 μm each 10 μm step.

The morphology is not constant along the profile due to the coffee ring effect. As a result,
the thickness of the edges is higher than the center. Moreover, drop overlap has a significant
impact on the pattern thickness. Note that, the thinnest thickness is observed at 50 μm, but it
leads to unstable pattern formation. Consequently (i.e., non-continuous patterns), the drop
overlap of the gate electrode equals 40 μm (i.e., the average thickness between the highest edge
and lowest center) has been fixed. Finally, the measured thickness of the inkjet-printed gate
electrode is 165 ± 55 nm.

ii. Electrical resistivity characterization

The electrode sintering step optimization is crucial because it allows to obtain conductive
patterns. Conductivity is the reciprocal of the resistivity. That is 1/ρ and is measured in Siemens
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per meter (S/m). The electrical resistance as a function of conductivity is given by the following
Equations 3.1 and 3.2:

𝐿 1 𝐿
𝑅= 𝜌 ,𝜎 = ,𝑅 = Ω …..................... Eq. 3.1
𝑆 𝜌 𝜎𝑆

𝐿
𝜎= …..................... Eq. 3.2
𝑅𝑆

Where σ is the conductivity, R is the resistance, S is the cross-sectional area of the electrode,
and L is the length of the electrode, respectively.
The measurement of the gate electrode was already demonstrated in a previous work by
Wenlin et al. 160, as shown in Figure 14. To measure the resistivity of the gate electrode, a four-
point probe was used as a function of sintering temperature and time.

Figure 14. Inkjet-printed Ag resistivity as a function of sintering temperature and time. Adapted from
ref. 160.

Table 1. Resistivity as a function of drop overlap 160.

Drop overlap (μm) Pattern thickness (μm) Resistivity (×10-5 Ω·cm)

10 9 1.47
20 1.2 1.41
30 0.45 1.5
40 0.2 1.45

For all the tested temperature, optimum resistivity (typically 2.2×10-5 Ω·cm) is obtained after
35 minutes. A sufficient resistivity is obtained when the sintering temperature equals 130°C
for 35 minutes. As expected, the drop overlap has no impact on the resistivity, as highlighted

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in Table 1. It signifies that a temperature equals 130°C is enough to fully destroyed the core-
shell of nanoparticles.

b. Printing electrode on the SU-8 surface

To investigate the influence of S/D electrode morphology, several considerations must be
taken into account including: drop overlap, surface energy, substrate temperature, resistivity
according to the sintering temperature, and gate morphology effect.

i. Impact of surface treatment onto patterns` morphology

To print onto the SU-8, UV ozone (UVO) surface treatment was used as the method to
control its surface wettability. In the case of the SU-8, the surface is hydrophobic. UVO is a
way “to activate” the SU-8 surface. It does not affect the SU-8 surface roughness in contrary
to O2 plasma, for instance. Wei et al. 161 described its working behaviour as shown in Figure 15.

Figure 15. Schematic illustration of UV-ozone treatment. Adapted from ref. 162.

The UV-ozone treatment mechanism is performed thanks to the use of the high-intensity UV
light sources consisting of two wavelengths: 185 nm and 254 nm. The light illuminates the
target surface, and two free radicals of oxygen are created. Residual oxygen radicals can react
to provide ozone molecules (O3). The created ozone performs two functions simultaneously
according to the conditions of the irradiated UV wavelength: surface cleaning and tuning the

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wetting. Indeed, UV-ozone creates hydroxyl groups at the polymeric surface that is well-known
to increase surface hydrophilicity.

ii. UV-ozone treatment impact on inkjet printed Ag on the SU-8 surface

The water contact angle has been measured, as shown in Figure 16(a). When UV-ozone
irradiation time is increasing, the contact angle of SU-8 is significantly reduced. The spin-
coated SU-8 has been used, as a model surface, but we assume that the same results can be
obtained onto printed SU-8. As shown in Figure 16(a), from 0 to 60 seconds of UV-ozone
treatment, the contact angle did not show a significant change. However, the water contact
angle on SU-8 begins to decrease after 60 seconds of UV-ozone treatment. These results
highlight that UV ozone treatment is efficient to control wettability. Note that, full wetting
behaviour is obtained after 200 seconds. As expected, UV-ozone induces an increase in droplet
diameter, as shown in Figure 16(b).

Figure 16. (a) water contact angle on SU-8 depending on UV-ozone treatment time. The inset shows
the state of each droplet over UV-zone time. (b) Droplet diameter variation depending on UV-ozone
treatment time.

iii. Drop-overlap and drying behaviours

Since the DoD inkjet printed OTFTs will be the first building block of the circuit
development, it is necessary to define the factors that can negatively affect its accuracy.
Morphologies of the printed patterns are governed by the droplet impinging behaviour, which
is mainly defined by the volume of inks, size (i.e., radius) of drop on the surface, and drops
overlap. The drop overlap is a factor that can be tuned to fabricate optimized patterns that must

100
be continuous. Different morphologies of printed structures, such as scalloping, stacked coins,
or bulging can be obtained varying the amount of deposited material due to drop overlap
tuning 162 (Figure 17).

Figure 17. (a) schematic illustration with a top view showing a droplet. (b) Schematic illustration for
droplets impinged onto a printed line, showing the formation of different morphologies of printed
structures. The dashed lines indicate the contact lines; (c) photographs showing different printed
morphologies. Adapted from ref. 163.

Figure 17(a) shows the schematic of the droplets deposited on the substrate. Where R is a
radius of the cylindrical shape, and r is a radius of the spherical cap shape, respectively. D is
the distance from the droplet to the end of the line (defined herein as the ‘bead’), and d is drop
spacing. Before the solvent evaporates, the droplet has a regular cap shape with radius r, and
the line has a cylindrical shape with radius R. the droplet behaviour is expressed by the
following Equation 3.3:

𝐷 =𝑑−𝑅 …................. Eq. 3.3

Each morphology can be explained by the relationship of parameters involved in

morphology behaviour, as shown in Figure 17(b) and 17(c).

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 - ‘Stacked coins’ and ‘Bulging’ lines: when drop spacing d is small, the droplet lands on
the bead of the line and expands around the bead rather than creating its contact line
(i.e., d < R, and D < 0).

- ‘Scalloped’: when drop spacing d is large, the impinging of the droplet with the bead is
restrained (i.e., 2R < d < 2r, and D > R).

- ‘Isolated drops’: when drop overlap is excessively large (i.e., d > 2R), lines were not
continuous, forming individual drops.

In particular, “bulging” and “scalloping” are factors that make it difficult to define the
channels of an OTFT accurately. Also, the additional capacitance can be formed by these
factors, which directly impacts the device characteristics. Therefore, the drop overlap has been
determined as a crucial printing parameter to obtain a stable morphology.

iv. Exploring sufficient parameter for surface energy and drop overlaps
Investigations on drop overlaps (e.g., overlapdrop and overlapline) and surface energy was
carried out to implement a stable and accurate printed pattern corresponding to the targeted
design. At first, proper conditions according to the exposure time of UV-ozone treatment(s)
with a fixed drop overlap (μm) on the spin-coated SU-8 were investigated. The spin-coated
SU-8 was used as in previous experiments. The fixed drop overlap of 40 μm has been used
thanks to the vector test pattern. All inkjet-printed Ag electrodes on Su-8 surface have been
performed on the fixed substrate temperature at 50 °C.

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 Figure 18. Inkjet-printed Ag line and vector test pattern on the UV-ozone treated spin-coated SU-8
depending on irradiation time of (a and d) 30s, (b and e) 30s +30s, (c and f) 30s + 30s + 30s, (g and h)
30s + 30s + 30s + 30s.

Table 2. Measured analytical values from experiments on the dependence of UV-ozone treatment
time.

Line width Num. of

UVO3 time drop size Line
(1 drop line, size of bulges in 100
(㎛) continuous
bulges) (㎛) ㎛
30s 46.8 36.6 (96.6) 6 X
30s + 30s 54.1 40.9 (20) 4 O
30s + 30s + 30s 57.0 49.5 (16) 1 O
30s + 30s + 30s + 30s 69.44 60.22 (3) 0 O

Figure 18 and Table 2 show the UV-ozone treatment impact according to the irradiation
time for a line and a film. The results show that 30 seconds of UV-ozone treatment time is not
sufficient to form a continuous line and pattern (Figure 18(a) and 18(d)). Indeed, when a
surface is hydrophobic, the liquid contact line is not well firmly pinned and patterns tend to
split. Besides, many numbers of undesirable behaviours, like bulging, was observed due to the
lack of drop overlap caused by small droplet size and excess of liquid. From 60 seconds of UV-
ozone treatment, continuous lines have been fabricated and the number of bulges starts to
decrease (Figure 18(b) and 18(e)). The dimension began to respect the desired pattern (70 μm).
However, it is necessary to minimize the difference from the design to improve the pattern
accuracy. The occurrence of bulging should be equal to as zero as possible. The result of adding

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30 seconds of UV-ozone treatment lead to a number of bulges close to 1 and size of bulging
become smaller than 60 seconds one (Figure 18(c) and 18(f)). Finally, a stabilized pattern with
the improved pattern accuracy is obtained for UVozone treatment time equals 120 seconds, as
shown in Figures 18(g) and 18(h).

Figure 19. Influence of UV ozone treatment time on the morphology of inkjet-printed electrode. (a)
two-dimension cross-sectional profile, and (b) three-dimensional profile of the inkjet-printed electrode.

Figure 19 shows the influence of UV ozone treatment time on the morphology of the inkjet-
printed Ag electrode. The drop overlap has been fixed to 40 μm, as in the previous study.
Although the droplet diameter and line width can be changed by UV ozone treatment, the
morphology of the inkjet-printed electrode does not change. It signifies that the coffee ring is
not dependent on UV-ozone.

Figure 20. Microscopic images of the Inkjet-printed Ag electrode. Inkjet-printed (a) line pattern, (b)
S/D channel is performed by inkjet printing technology with UV-ozone treated of 120 seconds on the
printed SU-8 and gate electrode.
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 The stabilized UV-ozone treatment time was also applied to the inkjet printing SU-8. Printed
lines and S/D channel show a well-defined pattern without bulging and printing accuracy close
to the desired dimension like the result performed with spin-coated SU-8, as shown in
Figure 20.

2. Inkjet-printed Gate dielectric (SU-8); morphology

control
This section will present the optimization process to achieve stable printability and film
formation of SU-8 2002 ink. The process step of SU-8 fabrication consists of 5 stages:

1) A UV-ozone treatment is performed to improve the wettability of the ink on the surface
of the glass and the Ag gate electrode.
2) The deposition of SU-8 ink.
3) The pre-baking step on hot-plate at 95 °C for 5 minutes.
4) Crosslinking of the printed film through UV exposure (λ = 365 nm).
5) The post-baking step for improving the adhesion and to complete the polymerization on
hot-plate at 95 °C for 5 minutes and 115 °C for 35 minutes.

To fabricate inkjet-printed OTFTs, printing SU-8 can be carried out with one or several
activated nozzles.

a. SU-8 morphology control

As already discussed, an inkjet-printed thin film is often submitted to the coffee stain effect,
which is a well-known phenomenon causing by the transportation of particles in liquid (e.g.,
ink). The coffee ring effect is a phenomenon that is difficult to adjust. In order to obtain a
smooth surface without peaks and valleys, several methods were reported; such as well-
designed ink formulation, drying methods optimization, using a laser or bank formation, and
163–165
photolithography to remove thicker region . In this work, such complex methods were
not used. This study focused on the control of printing parameters such as a number of nozzles
activated during printing and overlapping distance.
The gate dielectric in our BGBC structure directly makes an interface with the OSCs layer.
In other words, the morphology of the dielectric can have an impact on surface roughness,

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thickness, molecular disordering, etc. Those factors can affect the electrical parameter of
OTFTs. Indeed, it has already been shown that they can negatively impact the carrier
mobility 12,154,166,167.
Consequently, two types of printing methods have been studied: The first one uses only one
activated nozzle, called “Mono-nozzle printing,” and the other uses several nozzles, called
“Multiple-nozzles printing.” In general, multiple nozzles printing can use 1 to 16 nozzles at the
same time. 16 activated nozzles are the maximum number of nozzles available with Dimatix©
cartridge.
The following sub-sections deal with thickness control via drop-overlap and UVO3 treatment
time, as well as the impact onto the morphology of the SU-8 as a function of the printing
methods.

i. Influence of UV-ozone treatment on printed SU-8

In order to find a sufficient condition as a function of UV-ozone treatment time, three
different conditions of UV-ozone treatment were applied to the glass substrate. A drop overlap
of 45 μm has been kept constant to observe the influence of UV-ozone treatment. As shown in
Figure 21(a), the inkjet-printed SU-8 films at fixed drop overlap have a similar thickness of
3 ± 0.6 μm with 90 seconds and 130 seconds. The thinnest thickness of 2.7 ± 0.2 μm was
obtained with 150 seconds of UV-ozone.

(a) 4.0 Drop spacing = 45 m UVO 90s

UVO 130s
3.5
UVO 150s
Layer Thickness (m)

3.0

2.5

2.0

1.5

1.0

0.5

0.0
-200 0 200 400 600 800 10001200140016001800
Scan range (m)

Figure 21. (a) two-dimension cross-sectional profile of SU-8 as a function of UV ozone treatment
time: 90s, 130s, 150s with a fixed drop overlap of 45 μm, and optical microscopic image of inkjet-
printed SU-8 film with UV ozone time of (b) 90s, (c) 130s, (d) 150s, respectively.

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 Film formation is reached using short UV-ozone treatment of 90 seconds. However, as
shown in Figure 21(b), SU-8 film shows many voids and unstable surfaces. We believe that
this phenomenon was due to the short UV-ozone time resulting in low surface energy leading
unstable patterns as also observed for Ag ink. On the contrary to the result of 90 seconds, the
UV-ozone treatment in 130 seconds showed inkjet-printed SU-8 film with stable patterns
without voids. Although the results in the 150 seconds of UV-ozone treatment has the thinnest
thickness but also confirmed that a part of the pattern is collapsed and formed irregular
thickness (Figures 21(c) and 21(d)).
Regarding layer morphology, the 130 seconds of UV-ozone treatment time has been chosen
to form the inkjet-printed SU-8 film.

ii. Thickness control of printed SU-8

The SU-8 films varying thickness deposited by inkjet printing technology have been studied
to achieve the best gate dielectric layer from the electrical point of view. In general, the
thickness of the gate dielectric for efficient OTFT characteristics is targetted as thin as possible
but avoiding gate leakage current. In the OTFT structure, optimized gate dielectric thickness
provides a low voltage drive 168.
(a) Drop spacing (m) (b)
7
30
10 35 Layer thickness
Layer thickness (μm)

6
Layer Thickness (m)

40
8 42
5
45
47
6 50 4
55
4 57 3
59
60 2
2
1
0 30 35 40 45 50 55 60
0 290 580 870 1160 1450 1740 Drop spacing (μm)
Scan range (m)

Figure 22. Influence of drop overlap on the SU-8 film thickness. (a) two-dimension cross-sectional
profile, and (b) layer thickness in terms of the drop spacing. UV ozone treatment is applied to the glass
substrate for 130 seconds.

As shown in Figure 22, drop overlap governs the thickness of inkjet-printed SU-8 film. As
for Tao et al. 100, in this work, sufficient electrical characteristics of OTFT have been obtained
with a thickness of spin-coated SU-8 2002 of 1.2-1.5 μm thick. In our inkjet printing work, the

107
experiments have shown that 1.8 μm thick inkjet-printed SU-8 can be obtained, close to the
thickness of spin-coated SU-8 2002, with a large drop spacing (e.g., 60 μm). However,
increasing the drop spacing (i.e., small overlap size) dramatically leads to voids into the film.
As a consequence, this effect can also provide leakage current. In conclusion, gate dielectric
thinner than 1.8 μm thick cannot be printed using SU-8 2002 epoxy-based ink. In this work,
drop spacing equals 50 μm has been chosen to fabricate stable SU-8 gate dielectric.

3. Summary of the Fabrication process of inkjet-printed

n-type OTFT
In this section, the manufacturing process of n-type OSC based transistors using inkjet
printing technology is presented. The bottom gate bottom contact (BGBC) structure was
employed to implement the fully additive inkjet-printed.

a. Substrate preparation and gate electrode formation

Figure 23. Schematic illustration for processing steps to deposit the gate electrode using Ag NP ink
by inkjet printing, (a) substrate preparation, (b) printing Ag ink with mono nozzle, (c) sintering process
in the oven at 140 °C for 30 minutes, (d) gate electrode formation.

Corning© Eagle 2000 glass was used as a substrate. The substrates were cleaned by a
conventional cleaning process to avoid any surface contamination. Ultra-sonication is
performed for 15 minutes in 99.8 % acetone, 99.8 % ethanol, and then dried under N2 gas flow
after rinsed in de-ionized water (D.I.W.). After cleaning, the glass was directly placed into an
oven at 140 °C for more than 3 hours allowing to evaporate all the solvent. (Figure 23(a)).
The prepared glass substrate was placed onto the printing chuck. The substrate was heated
on the plate at 50 °C to obtain a reproducible pattern shape. Gate electrode is printed using 10
pl droplet volume. Ag NP ink is used as the ink to fabricate the inkjet-printed gate electrode.

108
The substrate temperature and the drop overlap for stable and reliable printing were optimized.
A micro-scaled overlap size of the printing parameter for the electrodes was investigated using
vector test patterns on the same substrate, before printing. Besides, the size of the channel
overlap between the gate and the S/D, essential parameters related to the size of channel overlap
capacitance, has been carefully controlled by the printing simulator and alignment system of
the software in the printing equipment (Figure 23(b)). The inkjet-printed gate electrode was
baked in the oven at 140 °C for 30 minutes (Figure 23(c)). Note that, the purpose of the
sintering step is mainly to provide better metal conductivity and excellent adhesion to the
electrode (Figure 23(d)).

b. Gate dielectric (SU-8) formation

Figure 24. Schematic illustration for processing steps to deposit the gate dielectric using the epoxy-
based ink (SU-8) by inkjet printing, (a) UV-ozone treatment, (b) printing SU-8 ink with mono- or multi-
nozzle, (c) sintering process on the hot plate at 95 °C for 90 seconds, (d) UV exposure and occurrence
of polymerization, (e) sintering process on the hot plate at 95 °C for 90 seconds to 115 °C for 35 minutes.

The un-cross-linked SU-8 2000 series negative photoresist (MicroChem©, Westborough,

MA, USA) is printed as the gate dielectric layer on the top of the inkjet-printed Ag gate
electrode. The 2 ml of the SU-8 ink was fulfilled in a cartridge (Fujifilm© – Dimatix DMP 2831
with 10 pl of the piezoelectric nozzle) after filtered with a 0.45 μm PTFE filter. After that, the
filtered Su-8 was printed.

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 The UV-ozone treatment is used as an effective method that increases surface tension to
form a hydrophilic surface before printing SU-8 (Figure 24(a)). The mono- or multi-nozzle
(16 activated nozzles) can be used to print the SU-8 (Figure 24(b)). After printing SU-8, the
substrate was pre-baked at 95 °C for 1.5 minutes on the hotplate and cooled down to room
temperature (Figure 24(c)). To ensure a cross-linking reaction, the printed SU-8 was exposed
to UV exposure with an energy dose of 50 mW/cm2 (Figure 24(d)). For the last step of the
process for SU-8, the exposed substrate was baked at 95 °C for 1.5 minutes, and ramped the
baking temperature up to 115 °C and baked for 35 minutes (Figure 24(e)). In experimental
results, the thickness and morphology of SU-8 were confirmed that these properties are
controllable by the UV ozone treatment time, the number of active nozzles and the gap between
the nozzle in case of the using multi-nozzle. The final thickness of the printed SU-8 dielectric
layer was found to be around 1.8 ± 0.3 μm.

c. Source and drain electrodes formation

Figure 25. Schematic illustration for processing steps to deposit the source and drain electrodes
using Ag NP ink, (a) UV-ozone treatment, (b) printing Ag ink with mono-nozzle, (c) sintering process on
the hot plate at 140 °C for 30 minutes, (d) source and drain electrodes formation.

The S/D electrodes were inkjet printed on the SU-8 dielectric layer after optimized UV-
ozone exposure equals 2 minutes. As mentioned above, the UV-ozone treatment is also an
essential step in forming a sufficient surface on the deposited SU-8 to print S / D electrodes
(Figure 25(a)). Also, well-controlled UV-ozone exposure time is an effective way to reduce
bulging instability. The bulging instability has to be controlled to get an accurate size of channel
overlap between gate and S/D electrodes, which are related to the overlap capacitance. The S/D
electrodes were inkjet printed on the SU-8 dielectric layer using the same parameters, which is
used for printing the gate electrodes (Figure 25(b)). The inkjet-printed gate electrode was
moved on the hot plate to bake at 140 °C for 30 minutes for the sintering step.
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 d. N-type OSC deposition
In the final step of OTFTs, the n-type organic semiconducting layer (C60, fullerene) was
deposited on the top of the BGBC structure by the evaporation system at room temperature
under vacuum (2 × 10-7 mbar) with constant deposition rate of 0.15 Å/s (Figure 26). After C60
deposition, the first fabricated inkjet printed n-type OTFTs have no post annealing step. During
the optimization process, semiconductors were not printed. More experimental detail to
optimize the process will be precise in the following section.

Figure 26. Schematic illustration for n-type OSC deposition using evaporation system, (a) n-type OSC
(i.e., C60) deposition.

e. Summary of the fabrication process

As presented above, the n-type OTFTs have been fabricated by fully inkjet printing
technology except for the OSC layer, C60, as shown in Figure 27.

Figure 27. (a) inkjet printed BGBC structure of n-type OTFTs with evaporated OSC (C60), (b) process
steps of inkjet-printed n-type OTFTs, (c) optical microscopic image of fabricated OTFT BGBC structure.
111
 Therefore, the processes have been performed as a fully additive process in which
conventional photo-lithography technology is not used for patterning at all.

IV. Optimization of electrical characteristics of

inkjet-printed n-type OTFT

Non-optimized inkjet-printed n-type OTFT

Figures 28(a) and 28(b) show the measured transfer and output characteristics of fabricated
n-type printed OTFTs, respectively. The device presents field-effect mobility (μFE) of 3 × 10-3
cm2V-1s-1 at VDS = 20 V, the threshold voltage (VTH) of 12 V, IDON/IDOFF ratio of 3 × 102, SS of
13 V·dec-1. The extracted mobility value is obtained from equation of drain current in linear
regime. To extract this value, the capacitance of SU8 has been measured around C = 2.36 nF.
(a) IJP OFET before optimization
(b) IJP OFET before optimization
Vgs = 0 V
Vgs = 5 V
Vgs = 10 V
1µ W/L = 5500/110 m
90.0n W/L = 5500/110 m Vgs = 15 V
Vgs = 20 V
Drain Current (A)

Vgs = 25 V
Drain Current (A)

100n 60.0n

10n 30.0n
Vds = 10 V
Vds = 20 V
Vds = 30 V
1n 0.0
-20 0 20 40 60 0 5 10 15 20 25
Gate Voltage (V) Source-Drain Voltage (V)

Figure 28. The first result from inkjet printed C60 OTFTs. (a) Transfer characteristics according to the
VDS = 10, 20, 30 V, (b) output characteristics according to the VGS = 0, 5, 10, 15, 20, 25 V.

Figures 28(a) and 28(b) show electrical characteristics without drastic process
improvements. In other words, it was our first results. However, mainly due to the poor
electrical characteristics (i.e., low μFE, highly positive VTH, poor ION/IOFF ratio and large SS),
efficient circuits cannot be fabricated. Moreover, the high contact resistance was observed in
the output characteristics. It is a key limiting factor determining the performance of the devices
169
. Indeed, experimental results and the simulation predictions have proven that the contact
170
resistance form on a barrier of energy between the source contact and the OSC . The
following sections describe investigations performed to highlight some of the processing
parameters impacting printed OTFT electrical behaviour such as I) gate electrode morphology
112
study, II) surface insulator morphology comparing wavy printed surface and smooth spin-
coated layer, III) insulator surface wettability when it is submitted UV-ozone after printing S/D
contact and Ⅳ) post-annealing conditions and thickness optimization for OSC.

Layer morphology effect

1. Gate morphology
This sub-section deals with the impact of printed gate electrode morphology in comparison
with the evaporated one. Intuitively, it could be anticipated that evaporated one will show better
electrical performances when used in OTFT devices.

Figure 29. Comparison between the inkjet printed and evaporated Ag electrode. Schematic
representations of OTFTs using (a) inkjet printed gate electrode, (d) thermal evaporated gate
electrode. Two-dimensional and three-dimensional cross-section profile of (c) inkjet printed gate
electrode, (d) thermal evaporated gate electrode. Transfer characteristics at VDS = 20 V for 5 OTFTs and
between the uses of the (e) inkjet-printed electrode and (f) evaporated electrode.

113
 Table 3. Comparison of extracted electrical parameters of the fabricated OTFTs using thermal
evaporated and inkjet printed gate electrode.

Deposit VTH VON ΔVHYST SS IDON/IDOFF IG μsat

tech. (V) (V) (V) (V/dec) - (nA) (cm2V-1s-1)
Thermal 7,8 -5 6,1 7 8.102 11 5,5×10-3
evaporation
Inkjet 8,1 -5,5 6,3 6,8 6.102 13 5,9×10-3
printing

To investigate if the gate morphology affects the electrical properties of OTFTs, evaporated
Ag electrode and printed one was applied to the OTFT. The evaporated gate pattern has been
fixed to the same dimensions (width and length) with the one fabricated by the inkjet printing.
The thermal evaporated Ag was patterned using a shadow mask. The inkjet-printed SU-8 gate
dielectric layer was 1.6-1.8 μm thick with a small wavy profile. The thermal evaporation was
used to deposit C60 onto the BGBC structure.
As shown in Figures 29(a) and 29(b), the fabricated OTFTs show the same morphologies
except for the gate electrodes. As shown in Figures 29(c) and 29(d), the evaporated Ag
electrode has a flat surface on the top of the electrode, in contrary to the inkjet-printed Ag
electrodes. The comparison of the I-V characteristics at VDS = 20 V are shown in Figures 29(e)
and 29(f) and are summarized in Table 3. The evaporated gate electrode has a little bit higher
“on current,” but a significant trend is not highlighted with inkjet-printed one. In conclusion,
the slight increase in ION is difficult to attribute to the effect of gate morphology. The same
conclusion can be drawn on the other crucial electrical parameters (field-effect mobility in the
saturation regime, SS, gate current IG).
Consequently, the morphology of the gate electrode does not significantly affect the
electrical characteristics of the OTFTs. A limiting factor in OTFT performances could also be
due to when processing gate dielectric or S/D electrodes. Hence, the next-sections aim at
determining if the limiting factor comes from the gate dielectric and S/D electrodes.

2. Processing and morphology study of Su-8

A comparison between a smooth spin-coated and inkjet printed wavy surface has been done
to evaluate the gate dielectric morphology effect on electrical characteristics of OTFT, as
shown in Figure 30.
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 Figure 30. OTFT fabrication steps, including the variant steps for gate dielectric (SU-8) layer
fabrication. (a) Gate inkjet printing using silver nanoparticles-based ink on the substrate, preparation
of (b) spin coating SU-8 and (c) Inkjet-printed SU-8 with the overlapping distances. Inkjet-printed Ag
S/D on (d) spin-coated SU-8 and (e) inkjet-printed SU-8. Note that only the SU-8 profile varies for this
set of experiments. Adapted from ref. 150.

The process variants used to fabricate the gate dielectric layer are described below:
Gate electrodes have been inkjet-printed using silver ink for all OTFTs, as shown in
Figure 30(a). The gate electrode process was not changed in this set of experiments. After this
step, the SU-8 has been deposited using two different techniques: spin coating, as shown in
Figure 30(b), and inkjet printing, as shown in Figure 30(c). Inkjet-printed SU-8 requires more
163
experimental parameter adjustment than a spin-coated one , and these printing parameters
induce various printed SU-8 morphologies. Moreover, the inkjet-printed gate dielectric layer
147
typically shows a wavy shape mainly due to the coffee ring effect . On the contrary, spin-
coated SU-8 shows a smooth surface. Height of wavy peaks and valleys are mainly governed
by the overlapping distance (Olines) between adjacent lines, as highlighted in Figure 30(c), and
by overlapping distance (Odrop) between adjacent droplets. After depositing the SU-8 with two
different morphologies, Ag S/D electrodes have been inkjet-printed for both gate dielectric
layer configurations, as shown in Figures 30(d) and 30(e). Finally, n-type OSC (C60) was
thermally evaporated on the BGBC OTFT structure using the same parameters.

 Spin coated SU-8 versus inkjet printed SU-8

The electrical properties of inkjet-printed OTFTs according to the morphology of the SU-8
dielectric layers are compared in Figure 31.

115
 (a) 1μ (b) 1μ
VDS = 20 V VDS = 20 V

100n

Drain current (A)

100n
Drain current (A)

10n 10n

1n Ag gate / Spin coated Su-8 / Ag S/D 1n Ag gate / Inkjet printed Su-8 / Ag S/D

-20 0 20 40 60 -20 0 20 40 60
Gate voltage (V) Gate voltage (V)

Figure 31. OTFT transfer characteristics as a function of gate dielectric layer fabrication with inkjet-
printed Ag S/D electrodes. Transfer characteristics of five devices using (a) spin-coated SU-8, (b) Inkjet-
printed SU-8.

Table 4. Summary of electrical parameters as a function of processing techniques for the gate
dielectric layer (spin-coating and inkjet printing). Note that source and drain contacts are inkjet-printed
silver. μ0, VTH, subthreshold slope (SS), and contact resistance Rc are calculated using the Y-function
method 171.

W/L SU-8 μ0 VTH SS

Processing VDS = Rc (Ω)
thickness
Tech. 20 V (μm) (cm 2 V -1 s -1 ) (V) (V/dec)
(μm)
Avg. 5000/ 1.5 1.2×10-2 8 6.5 6.5×107
Spin
Stand. 115 - 4×10-3 1.2 0.3 2×107
Dev.
Avg. 5000/ 1.7 7.4×10-3 9 6.5 6.9×107
Inkjet
Stand. 115 - 2×10-3 2.8 0.2 1.8×107
Dev.
Moreover, the relevant electrical parameters are summarized in Table 4. Five transfer
characteristics for each morphology have been measured under the same conditions. Results
are shown in Figures 31(a) and 31(b) and Table 4 did not highlight any clear trends. Note that,
the intrinsic mobility (μ0) seems to be a bit higher for the spin-coated gate dielectric layer,
which could be correlated to a smoother gate dielectric surface. In conclusion, the relationship
between morphological and electrical characteristics in the optimization process for inkjet-
printed OTFT was confirmed. The morphology is not a limiting factor to achieve
efficient OTFT.

116
 3. Optimization of n-type OSC; C60

a. Surface energy dependence between OSCs and gate

dielectric layer
The interface between OSCs and gate dielectric surface, the region where charge transport
takes place, has a crucial role for inkjet-printed OTFTs.
As we mentioned above, UV-ozone treatment has been used in our study as a powerful
surface chemical modification to switch from hydrophobic to hydrophilic state. This step is
crucial in order to fabricate continuous drain and source patterns onto SU-8, from the
processing point of view. In addition, the UV-ozone time has been investigated to see its impact
on device electrical behaviour. Therefore, the formation of a well-organized OSCs layer is
essential to reach a stable interface. Thus stable interface regardless of deposition technic is
often due to the molecular disordering depends on the surface energy as shown in Figure 32 172.

Figure 32. Schematic of (a) conformations at the semiconductor/gate dielectric interface as a

function of different surface energies, adapted with from ref. 172, (b) difference in the organization of
molecular packing on the interface between semiconductor/gate dielectric layers due to the surface
energy.

Many studies have been made on interface phenomena, such as surface-mediated molecular
ordering, surface dipoles, and semiconductor alignment.
To investigate the surface energy dependency on the electrical characteristics of inkjet-
printed OTFTs, UV-ozone has been performed on the printed structure (i.e., interface between
S/D contact/OSC) before depositing C60. Electrical properties behaviour as a function of UV-
ozone irradiation time has been evaluated, as shown in Figure 33.
117
 The transfer characteristics (Figure 33(a)) highlight that the UV-ozone irradiation has a
harmful impact on OTFT electrical performances. The most obvious effects of UV-ozone on
the electrical parameter is the value of IGS, hysteresis gap (∆Vhysteresis) and VTH. Notably, the
characteristics of the hysteresis gap (ΔV) and VTH (V) increased when UV-ozone irradiation
time is increased (Figure 33(b)). Field-effect mobility (μ), one of the most studied electrical
parameters of an OTFT, is also rapidly degraded from 2.3×10-2 to 0.4×10-3 cm2V-1s-1
(Figure 33(c)).
(a) (b)
120.0n
100.0n Igs
1µ 80.0n

Igs (A)
60.0n
40.0n
Drain Current (A)

20.0n
0.0
100n
Hyseteresis gap (V)
14
12 Hysteresis
10
8
10n 6
4
Without UVO3 2
With UVO3 1 min. 20
18
1n With UVO3 2 min. 16
Vth (V)
Vth (V)

With UVO3 3.5 min. 14

With UVO3 6 min. 12
10
8
100p 6
-20 0 20 40 60 w/o UVO3 UVO3 1 min UVO3 2 min UVO3 3.5 min UVO3 6 min
Gate Voltage (V) UVO3 irradiation time (min.)

(c) 2.5x10 -2

Field effect mobility ()

-2
2.0x10
)
-1 -1
Mobility (cm V s

-2
1.5x10
2

-2
1.0x10

-3
5.0x10

0.0
w/o UVO3 UVO3 1 min. UVO3 2 min. UVO3 3.5 min. UVO3 6 min.

UVO3 irradiation time (min.)

Figure 33. Comparison of electrical characteristics according to the UV-ozone irradiation time. (a)
Transfer characteristics, the trend of electrical parameters, (b) IGS, hysteresis gap, threshold voltage,
(c) field-effect mobility.

These experimental results allow to draw the following statements: At first, UV-ozone
irradiation can be used to make excellent wettability on the surface of the insulating layer
(SU- 8), from a processing point of view (i.e., source and drain printing). However, the UV-
ozone creates new chemical groups on the surface of the gate dielectric, such as C-O, C=O,

118
and O-C=O. These functional groups induce the shift of the VTH, certainly due to the trapping
effect of the electron. In that case to obtain charge neutrality, more hole carriers are induced,
and it causes the positively shifted of VTH. Moreover, the generated electron trapping state is
also related to the stability of the OTFT device, thus ∆Vhysteresis is also increased. The trap also
173
has an impact on mobility as hole trapping states under accumulation conditions . In
conclusion, the surface wettability of SU-8 has a significant effect on OTFT electrical
behaviour.

b. Impact of OSC morphology

① Impact of OSC post-annealing method
The conventional post-annealing treatment has been applied to the OTFT. Its effect has been
studied as a function of the following steps:

 Step I (Heating): the post-annealing temperature increases from room temperature

to 200 °C.

 Step II (Duration): the post-annealing temperature equals 200 °C for 10 minutes.

 Step III (Cooling down): the post-annealing temperature decreases from 200 °C to
room temperature.

All the fabricated OTFTs have the same channel dimension (W/L = 5000 μm /100 μm). The
experiments were designed in four groups. The process condition of each group is summarized
in Table 5 as follow:
Table 5. The designed experiments, scenario divided into four groups varying the post-annealing
process.

Group Step
I II III
(a) O200 °C)
(25 °C to O 10 min.)
(200 °C for (200 °CO
to 25 °C)
(b) O O X
(c) X O X
(d) X O O
*O: included step, X: not included step

119
 VDS=20V VDS=20V
(a) 10μ
(b) 10μ
T1 T1
T2 T2
1μ T3 1μ T3

Drain Current (A)

Drain Current (A)
T4 T4
T5 T5
100n T6 100n T6

10n 10n

Group (a) Group (b)

1n 1n
STEP Ⅰ : 25 ℃ to 200 ℃ STEP Ⅰ : 25 ℃ to 200 ℃
STEP Ⅱ: Duration 200 ℃ (10 min.) STEP Ⅱ: Duration 200 ℃ (10 min.)
100p STEP Ⅲ: 200 ℃ to 25 ℃ 100p
-20 0 20 40 60 -20 0 20 40 60
Gate Voltage (V) Gate Voltage (V)
VDS=20V VDS=20V
(c) 10μ
(d) 10μ
T1
T1 T2
T2
1μ T3
1μ T3 T4

Drain Current (A)

Drain Current (A)

T4 T5
T5
100n T6
100n

10n 10n

1n 1n Group (d)
Group (c) STEP Ⅱ: Duration 200 ℃ (10 min.)
STEP Ⅱ: Duration 200 ℃ (10 min.) STEP Ⅲ: 200 ℃ to 25 ℃
100p 100p

-20 0 20 40 60 -20 0 20 40 60
Gate Voltage (V) Gate Voltage (V)

Figure 34. Comparison of transfer characteristics of inkjet-printed OTFTs depending on post-

annealing methods.

The transfer characteristics of four annealing process groups are shown in Figures 34(a to d)
for 6 OTFTs. In Figure 34(a), the on-state drain current (IDON) from 1 to10 μA and the off-
state drain current (IDOFF) of less than 1nA is observed. When step III is removed, as shown in
Figure 34(b), the transfer characteristic has been improved. Even if higher off-state drain
current is observed, the IDON is higher and more uniform. Figure 34(c) shows the electrical
characteristic when only step II is performed. The IDON of OTFTs is not uniform. High off
currents were observed in comparison with the other experiments. For the last post-annealing
condition (Figure 34(d)), IDOFF is as good as conditions depicted in Figure 34(b) but IDON is
lower with the worst uniformity.
Among these four different conditions, the most efficient OTFT characteristic is observed
with the group (b). Consequently, the heating and the cooldown process with a gradual
increase and decrease are critical parameters influencing the post-annealing step of OTFTs. In
the next sub-section, an optimized temperature is determined using this post-annealing
processing method.
120
 ② Impact of OSC post-annealing temperature; electrical characteristics and
morphology
- Electrical characteristics as a function of post-annealing temperature

Figure 35. (a) transfer characteristics (VDS = 20V) and (b) output characteristics (VGS = 20V),
measured as-fabricated varying post-annealing temperature, respectively. The applied post-annealing
temperatures equal to 160°C, 200°C, and 250°C.

Table 6. The extracted electrical parameters of inkjet-printed OTFTs with four different post-
annealing temperatures.

VTH SS µFE Rc µ after Rc IDOFF

TA (°C) Ion/Ioff
(V) (V/dec.) (cm2V-1s-1) (cm2V-1s-1) (A)
(Ω)
Unannealed 19.3 9.3 5.3x10-5 8M 5.8x10-5 16 p 1.25×102
160°C 20 7 4.2x10-3 2M 4.47x10-3 34 p 4.7×103
200°C 11.2 4 1.44x10-2 1.7 M 1.46x10-2 0.2 n 2.9×103
250°C 6.2 6.2 1.46x10-2 2M 1.5x10-2 2n 2.7×102

Post annealing temperatures equals 160 °C, 200 °C, 250 °C have been compared with no
annealed (as-fabricated OTFT) condition. For a reliable comparison of the electrical
characteristics, five OTFTs were measured according to each condition, as shown in Figure 35.
A represented transfer and output characteristics as a function of the annealing temperatures
are shown in Figures 35(a) and 35(b). The extracted electrical parameters are summarized in
Table 6. A strong impact of annealing temperature was observed. Indeed, the field-effect
mobility and the off-state drain current (IDOFF) were gradually increased as a function of post-
annealing temperature whereas the contact resistance (RC) was gradually decreased. Besides,

121
with the increase of the post-annealing temperature, the off-state drain current is gradually
increasing from 1.6 pA to 2 nA, and IDON/IDOFF ratio increases from 1.25 × 102 to 2.7 × 102.
The increase of IDOFF seems to be due to the quality improvement of the active layer after
annealing including a better conductivity. The VTH is shifted in the negative in comparison with
the as-fabricated result. With the annealing temperature increasing, the VTH shifting refers to
the changes in interfacial properties between the gate dielectric/OSC interface, such as the
174 175
generation of dipoles in the interface , the impureness of the OSC , the interfacial state
176
and the charge trap density . Consequently, the OTFT with the post-annealing temperature
at 200°C exhibits the most suitable characteristic among four different conditions for circuit
implementation.
However, although the decrease in trap density with increasing temperature is well-known
in the literature, additional experiments were performed. In particular, the improved field-effect
mobility among its improved electrical parameters as a function of post-annealing temperature
is important to understand for the goal of this study. It can be related to the OSC grain size.
Thus, it will be measured with AFM analysis and reported in the next section.

- Morphology of OSC as a function of post-annealing temperature

The effect of the post-annealing temperature on the grain size of OSC, the morphology of
the OSC, was analyzed by Atomic Force Microscopy (AFM) measurement. An Atomic Force
Microscope (AFM VEECO Di Caliber) was utilized in tapping mode on an area of 1 × 1 µm2.
Here, the superstructure (τs) corresponds to the grain size and the equivalent root mean square
(RMS) roughness (σs), the height of the superstructures of the 1D profile of the AFM were
shown in Figure 36.

122
 Figure 36. 2D (1 × 1 μm) AFM images, corresponding 3D enlarged (0.5 × 0.5 μm) and corresponding
1D profile along the dash line of C60 thin film with different post-annealing temperatures of (a) room
temperature (as-fabricated), and (b) 160 °C,(c) 200 °C, and (d)250 °C.

Table 7. Average distance between domain, RMS roughness and grain size.

Annealing
RMS Roughness (nm) Grain Size (nm)
Temperature (°C)

As-Fabricated 1.4 4.7

160 1.8 7.7
200 1.9 13.5
250 2.7 14.2

C60 morphological behaviour as a function of post-annealing temperature has been measured

using 2D and 3D AFM scans and horizontal profile lines (Figure 36). Table 7 summarizes the
morphological parameters such as roughness and grain size.
The 1D profile in Figure 36 highlights morphologies that could reveal an organization at a
larger scale. Indeed, the distance between two deeper adjacent gaps marked by the red arrow
in Figure 36 could indicate τs of C60 OSC. The average distance between domains for as-

123
fabricated (at room temperature), 160 °C, 200 °C, and 250 °C were 0.10, 0.12, 0.16, and 0.22
μm, respectively.
2D AMF images show that the C60 OSC after post-annealing at 160 °C had enhanced grain
size and RMS roughness compared to as-fabricated one (i.e., non-annealed OSC). The
roughness and the grain size are σ = 1.4 nm, τ = 4.7 nm for the no annealing devices
(Figure 36(a)), and σ = 1.8 nm, τ = 7.7 nm for 160 °C (Figure 36(b)). Meanwhile, 200 °C
(Figure 36(c)) and 250 °C (Figure 36(d)) have higher roughness (σ = 1.9 nm and σ = 2.7 nm,
respectively) indicating larger grain size (τ = 13.46 nm and τ = 14.2 nm, respectively).

- Relationship between the OSC morphology and the electrical characteristics

A comparison between the electrical characteristics of OTFTs and the OSC morphology was
carried and shown in Figure 37. Based on Table 8, the usual electrical parameters were plotted
as a function of post-annealing temperatures (Figures 37(a)). Interestingly, in Figure 37(b) it
is shown that the field-effect mobility follows the same trend than the grain size: they rapidly
increase until 200 °C and "saturate" between 200 °C and 250 °C.

Figure 37. (a) Behaviour of the mean threshold voltage VTH MEAN, subthreshold slope SS MEAN and
field-effect mobility, when the annealing temperature increases; (b) Similar behaviour of the mobility
and the grain size as a function of the annealing temperature; (c) Behaviour of the subthreshold slope
SS, the surface roughness and the grain size as a function of the annealing temperature.
124
 The comparison of the behaviour of SS, the RMS roughness, and the grain size as a function
of post-annealing temperature is shown in Figure 37(c). The decrease of SS appears until
200 °C, which can be explained by the decrease in defect density inside the channel relative to
the increase of grain size. This behaviour is in good agreement with the roughness behaviour
correlated to grain size.
Consequently, the relationship between the electrical characteristics and its OSC
morphology as a function of post-annealing temperature has been studied with AFM
measurement. Based on a comparison of the overall electrical parameters, the most suitable
post-annealing temperature was fixed at 200 °C. Although slightly higher mobility was
observed at 250 °C, other electrical parameters (i.e., SS, VTH, RC, ID) showed better results at
200 °C.

③ Impact of OSC thickness on electrical characteristics

For the end of the section, the influence of the OSC thickness on the electrical characteristics
of OTFTs has been investigated. Following the previous study, the OTFTs were post-annealed
by the optimized method at 200 °C. Four different OSC thicknesses of 60, 90, 125, and 250
nm were chosen for the experiments with the same dimension of OTFTs.

Figure 38. (a) Transfer characteristics (VDS = 20 V) and (b) output characteristics (VGS = 20 V) of OTFTs
as a function of the thicknesses of OSC layer; 60, 90, 125, and 250 nm.

The transfer and output characteristics of OTFTs are shown in Figure 38, and the extracted
electrical parameters are summarized in Table 8. Table 8 shows the behaviour of VTH, SS, and
field-effect mobility.

125
 Table 8. Comparison of the main extracted electrical parameters of OTFTs as a function of OSC
thickness.

tC60 VTH SS µFE Rc µ after Rc

Ioff (A) Ion/Ioff
(nm) (V) (V/dec) (cm2V-1s-1) (cm2V-1s-1)
()
60 5,7 5,2 1.8x10-2 2.70 M 1.9 × 10-2 3n 1.8 × 102
90 10,8 3,6 2.9x10-2 0.75 M 3.0 × 10-2 0.1 n 7.8 × 103
125 10,8 4.0 1.4x10-2 12 M 1.7 × 10-2 0.2 n 2.9 × 103
250 11.0 9,2 6.1x10-3 10 M 6.5 × 10-3 0.3 n 8.7 × 102

Figure 39. The behaviour of their mean electrical parameters (Threshold voltage, subthreshold
slope, and mobility).

As shown in Figures 38, 39 and Table 8, the electrical characteristics of the fabricated OTFT
are better for 90 nm thick of OSC. Indeed the lowest off-state drain current, the highest field-
effect mobility and IDON/IDOFF ratio were highlighted. The VTH gradually increases and shifting
in a positive direction as the OSC thickness increases from 60 nm to 90 nm. However, the
increase of VTH is saturated when the OSC thickness is above 125 nm. The shifting of VTH
according to the increasing of OSC thickness is associated with increasing the defect density
inside of thick OSC layer.
Our experimental results have also demonstrated that mobility and contact resistances are
strongly dependent on the film thickness. Contact resistance values were found to range from
nearly 0.75 MΩ to approximately 12 MΩ depending on thickness.

126
 The general trend of the value is that the mobility is decreased for thin films, increases and
reaches a maximum at the mid-thickness film (i.e., 90 nm thick), then decreases for thicker
177
films (above 90 nm thick of OSC). Pesavento et al. presented that mobility differences in
BC structure could be due to much higher contact resistance with the increase of OSC thickness.
Besides, Pesavento showed the thickness dependence of mobility for a very thin OSC, below
30 nm, and it must be due to the growth of the film than contact resistance. As presented in the
literature, in our works, the highest field-effect mobility of 2.9 × 10-2 cm2V-1s-1and the lowest
contact resistance of 0.75 MΩ have been observed with the 90 nm thick of thin OSC layer.
Even though the OSC thickness of 60 nm was thinner than 90 nm, it did not show better
electrical parameters. Rather, its electrical characteristics were similar to 125 nm`s one. In the
case of the 60nm thick, the OSC thickness seems not enough to cover the source and drain
electrodes edge. As shown in Table 8, the OTFT characteristic of 60 nm OSC has a higher
contact resistance than 90 nm OSC, despite its lower thickness. However, such a high contact
resistance due to the coverage of OSC is not a higher impact than a thicker OSC layer (i.e.,
125-250 nm). The extracted field-effect mobility and contact resistance can be used to present
this result. We believe that the impact of the thick layer above 90 nm has come from an increase
of defect density corresponding to the thickness of OSC.
Consequently, the optimized condition to deposit the evaporated C60 OSC layer of inkjet-
printed BGBC OTFT is obtained with an OSC thickness of 90 nm and post-annealing
temperature equal to 200°C.

Optimized inkjet-printed n-type OTFT

Through dedicated works, inkjet-printed n-type OTFT has been optimized as shown in
Figures 40(a), 40(b) and Table 9. Figures 40(a) and 40(b) show the measured transfer and
output characteristics of optimized n-type printed OTFTs, respectively. The extracted electrical
parameters, as shown in Table 9, optimized device presents improved electrical characteristics
with improved field-effect mobility (μFE) of 8 × 10-2 cm2V-1s-1 and IDON/IDOFF ratio of 3.3 × 103
at VDS = 20 V, reduced threshold voltage (VTH) of 4.4 V, SS of 5.3 V·dec-1.

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 Figure 40. The result from optimized inkjet printed C60 OTFTs. (a) Transfer characteristics according
to the VDS = 10, 20, 30 V, (b) output characteristics according to the VGS = 0, 5, 10, 15, 20, 25 V.

Table 9. Comparison of the main extracted electrical parameters of OTFTs.

W/L VDS µFE.lin. Vth Ion/Ioff S.S.

(㎛) (V) (cm2·V -1s-1) (V) ratio (V·dec-1)

Optimized 5100/115 20 8 × 10-2 4.4 3.3 × 103 5.3

Non-
5100/115 20 3 × 10-3 12 3 × 102 13
optimized

The device optimization is mainly performed by morphology studies for each layer and
improved quality of OSC itself using post-annealing. The result presented above demonstrate
that importance of interface morphology between source and drain electrodes and OSC layer,
and quality of OSC layer for OTFT electrical characteristics.

Reproducibility & Uniformity properties

Circuits are made of at least two OTFTs that must have efficient electrical characteristics
(μFE, VTH, SS, etc.) 178. As also discussed above, these parameters will directly impact circuit
behaviours such as operation frequency, voltage excursion, rising and fall time, etc. However,
other parameters are also highly crucial: the reproducibility and the uniformity of the process.
The capacity to reproduce a process from one substrate to another one is defined as the
reproducibility. Uniformity is defined by the capacity to reproduce the process from one device
to another one in the same substrate. Focusing on uniformity: the OTFTs, which have not the

128
same characteristics due to poor uniformity, can induce an abnormal circuit operation. For
instance, considering the logic circuits, it can lead to a wrong truth table.
Note that, a uniform and reproducible process via inkjet printing technology is mandatory to
179
reach for a circuit application because it remains an issue in printed electronics .
Consequently, in the following process uniformity is evaluated.
Experiments dealing with uniformity of the inkjet-printed devices were carried out with a
total of 50 OTFTs with the same dimension (W/L = 5000 μm/115 μm) on a 5 × 5 cm glass
substrate, as shown in Figure 41(a). The device yield reached 88 % (i.e., only six devices out
of 50 functional). They show stable electrical performances as presented using histograms in
Figures 41(b to d).
(b) 50 OFETs on 5 cm size glass substrate (FE)
2

20 FE, avg = 0.04

(cm V-1s-1 )
2

15
Count

10

0
0.030 0.035 0.040 0.045 0.050 0.055 0.060
Mobility (cm V s 2 -1 -1
)

2
(c) 50 OFETs on 5 cm size glass substrate (Vth)
20 Vth, avg = 0.04 (V)

15
Count

10

0
4 5 6 7 8 9
Vth (V)

Figure 41. Analysis of the uniformity in terms of electrical characteristics (a) 50 n-type OTFTs on 5 X
5 cm glass substrate fabricated by inkjet printing, distribution using ‘histograms’ of the (b) field-effect
mobility in the saturation regime (µ FE), (c) threshold voltage (VTH).

In terms of device uniformity, the most important electrical parameters for OTFTs (μFE and
VTH) exhibit almost identical behaviour without significant change. The reproducibility can be
evaluated using the standard deviation of the electrical parameters, called the coefficient of

129
 180
variation (CV) or relative standard deviation (RSD), as presented in literature . For the
device-to-device reproducibility, three substrates with the same conditions as for the uniformity
experiments were carried out simultaneously with the reproducibility one. The CV of mobility
calculated from the standard deviation and the average value was confirmed at 12.5 %.
Although there is no statistical value of CV to verify the reproducibility, the obtained value of
12.5 % is considered to be within the stable range for circuit implementation with comparing
to other literature (CV range for a reproducible process: 20-30%) 180,181.
The errors of the electrical parameters could be due to the variation of the channel geometries
drop jetting inaccuracy of ± 5-15 μm of inkjet printing, as confirmed by experimental results.
Note that, the inkjet printing is known to have a drop accuracy of ±5 μm due to variations in
the flight trajectory of inkjet droplets and their spreading on the substrate surface 153.

Electrical stability
The stability of the developed device was monitored by two different methods, hysteresis
analysis, and constant gate bias stress. Two models are currently used to describe these
stabilities. The first one is called stretched exponential which correlates the carrier
redistribution and the bias stress. The second one is a logarithmic fit of the threshold voltage
182
shift by carrier trapping into a gate dielectric layer. Zhang et al. reported the way to
determine those origins from drain current variation under constant drain-source voltage and
gate-source voltage (VGS, VDS). This measurement could give some information about carrier
density and flat band voltage variation with the following relation:
A stretched-exponential function can describe the bias stress instability based on threshold
voltage shift (ΔVTH) or drain-source channel current decay. A stretched-exponential equation
of ΔVTH proposed by Libsch and Kanicki is given by the following Equation 3.4 183;

𝑡 𝛽 …..................... Eq. 3.4

|∆𝑉𝑇 (𝑡)| = |𝑉𝐺𝑆 − 𝑉𝑇𝑂 | { 1 − 𝑒𝑥𝑝 [− ( ) ] }
𝜏

Where ∆VGS-VTO is approximately the effective voltage drop across the gate dielectric layer,
and τ is the characteristic of the trapping time of carriers, respectively. β is the stretching
exponent. Drain current at saturation region is shown in Equation 3.5. The current after
threshold voltage shift is shown in Equation 3.6.

130
 1 W …..................... Eq. 3.5
ID(sat) = μCi (VGS − VTO )2
2 L
1 W …..................... Eq. 3.6
IDS(t) = μCi [VGS − (VTO + ∆VT (t))]2
2 L

The ration of two current shown in Equation 3.7 is represented as stretched exponential, as
shown in Equation 3.8.

IDS (t) [VGS − (VTO + ∆VT (t))]2 …..................... Eq. 3.7

=
ID(sat) (VGS − VTO )2

IDS (t) t β …..................... Eq. 3.8

= ⅇxp [− ( ) ]
ID(0) τ

(a) 10μ
VDS = 20 V
1μ
Drain current (A)

100n

10n
V = 1.9 V
1n

100p

10p
-20 0 20 40 60
Gate voltage (V)

Figure 42. Electrical stability on inkjet printed OTFTs (a) Hysteresis analysis of inkjet printed OTFT
with the controlled gate dielectric morphology (b) Drain-source current behaviour under constant
drain-source voltage (VDS = 10 V) and gate-source voltage (VGS = 20 V).

As shown in Figure 42(a), the hysteresis allows evaluating the threshold voltage shift with
a forward and backward voltage scan and small hysteresis means stable devices. In hysteresis
analysis, we obtained ΔV = 2.05 V with optimized conditions. In Figure 42(b), the symbols
are the experimental data, and the line is a fit according to Equation 3.8. The experimental
data can be fitted well with Equation 3.8 where the on-current was obtained in the saturation
region. The extracted parameter β reflecting the width of the involved trap distribution is very
low (0.34) and is related to the interface quality between the semiconductor and gate dielectric
layer. The obtained β value is like that of a stable organic transistor obtained by Mathijssen
et al. 184,185. The stability of constant gate bias stress can be compared by characteristic time τ
which is high for a stable device. In literature, τ values vary from 103 to 107 s. The above
131
analysis verified the stability of the developed fully inkjet-printed OTFT with organic gate
dielectric film, silver electrode and C60 as an organic semiconductor.
Consequently, the stability of the developed OTFT was as good as only a 7% decrease in
drain current after 10 minutes of operation. Therefore, the development of the fully inkjet-
printed OTFT was evaluated through good electrical properties and excellent stability. Then, it
is determined that it can be sufficiently used for the implementation of circuit applications.

V. Conclusion
Inkjet printing process, a promising technology, was used as a methodology for the OTFT
process. All the layers of the BGBC OTFTs, except the C60 n-type OSC, have been processed
using the inkjet printing technology as an additive process on-demand without any
photolithography. The experiments were designed according to the set of parameters so that
the optimized inkjet printed n-type OTFTs could be applied to the circuit application. Several
main factors are considered and modified; 1) exploring a significant condition of SU-8 via
morphology control (i.e., thickness), 2) investigation of interface between OSCs and S/D
electrodes according to the surface energy dependence, 3) well-organized molecular packing
for sufficient channel formation, 4) improve the printing accuracy to minimize gate overlap
capacitance avoiding frequency limitation in circuit applications. Finally, the reproducibility
and uniformity of the fabricated inkjet printed n-type OTFTs were simultaneously confirmed
with improved electrical performance. Moreover, highly reliable electrical stability is evaluated
by hysteresis and drain-source current behaviour under constant drain-source voltage.
Unlike the results of primary OTFTs with poor characteristics, the properties of OTFTs
through the optimization process was improved. The applicability of inkjet printing technology
for OTFTs, even without any surface treatment processes, was successfully demonstrated. A
detailed condition for the inkjet printed n-type OFET is provided as follows: 1) the inkjet
printed lines and S/D channel have been adjusted without bulging in optimized condition and
printing accuracy has been satisfied the desired dimension, 2) 1.7-1.8 μm thick gate dielectric
layer, SU-8, is deposited by inkjet printing technology with controlled morphology, 3) the
optimized condition for the evaporated n-type OSC, C60 layer is obtained with an OSC
thickness of 90 nm and post-annealing temperature at 200°C during 5 min. In our best result,
obtained under a well-controlled process and well-crystallized OSC film, the improved inkjet
printed OTFT characteristics presents a field-effect mobility (μFE) of 3.5×10-1 cm2V-1s-1,
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threshold voltage (VTH) of 10.78 V, IDON/IDOFF ratio of 1.4×104, SS of 3.98 V·dec.-1 at VDS =
20 V with less contact resistance and bias hysteresis. The bias hysteresis (∆Vhysteresis) of 0.7-2.7
V between forwarding and backward sweep shows a small gap than initial results. The
improved properties are assumed to be due to the trapping of electrons in the hydroxyl groups
on the surface of the SU-8 dielectric surface and well-crystallized OSC film through various
optimization processes. The gate capacitance, controlled by the considered pattern accuracy
and minimize a bulging occurrence, did not show a significant difference in the device.
However, the impact of gate capacitance is expected to show the difference when it applies to
the circuit application.

133
134
 Chapter 4: Circuit applications using
Inkjet Printed n-Type Organic Thin-Film
Transistors
In Chapter 4, we present the development for various types of unipolar (i.e., only n-type)
circuit applications using C60-based transistors using Drop on Demand (DoD) inkjet printing
technology. The study of the fully additive process using inkjet-printed to fabricate OTFT
structure had one main objective:
Demonstrate the applicability of inkjet printing technology to fabricate digital electronic
circuits.

There are several steps to achieve this goal;

- Step 1: Building and applying an electrical model for printed OTFT to simulate and
design digital electronic circuits.
- Step 2: Understanding and eliminating the main limiting factors that can affect effective
circuit operation of elementary electronic circuits (i.e. elementary logic gates).
- Step 3: Design and fabricate digital electronic circuits (Multiplexer and D-latch) to
validate the inkjet printing technology associated with a simple electrical model.

As has been shown in Chapter 3, inkjet printing technology is a very promising technology
to fabricate uniform, reproducible and electrical stable OTFT. Even the electrical performances
of OTFT were not as high as OTFT fabricated with photolithography technology, we assume
that this fully additive technology could be used to perform more complex electronics. Indeed,
inkjet printing technology, as contactless printing technology, with low-viscosity inks, often
suffers from non-uniformity of the obtained patterns due to the coffee ring effect. However, as
we confirmed in the previous chapter 3, our experiments were based on conditions of the inkjet
printing process with well-defined uniformity and reproducibility. Moreover, the confirmation
of the morphological impact of the gate dielectric layer, the carefully selected materials and
interface and the efforts to improve the pattern accuracy were an aid for improving the electrical
properties of inkjet-printed OTFTs.

135
 Chapter 4 will discuss the potential applicability of printed electronics through our
experimental studies in which devices were fabricated based on the simulation result. As a
proposed approach, the simulation results through modelling before design and fabrication are
to ensure practical experiments. The results from the simulation must be performed for the
exploration of the main limiting factors that can affect the circuit performances. Then, from
simple logic circuits, as inverter and NAND, to complex designed sequential and
combinational circuits, as multiplexer and D-latch, are implemented by fully inkjet printing
technology. This work will open up unprecedented opportunities for future achievements in
ultra-low-cost environmental electronics. The detailed plan for Chapter 4 is summarized by
the flow chart, as shown in Figure 1.

Figure 1. Flow chart of development for inkjet-printed digital circuit process based on the simulated
result.

I. Inkjet-printed applications based on OTFTs

In this section, the applications based on organic electronics using printing technologies will
be shown through several examples performed in the last few years. Printing technologies are
not only used for transistor fabrication but has also been extensively used for the fabrication of
more complex electronic circuits, sensor, and segment, etc. Moreover, the implementation of
several function blocks of digital circuits via printing organic technology is a good challenge
leading to low cost applications 186.

136
 Elementary circuits
As aforementioned, organic-based TFTs can constitute several function blocks of logic
circuits for a unipolar circuit or CMOS circuit. However, the implementation of the CMOS
circuit requires the coordinative properties of both types of TFTs. Moreover, the dynamic
response of logic circuits is directly affected by the performance and resolution of TFTs.
Therefore, in general, the uniform and stable electrical performance of the logic circuits
constituting the circuit applications is required. Moreover, the dynamic response of the logic
circuit can determine the maximum operating speed of the circuit applications.

Figure 2. Ultrathin organic CMOS logic circuits using a stacked structure. (a) Photograph of an
organic CMOS logic circuit on a one-micron (μm) flexible substrate. The total thickness was less than 3
μm. Scale bar, 25 mm. (b) complete structure for the stacked device. (c) Image of the CMOS inverter
constituting the D-FF circuit. Scale bar, 500 μm. The electrical performance of printed transistors in
transfer characteristics of (d) the p-type OTFT with VDS = − 10 V and (e) the n-type OTFT with VDS = 10
V, and in output characteristics of the (f) p-type OTFT and (g) n-type OTFT. Adapted with permission
from ref. 141
141
A representative work has been carried out by Tokito et al. . Their successful
demonstration for CMOS logic circuits with low-voltage operation using printed OTFT devices
and a novel stacked configuration has been employed using SAM modification treatment, as
shown in Figures 2(a-c). The use of SAM treatment on the source and drain electrodes has a
very important role to improve the electrical performances of OTFTs. Their structure is
proposed as a strategic new structure to secure the problems existing in the planar structure.
Moreover, the fabricated printed D flip-flop application is realized via the cooperative

137
properties of the developed n-type and p-type used for balanced complementary logic
functionality, as shown in Figures 2(d-g).
Both OTFT devices showed excellent carrier mobilities over 0.2 cm2V-1s-1. In particular,
field effect mobility of the developed n-type OTFT was the highest level ever reported for
printed complementary circuits. Moreover, the threshold voltage of the fabricated devices was
very close to the ideal value of 0 V. Hence, the digital logic gate, as a D flip-flop, was driven
at a low operating voltage of only 5 V. In addition, the printed inverter gate shows proper
inversion operations at very low operating voltages of 1.5 V. It was operated successfully with
a noise margin greater than 50 % at a VDD from 2 to 10 V. The switch voltage value is closed
to half of the VDD value and an absolute value of defined voltage gain close to ∆Vout/∆Vin. The
sharp switching was also observed, which is a major advantage of CMOS logic gates.

1. Logic inverter
The logic inverter is the most straightforward component of the complementary integrated
circuit. The configuration is based on only two transistors and well suited to prove the
187
capability of the fabricated TFTs to build up more complex circuits . Moreover, a ring
oscillator can be implemented with an odd number of inverters.

Figure 3. Organic inverter with different circuit configurations, (a) and (b) represents unipolar
configuration, while (c) and (d) signify complementary CMOS-like architecture. Unipolar inverter
configuration, where only n-type or p-type semiconductor is attached with a load resistor (a) and (b) a
depletion mode load transistor. (c) Complementary inverter made off two different semiconductors; n-
type and p-type. (d) Complementary like inverter consists of one single ambipolar semiconductor.
Adapted from ref. 188.

Inverters can be classified according to the type of semiconductor layer or the TFT design
configuration. At first, the transistors compositing the logic inverter can be either a single type
138
(n-type or p-type) or complementary type. These are named PMOS or NMOS and CMOS,
respectively. A comparison of the differences in configuration between unipolar inverters and
complementary inverters are depicted in Figure 3 188.
Unipolar inverter configuration is attached with a load resistor, where only n-type or p-type
semiconductor is used (Figures 3(a) and (b)). As shown in Figures 3(c) and (d), “CMOS-like”
logic can be implemented both with the close patterning of two different unipolar n-type and
p-type semiconductors or with a single ambipolar semiconductor 189.
Table 1 summarizes the performance of the five different types of inverters, which is
commonly used. The summarized configuration is used differently depending on the node to
where the pull-up resistance is connected.
Table 1. Comparison of the inverters according to the configurations.

Inverters VOL VIH Noise margin Power

Resistor Weak Strong Poor for low High
nMOS – depletion Weak Strong Poor for low High
nMOS -
enhancement
Weak Weak (Poor
low and high )
for both
High

Psuedo - nMOS Weak Strong Poor for low High

CMOS Strong Strong Good Low
nMOS n-type metal–oxide–semiconductor, CMOS complementary metal-oxide-semiconductor

Moreover, as summarized in Table 1, CMOS inverters have much better performances and
more advantages than unipolar inverters, including a high noise margin and low static power
consumption, etc. It is because one transistor is always in off-state and is a compensation
relationship between the load TFT and the driver TFT using a different type of TFT. As a
consequence, when we compare all types of inverters, only CMOS is superior circuit elements
and can be used for industrial products because of its various advantages.
We can understand a basic operation mechanism of the inverter using an example of a typical
CMOS configuration, as depicted in Figure 4.

139
 Figure 4. Inverter characteristics (a) commonly used CMOS circuit diagram consisting of two TFTs
using n-type and p-type, schematic illustration to describe operation mechanism of the inverter (b) at
VIN = 0 (Low-to-High) and (c) at VIN=VDD (High-to-Low), (d) inverter truth table, and (e) symbol.

Figures 4(a) and (d) show the typical schematic diagrams of CMOS inverter and its truth
table. As schematic descriptions in Figures 4(b) and (c), the operation mechanism of the logic
inverter can be expressed as follows:

 Pull up (Figure 4(b)): when the input voltage (VIN) is a logic value “0 (= Low),”
the output voltage (VOUT) is “1 (=HIGH).”

 Pull down (Figure 4(c)): On the contrary, the input voltage (VIN) is high, and
the output voltage (VOUT) is low. VOUT of an ideal inverter should be equal to VDD
at low VIN.

However, the most important basic concept that needs to be reminded for a CMOS
implementation is the requirement of a balanced p-type and n-type TFT configuration. Finding
the balance between the μFE of the n- and p-type and VTH for all types of semiconductors (e.g.,
inorganic, organic, hybrid) is always a scarcity.
The static and dynamic characteristics are used to evaluate inverter properties. In general,
voltage-transfer characteristics (VTCs) are considered as a static characteristic of the basic
inverter, as shown in Figure 5(a). Considering the shift of Vm (equal to VDD/2) value, it is
related to the μFE and VTH of TFTs consisting of the presented inverter. It is hard to observe the
ideal switching point for a CMOS inverter, as Figure 5(a). The shift of Vm value can properly
be adjusted by the design factor (β). In other words, the dimension (W/L) of the TFTs and their
ratio that constitutes the inverter can be adjusted.

140
 Noise margins (NMs) are also a parameter to evaluate the static behaviour of inverter
characteristics with the VTC curve, as shown in Figure 5(b). The VTC characteristic refers to
the operating regimes of the TFT that constitutes the inverter according to the threshold voltage.

Figure 5. Static characteristics of CMOS inverter, (a) VTC and (b) corresponding noise margins, (c)
rise and fall time.

Table 2. Characteristic operation regions of CMOS inverter.

Voltage-threshold n-type p-type

Vtn Cut-off Linear
VIL Saturation Linear
Vm (VDD/2) Saturation Saturation
VIH Linear Saturation
VDD + Vtp Linear Cut-off

141
 The relationship between the voltage and VTC characteristics in each region is summarized
in Table 2 based on CMOS design, as shown in Figure 5(a) (CMOS is used to define the
standard inverter characteristics). In this case, the NM can be defined as the side of the largest
square that can be inscribed within the loop formed by the VTC curves of an inverter pair 189.
The value is indicated as the “dVOUT/dVIN = -1” slope criterion, as shown a red straight line in
Figure 5(a). The maximum/minimum input and output voltages (VIH/V IL and VOH/VOL) are
defined by the critical points where gInv = 1. The two different levels, high and low, of the NMs,
are given by the following Equation 4.1 and 4.2:

𝑁𝑀𝐻 (𝑛𝑜𝑖𝑠𝑒 𝑚𝑎𝑟𝑔𝑖𝑛 𝑎𝑡 ℎ𝑖𝑔ℎ 𝑙𝑒𝑣𝑒𝑙) = 𝑉𝑂𝐻 − 𝑉𝐼𝐻 ….................. Eq. 4.1

𝑁𝑀𝐿 (𝑛𝑜𝑖𝑠𝑒 𝑚𝑎𝑟𝑔𝑖𝑛 𝑎𝑡 𝑙𝑜𝑤 𝑙𝑒𝑣𝑒𝑙) = 𝑉𝐼𝐿 − 𝑉𝑂𝐿 ….................. Eq. 4.2

Rise time (tr) and fall time (tf) are also important characteristics of circuit applications. The
term of rise time indicating the time it takes for the leading edge of a voltage (or current) to
rise from its minimum value to its maximum value. Rise time is typically measured from 10 %
to 90 % of the value, as shown in Figure 5(c). In contrary to rise time, the term of fall time
indicating the time it takes for the voltage (or current) to move from its maximum value to its
minimum value, as also shown in Figure 5(c). For instance, the rise time is given by the
following Equation 4.3:

𝑡𝑟 = 𝑡0.9 − 𝑡0.1 ….................. Eq. 4.3

Where, t0.9 is a time at which reaches 90 % of its steady-state value, and t0.1 is a time at which
reaches 10 % of its steady-state value.
In a resistive circuit application, the rise time is mainly depending on the capacitance and
inductance. This capacitance dependence of rise time causes a delay in voltage (or current) and
it indicates how well the system preserves a fast transition in the input signal.
So far, in the case of OTFTs, the properties of n-type OTFTs still have many significant
challenges to improve performance and to be used in applications, including CMOS circuits.
Although contradictory, most of the reported results in the literature are still mainly focused on
pMOS, but not in nMOS circuits, as summarized in Figure 6 189. In other words, implementing
high-performance organic-based CMOS circuits for digital applications requires more effort to
improve the performance of nMOS OTFTs.
142
 nMOS
pMOS
CMOS

CMOS
pMOS 25.64%
66.67%

nMOS
7.69%

Figure 6. Number of representative works in literature along with the organic ring oscillators
fabricated using solution processes corresponding circuit configurations from ref. 189.

2. Logic NANDs
The next step towards more complex design circuitry beyond inverter is behaviour of 2-input
NAND (not-AND) gates. Design of 2-input nMOS NAND was used in this study, it is
configured based on one load TFT and two drivers TFTs. The logic given for a NAND gate is
the opposite to the AND gate and it performs the complements of the output. Two or more
inputs are applied to the logic NAND compared to an inverter. These are given names as a “bit”
in front of the “NAND” according to the number of inputs. That is, when a NAND has two
inputs, it is named as a 2-bit NAND. Even there are many inputs, there is only one output.
The logic NAND is operated in such a manner as follow:
When either input voltages A (= VIN1) or B (= VIN2) are logic values “0 (= LOW),” the output
voltage (VOUT) returns to “1 (=HIGH),” whereas the NAND gate gives “LOW” when both
inputs are “HIGH.”
Logic NANDs are the most frequently logic gates used to design more complex digital
circuits.

3. Oscillator
The first demonstration of fully printed organic ring oscillators has been made in 2004 by
Knobloch et al. 190. Their ring oscillator was fabricated by a specific printing technology and
doctor blade coating techniques. P3HT was used as a p-type semiconducting material. The
supply voltage was VDD= 90V and the intrinsic oscillation frequency was Fosc=0.86 Hz. Besides,
Knobloch also demonstrated a seven-stage ring oscillator using different semiconductor

143
materials such as PDHTT due to the better electrical performance than P3HT in terms of the
IDON/IDOFF ratio and VTH. However, lower field-effect mobilities of PDHTT affect the
oscillation frequency of the fabricated seven-stage ring oscillator. Another reported result by
191
Hambsch et al. has been demonstrated the production of 50,000 transistors based on poly
(tri-phenylamine) using gravure printing technique and characterized regarding uniformity
through random examination. They obtained a yield of approximately 75 % of functional
OTFTs and a five-stage ring oscillator. The fabricated application can satisfy the desired
properties in terms of uniformity. However, differences between positions of TFTs with a more
considerable distance from each to another indicate the necessity for further improvement of
reproducibility and stability of the printing process. Their too thin low-k insulating layer in
comparison with the roughness of the source-drain electrodes has been led to low IDON/IDOFF
ratios about 102. As a result of Hambsch, the limitation in performance of the printed ring
oscillator with F=2.5 Hz at supply voltage of -100 V has been found. This result can be
explained by the relatively large channel lengths of 100 μm and low mobility of the
192
semiconductors. Kampa et al. have been produced in an improved complementary ring
oscillator using printing technology. All layers were additively deposited by gravure,
flexographic printing and neither additional patterning nor interconnecting step was involved.
The field effect mobilities of n-type and p-type transistors in their circuits showed similar
values of 10-3 cm2V−1s−1, as well as equivalent threshold voltages close to 0 V.
Table 3. Comparison of parameters of printed unipolar and complimentary ring oscillator circuits
192
.

Complementary
Unipolar Unipolar
(Kempa et al.)
Number of stages 7 5 5
Channel length 100 μm 100 μm 70 μm
Supply voltage 80 V 100 V 100 V
Frequency 3.9 Hz 2.5 Hz 134 Hz
Scaled stage delay (after (1)) 14 ms 39 ms 1.5 ms

They show a comparison of parameters of printed unipolar and complimentary ring oscillator
circuits, as shown in Table 3. The values have no significant improvement of charge-carrier
mobility, the gain in switching speed by more than a factor of 10 can be mostly attributed to

144
the influence of complementary circuitry. They obtained an intrinsic oscillation frequency of
134 Hz using a complementary organic printed transistor with gains of 5 and a scaled stage
delay of 1.5 ms.
An accomplishment of the fabricated ring oscillator in a 3D configuration was reported by
193
Hubler et al. . Their fully printed ring oscillator circuit, which has not only horizontally
arranged parts but also the stages of an inverter are vertically stacked on top of each other in
four through-connected substrate layers. Notably, here the intrinsic oscillation frequency was
reported as 5.9 Hz for the 3D stacked ring oscillator at a supply voltage of 50 V. In recent
progress, the best demonstration of fully printed ring oscillators was made by Mandal et al. 194.
They demonstrated a ring oscillator capable of operating at a reported oscillation frequency of
2 kHz when biased at 100 V, as shown in Figure 7.

Figure 7. Demonstration of fully printed organic ring oscillator. The maximum oscillation frequency
of 30 μs measured, and 90 % transparency and bendability up to 1 % tensile strain is obtained. Adapted
with permission from ref. 194.

To provide these devices, fully inkjet printing techniques were used with highly conducting
polymer, a dielectric polymer and P(NDI2OD-T2) and DPPT-TT as n- and p-type organic
semiconductors respectively. Moreover, all processes with scalable printing techniques have
been done at low temperatures on plastic substrates (PEN). In particular, the high mobility
characteristics of two different types of transistors, achieving saturation field effect mobility of

145
0.4 cm2V−1s−1 and 0.22 cm2V−1s−1, have been highlighted. As a result of Mandal, we can expect
the effect of a circuit composed of transistors with high mobility compared to many other
previous works. Moreover, the main advanced information of these results can show that a key
aspect in obtaining such a well-balanced complementary transistor characteristic is the
achievement of high performing n-type FETs despite the use of high work function conducting
polymers. A minimum time response of 30 μs was measured for the rings corresponding to the
shortest stage delay reported so far for truly all printed polymer circuits on plastic substrate.
Besides the properties of their superior printed organic electronics, additional and considerable
results are a 90 % transparency and bendability up to 1 % tensile strain.

Digital circuits
Different types of logic gates (i.e., logic inverter, NAND, etc.) can be used to build a wide
variety of the different digital circuits in order to perform the desired function. They can be
classified into two categories according to the operation behaviours of circuits, as follows 195:
Figure 8 illustrates the difference in the operating characteristics of two different types of
digital circuits in a block diagram.

Figure 8. Block diagrams of digital circuits (a) combinational circuit, (b) sequential circuit, which is
consisting of a combinational circuit and memory elements.

Understanding and implementing the combinational and sequential circuitries are crucial for
data comparison and code generation task advanced applications. Furthermore, the task can be
used to verify the feasibility of printing technology for complex designed circuits. In this
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section, as typical combinational circuits and sequential circuits, 2 to 1 Multiplexers and D-
latch were fabricated using inkjet printing technology based on n-type organic OTFTs and were
evaluated.

1. Combinational circuits
Output variables are dependent only on the present input variables. In other words, when the
gate of the circuit receives the input signals, they are immediately combined to produce the
final output. These types of digital circuits do not store data and the circuits do not rely on the
clock signal. The combinational circuits have no memorial behaviour. Therefore, these types
of circuits do not require feedback. These circuits can be categorized into three variations, such
as arithmetic and logical functions, data transmission and code converters. The arithmetic and
logic circuits are the adders, subtractors, comparators, PLDs, etc. The data transmission circuits
are multiplexers, demultiplexers, encoders, etc. code converter circuits are BCD and 7
segments. The combinational circuits are typically faster than sequential circuits and easier to
design.

2. Sequential circuits
Output depends on the present input as well as the past output. Notably, these types of digital
circuits should have memory elements, which can store a past data inset of the circuits. In other
words, sequential circuits require feedback and a clock signal is then used to perform triggering
of the function. The characteristic of this circuit is that the output state changes in the order of
input. It means that the sequential circuits are consisting of a combinational circuit and memory
elements. These circuits can be categorized into two variations, such as synchronous and
asynchronous circuits. Latches, flip-flops, and registers are defined as the sequential circuits.
As aforementioned in the definition of combinational circuits, the sequential circuits are
typically slower than combinational circuits and they are comparatively harder to design with
more requirements.

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 II. Development of inkjet-printed inverter based
on n-type OTFTs

Inverter with a discrete load resistance

The inkjet printing process to fabricate Organic Thin Film Transistor has been optimized
and detailed in Chapter 3. In this section, we will focus on the dynamic behaviour of such
OTFTs. As the goal of this thesis is to fabricate digital circuits with inkjet printing technology,
we have to analyse the dynamic limit of this technology.
First of all, a single N-type Printed OTFT has to be studied. Then, we choose an elementary
digital component. An inverter made of printed OTFTs as a driver associated with discrete
resistance is the simplest digital device we can characterize.
In the next section, we will propose to measure the frequency limitation of a single OTFT
associated with two different resistance values.

1. Output versus load resistance characteristics

According to output characteristics of OTFTs, we fixed supply voltage VDD to 25V. Due to
low current values ID in OTFT, we have to take account of several considerations:

- Output voltages must be measured through a follower circuit made of high input
impedance OPA.
- Resistance RDS of OTFT channel will be very high and will generate noise in
the measurement system
- OTFTs will be not encapsulated and then will be measured into gloves box.
Function generator and oscilloscope will be outside the gloves box and long wires will
be necessary to measure dynamic characteristics of OTFTs.
- Due to the previous consideration and the high value of RDS, the equivalent
capacitance of our measurement system must be evaluated, and time response impact
has to be determined.

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 Figure 9. (a) inverter configuration using the optimized OTFTs for driver transistor and fixed load
resistance using discrete resistances (100 MΩ and 500 MΩ), (b) load line with the output characteristic
of a transistor, and the intersection in series of VGS (red remarks).

Device operation of the inverter can be estimated by an operating point where the resistance
load line crosses output characteristics of OTFTs for VGS = 0 V and VGS = 25 V. The applied
VGS, from 0V to 25V, has been determined in consideration of the operating range of the
implemented circuits. The configuration illustrated in Figure 9(a) was used for this experiment.
As mentioned in Chapter 3, an optimized inkjet printed OTFT was used as a driver OTFT
(W/L = 5000 µm/ 100 μm). The output characteristics of the driver OTFT, as well as the load
line of a resistance, are shown in Figure 9(b). The inverter operating point is represented with
black points in both cases R = 500 MΩ and R = 100 MΩ. These points correspond to the
intersections between the output curve of OTFT and the load line of resistance.
From a static point of view, the load line of 500 MΩ discrete resistance showed a better
result because it is well-fitted with the output curve of inkjet-printed OTFT. Indeed, with a
500 MΩ resistance, the output voltage of the inverter should be VOUT = 1.6 V when VGS is high
(25 V) and VOUT = 25 V when VGS is low (0 V). With a 100 MΩ resistance, VOUT = 8.3 V when
VGS is high (25 V). Then, a trash voltage of 8.3 V should be observed.
In the next Figures 10(a to b), we have represented the dynamic characterization of this
inverter in both cases.

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 Figure 10. Dynamic response of inverter combining printed OTFT and discrete resistance. Inverter
with a discrete resistance of (a) 500 MΩ and (b) 100 MΩ.

As expected, in the 500 MΩ cases, VOUT for VGS = 25 V is lower than in the 100 MΩ cases.
However, the output value is higher than expected. It could be due to a stress effect on the
OTFT because dynamic measurement is like a constant polarization stress. If the slope, in a
linear region (Figure 10) decreases, meaning a decay of drain current ID, VOUT will increase
when VIN = 25 V.
This result was our first dynamic results obtained with printed OTFT structure and with
evaporated C60 (thickness = 125 nm). The semiconductor was annealed for 5 minutes at 200 °C
but the study on thickness effect of the semiconductor was not yet performed. We presented in
Chapter 3, the effect of semiconductor thickness on OTFT electrical performances. Field
effect mobility has been double using a thickness of 90nm instead of 125 nm. In order to
decrease RDS value and then have less trash voltage on VOUT when VIN = 25V, we decrease the
length of the channel to 100 µm. Even we succeeded to define length channel of 50 µm, this
process was not reproducible and too much difference appears between two OTFT channel
lengths. Then, a channel length of 100µm was fixed to obtain the most reproducible OTFT
structure.
Thus, the same dynamic measurement has been done and is presented in the next Figure 11.

150
 Figure 11. Inverted made of printed OTFT W/L = 5000 µm/100 µm (thickness = 90 nm) associated to
discrete resistance R = 500 MΩ.

The major differences occurring in this dynamic measurement are the low VOUT when
VGS = 25 V and the strong difference between rise and fall times. Fall time is corresponding to
the path to go from VOUT = 25 V to VOUT = 0 V. This transition occurs when the printed OTFT
turns from off state to on state. Then the fall time is related to RDS of printed TFT in on state
and capacitance of combined measurement system and OTFT. Because our system
measurement is not optimized, we have evaluated that the capacitance of the measurement
system is the preponderant one.
In the non-optimized printed OTFT, the discrete resistance has a value close to the RDS of
the OTFT in the on state. Then, rise and fall times were linked to the discrete resistance. In the
case of optimized printed OTFT, the resistance RDS in the on state is lower than the discrete
resistance. Then, the rise time is still linked to the discrete resistance, but the fall time is only
related to RDS of the OTFT in the on state. This observation is really interesting and could help
us to determine the frequency limitation of printed OTFT.
On the next Figures 12(a to d), dynamic response of inverter combining printed OTFT and
discrete resistance has been plotted according to supply voltage VDD.

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 Figure 12. Dynamic response of inverter combining printed OTFT and discrete resistance with (a) VDD
= VIN = 5 V, (b) VDD = VIN = 10 V, (c) VDD = VIN = 15 V, (d) VDD = VIN = 20 V.

First of all, printed OTFT has been successfully integrated into an inverter working with a
supply voltage VDD of 5 V (Figure 12(a)). Of course, the dimensioning of the circuit must be
optimized to improve excursion voltage at VDD = 5V, but this result shows the possibility of
printed electronics to work at low voltage.
If we consider that an equivalent load capacitance of the measurement system combined
with OTFT equivalent capacitance, it will limit the time response. If the rise time is only due
to the discrete resistance with a fixed value of 500 MΩ, the time to load this capacitance will
be equivalent to 3 τ when 95 % of the output voltage will be reached. For the five different
VDD, we sum up the rise time of the output voltage in Table 4.
Table 4. Summary of the rise time of the output voltage associated with the five different VDD.

Supply voltage (VDD) 5V 10 V 15 V 20 V 25 V

Time when output voltage is 95% of
246 264 264 252 262
the final value (3τ) (ms)
τ (ms) 82 88 88 84 87.3

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 Considering the resistance value of 500 MΩ, a simple calculation allows us to estimate the
total parasitic capacitance of our measurement system Cp = 171.7 pF. This value is high and
limits our measurement because organic TFTs have very high RDS value.
When analysing now the fall time related to the printed OTFT, we can evaluate the transition
frequency according to the supply voltage VDD. The result has been plotted in the following
plot, as shown in Figure 13.

Figure 13. Frequency transition in OTFT according to supply voltage VDD of inverter.

In the classical electronic field, when field effect mobility is constant in the semiconductor,
the transition frequency relationship is given by the following Equation 4.4:

𝑉𝐷𝐷 ∗ µ𝐹𝐸 ….................. Eq. 4.4

𝐹𝑇 =
𝐿2

Linear fit of the transition frequency according to supply voltage could give us the mean
carrier mobility in the printed OTFT channel. When this value extracted, carrier mobility is
µ = 6.37 × 10-4 cm²/V.s. This value is largely below from the one extracted with the classical
method in the previous chapter. In conclusion, the field effect mobility usually useful to know
the frequency limitation of electronic circuit is, in the organic electronic field, more difficult to
link to circuit frequency operation.

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 2. Channel length effect on the electrical performance of
Inverter: 100 μm and 200 μm
The channel length (L) impact should be confirmed by the experiment. The use of fixed load
resistance of 500 MΩ is to avoid the other influences than the size of L dependence on driver
transistor. The L of the fabricated driver transistor is 100 μm and 200 μm, and the channel
width is fixed at 5000 μm, respectively. Transfer and output characteristics obtained from two
different L of inkjet-printed OTFTs are shown in Figure 14. In output measurement, VGS was
applied up to 25 V, which value is equal to the maximum of the available supply voltage (VDD)
for our measurement system.
(a) 10μ (b)
600n
1μ
500n
Drain current (A)
Drain current (A)

100n 400n

10n 300n
L = 100 m, VGS = 0 V

1n
200n L = 100 m, VGS = 25 V
L = 100 m L = 200 m, VGS = 0 V
100n
100p L = 200 m L = 200 m, VGS = 25 V
0
-20 0 20 40 60 0 5 10 15 20 25
Gate Voltage (V) Source-Drain Voltage (V)

Figure 14. Electrical characteristics of fully additive n-type OTFT using inkjet-printing technology,
according to the two channel dimensions (channel W/L = 5100 μm/100 μm and 200 μm) (a) transfer
at VDS = 20 V and (b) output characteristics at VGS = 0 and 25 V.

As the electrical characteristics, the various sizes of Ls do not impact on the performance of
the fabricated OTFTs. Although there is a slight difference, it is difficult to define that the L
has an impact. In two different transfer characteristics, they have similar value in on-current
(2.74 ± 0.14×10-6) and showing the differences in S.S., mobility, and off-current, as
summarized in Table 5.

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 Table 5. Extracted electrical parameters from the fabricated OTFTs with two different channel
lengths (channel W/L = 5100 μm/100 μm and 200 μm).

TFT dimension (㎛) 5000/200 5000/100

μ (cm2V-1s-1) 0.07 0.04

VTH (V) 16.25 12.81

ION (A) 2.64 × 10-6 2.93 × 10-6

ION/IOFF ratio
IOFF (A) 1.34 × 10-10 4.81 × 10-10
S.S. (mV/Dec.) 6.0 5.4

However, when it determined with output characteristics, OTFT with L = 100 μm shows the
highest on-current and minimum trash voltage at VGS = 25 V. Larger L (= 200 μm) allows for
easier trap formation on the channel region of the fabricated OTFT, while also increasing
contact resistance. However, these results from the OTFTs with various Ls have not been
showed differences drastically. Therefore, circuits using two different Ls are expected that
couldn`t show L dependence on their electrical behaviour.
VIN
30 VOUT, CHL = 200 m 30
VOUT, CHL = 100 m
25 25
Input Voltage (V)

Output Voltage (V)

20 20

15 15

10 10

5 5

0 0
-1.0 -0.5 0.0 0.5 1.0
Time (sec)
Figure 15. Comparison of dynamic switching characteristics of the inverter (based on a resistance-
load (500 MΩ) and n-type OTFT driver using fully additive inkjet-printing technology) according to the
two different sizes of channel lengths (L = 100 μm and 200 μm) of driver OTFTs.

As shown in Figure 15, the dynamic switching characteristics of two inverters manufactured
on one substrate were compared and analysed at VDD = 25 V. A 500 MΩ of resistance-load
155
was fixed, and the driver OTFTs was used in two different Ls like a single device OTFT. The
extracted parameters, as the low to high trip point (VLH), the high to low trip point (VHL), rise
time (tr) and fall time (tf) were showing differences, but the differences have a value less than
1 V for VLH and VHL and 10 ms for rise/fall time.
By all results, the fabricated inverters have demonstrated that there has in-dependence to
the L, and the electrical properties were not affected. In general, the carrier mobility of the fully
additive or printed electronics has L dependence 196. However, even the shortest L of 100 μm
for the fabricated OTFT has no shorter channel effect and operated as a long channel because
they are micron TFTs. Printed sub-micron TFTs are needed to obtain improved electrical
properties from short channels of OTFTs. In the sub-micron TFTs, the channel resistance
(which is proportional to the L) is significantly smaller than the contact resistance (which is
independent of the L) 197. However, in order to obtain a printed sub-micron TFT, the inherently
low resolution of printing technology must be solved at first. Other process technologies, as
198
the self-aligned process, a self-assembled monolayer (SEM), using a specific ink or a
laser ablation 199, are required to obtain a short L less than 10 μm. However, these additional
methods do not meet the goals of this thesis. Therefore, based on the experimental results, the
next sub-section is carried out to verify the printed circuit.

Fully printed Inverter

Since the load resistance of the inverter has been defined, the entire inverter configuration
(i.e., load transistor and driver transistor) can now be made with inkjet printed OTFTs. Notably,
the first task performed before the implementation of the fully printed inverter is to build a
model based on the measurement results of the diode-loaded inverter. The model verification
is interesting to understand in systematic analysis to estimate electrical performance before
fabrication. Moreover, the proposed method also reduces process failures. Based on the
evaluated simulation result, the development of fully printed inverter can facilitate the
realization of low-cost processes for circuits.

1. Model verification of electrical performance

This section will describe the inkjet-printed circuit applications based on n-type organic
material. A proposed transistor model is adopted based on the established AIM-SPICE

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Level 15 model for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) with
augmentations. As an organic semiconducting layer is a disordered material, we applied a
model based on a-Si:H TFTs. From the electrical characterization of printed OTFT (Transfer
and Output characteristics), Aim-Extract is used to model the TFT from a real measurement.
Then, Aim-Spice is used with this model to simulate electronic circuit behaviour made of
modelled printed OTFT. The nominal process parameters are summarized in Table 6. The
equivalent circuit diagram is shown in Figure 16.

Figure 16. Equivalent circuit diagram of the model ‘Amorphous-Si TFT Model ASIA 2 (level 15)’.
196
Zhang et al. indicated that the model needs attention due to the inadequate use for the
following issues: First, the effect of channel length (L) on carrier mobility (μ) of printed
transistors is not modelled; note that unlike conventional silicon transistors and a-Si: H TFTs,
the carrier mobility of printed transistors is usually L dependent. Second, the AIM-SPICE
Level 15 model can only adequately model the operation of Fully-Additive printed transistors
in the supra-threshold region but not in the linear, sub-threshold, and cut-off regions. Third, the
model does not adequately model the leakage current and the parasitic capacitances of the
Fully-Additive printed transistors. It is mostly because both the leakage current and the
parasitic capacitances in a-Si: H TFTs are much lower. Nevertheless, considering these
inadequate model ‘AIM-SPICE ASIA 2 (Level 15)’, several parameters were chosen for the
modelling of OTFT from Table 6. Variables factors were selected to obtain a good agreement
of the measured result and the fitted model, respectively. Except for the selected parameter,
other various parameters were fixed to match the process conditions of the fabricated transistor
(e.g., gate-drain/source overlap capacitance per meter channel width, Dark Fermi level
position, the thickness of the dielectric layer, etc.).
157
 Table 6. Detailed references of the model ‘Amorphous-Si TFT Model ASIA 2 (level 15)’

Using the model described above and the parameters in Table 6, Figure 17 shows a
comparison of the transfer and output characteristics of the inkjet-printed OTFTs achieved by
the modelling and experimental results.
(a) (b) 3.0µ
10μ Transfer characteristics at Vds = 20 V, Output characteristics at Vgs = 0 , 25 V
and result of Simulated vs Measured Simulated vs Measured result
Drain current (A)
Drain Current (A)

Simulated Simulated 0V
1μ Measured 2.0µ Simulated 25V
Measured 0V
Measured 25V
100n
1.0µ

10n

-20 0 20 40 60 0 5 10 15 20 25
Gate Voltage (V) Drain-source Voltage (V)

Figure 17. Model verification of electrical performance of proposed inkjet printed OTFTs, comparison
of measured and simulated result from (a) transfer characteristic, (b) output characteristics.
158
 The well-fitted simulation result with the measured result has been confirmed. The good
agreement between the fitted and experimental results indicates the accuracy of the proposed
model. The accurate and reliable result of the developed model can be further verified to build
fundamental inkjet printed circuits, as logic gates. Furthermore, circuits developed based on
simulation results can be efficiently used to estimate circuit performances.

2. Evaluation of fully inkjet-printed inverter

a. Layout and printing of Logic Inverter

An enhancement modes NMOS based inverter was designed with two different dimensions
of n-type OTFTs, and it fabricated by fully inkjet printing technology. The two OTFTs in
inverter configuration are called T1 (W/L = 1500µm/100μm) for load resistor and T2
(W/L = 5000µm/100 μm) for driver transistor, respectively.
The schematic diagram and fabrication result of the enhancement modes NMOS based logic
inverter is shown in Figure 18.

Figure 18. (a) Schematic diagram and (b) optical micrograph image of the fabricated inverter.

An enhancement-mode nMOS transistor with a gate typically connected to its drain (VDD)
can be used as an active pull-up resistor. So, load transistors can be operated either in a
saturation region or in the linear region, depending on the bias voltage applied to its gate
electrode. The saturation-enhanced load inverter, as depicted in Figures 18(a) and 18(b), has
benefited from a single supply voltage and a simple process than the depletion load inverter.
However, the enhancement-mode inverter has a drawback that VOH is limited to the VDD - VT.
In other words, the output voltage for VIN = VDD is not 0 V, because both of the transistors
(i.e., T1 and T2) are conducting and act as a voltage divider. The problems with the simple

159
process and all nMOS circuits are very similar to the inherent problems of CMOS circuit
technology. In other words, the developed enhancement type inverter can be quickly replaced
with the CMOS circuit. Since the presented benefit of the configuration, the enhancement mode
inverter was chosen for this work.
Based on measurements, the dimensions of the transistors can be empirically derived, as
depicted in the schematic diagrams. Typically, output voltage and voltage gain of the logic
inverter is determined by a ratio of the channel width (W) from the driver transistor (T2) and
the load transistor (T1). We have chosen W/L dimensions for the driver T2 to be 3.4 times
larger than the load T1. The choice of the transistor's dimension is purposed to minimize the
access resistance of T1. Moreover, the design on the restricted substrate area should be
considered for a complex designed circuit.

b. Supply voltage (VDD) dependence of inverter

The fully inkjet-printed n-MOS inverter with various supply voltage (VDD) is investigated to
verify its electrical performance. The range of applied power supply voltages was chosen from
5 V to 25 V at 5 V intervals with 0.1 Hz frequency.
V =5V
DD
5 5

0 0
V = 10 V
10 DD 10
Output voltage (V)
Input voltage (V)

0 0
V = 15 V
DD
15 15

0 0
V = 20 V
DD
20 20

0 0
V = 25 V
DD
25 25

0 0
0.0 1.1 2.2 3.3 4.4 5.5 6.6 7.7 8.8 9.9
Time (s)
Figure 19. Square wave input pulse and the inverter dynamic switching behaviour under five
different supply voltage (VDD) from 5 V to 25 V at 5V interval with 0.1 Hz frequency.

160
 Dynamic inverter switching behaviour is well captured in Figure 19 with VDD ranges from
5V to 25 V at 5V intervals (i.e., 5, 10, 15, 20, 25 V). Comparing the input and output waveforms
showed excellent transient characteristics even in the lowest VDD = 5 V. In all results in VIN
and VOUT, Peak to peak voltages (VPP) were close to the applied VDD. By decreasing the VDD,
switching delay has been observed from the output at all rising and falling edges. However, the
measured results in dynamic inverter switching behaviour have been demonstrated the
electrical performance of inkjet-printed n-MOS inverter with correct behaviour regardless of
the applied VDD.

c. Frequency dependence of inverter

In this section, we used various frequencies with a fixed VDD to verify the switching
frequency dependence of the fabricated inverter. The switching frequency in an inverter is the
rate at which the switching device is turned on and off. The switching frequency directly affects
the power dissipation in switching elements as the transistors. Therefore, the investigation of
the frequency dependence of the inverter is an important task to examine for further circuit
applications.
25 25

0 0
Time (285 ms/div)
25 25
Output Voltage (V)
Input voltage (V)

0 0
Time (400 ms/div)
25 25

0 0
Time (1s/div)
25 25

0 0
Time (2.5 s/div)
25 25

0 0
Time (10 s/div)

Figure 20. Square wave input pulse and the inverter dynamic switching behaviour under five
different switching frequencies range from 0.1 Hz to 3.5 Hz at a fixed VDD = 25V.

161
 As shown in Figure 20, the range of applied frequencies was chosen from 0.1 Hz to 3.5 Hz
at the fixed VDD equal to 25 V. These results indicate that frequency has a considerable impact
on the increase of frequency. The fabricated inverter showed well-defined inverter behaviour
and the rise time (tr) equal to 0.62 s under the switching frequency of 0.1 Hz with a constant
VDD at 25 V. However, the inverter showed a frequency limitation in switching frequency range
from 0.5 to 3.5 Hz. The increase in switching frequency led to a decrease in the VPP in response
to a drastic decrease in VOH. These results may be due to the poor electrical parameters of the
OTFTs that compose the inverter. As shown in Figure 20, the insufficient output of the inverter
at high frequencies (i.e., above 0.5 Hz) may be due to the low mobility characteristics of n-type
OTFT. Besides, the VTH shifting also can be the reason. However, we thought that the measured
results of the inverter were not only due to the electrical characteristics of the OTFTs. The
capacitance of the measurement system can have an impact on the output of the inverter, in
particular, as a limiting factor of the rise time tr. In the next section, we will discuss the
problems of the measurement systems used before and describing a developed measurement
system.

Development of electrical characterization

method

1. Problem on electrical characterization system

Electrical characterization of organic components such as logic gates, amplifier or sensors
is a critical point and is not as easy as for classical devices made of silicon material. Because
of low carrier mobility of such organic material, equivalent resistances of transistor, even in on
regime, are very high (R > 1M). Organic TFT fabricated with inkjet printing technology has
another disadvantage: a very low resolution in the channel length definition (L > 50µm).
In order to characterize printed logic gates, specific attention has been carried on. Because
the encapsulated layer has not yet been developed for our devices, electrical characterizations
will be made in the gloves box. This consideration will have an impact on the wiring length to
supply the logic gate and to acquire the output voltages. Moreover, the main objective of this
thesis work is to fabricate and to characterize digital circuits such as D-Flip Flop and
multiplexer with several inputs and outputs. Until now, OTFTs have been characterized using a
162
4-probes station into a gloves box. Considering the numerous input/output in digital circuits, a
new homemade probe station has been developed dedicated to printed circuits.
As we discussed in this chapter, the frequency limitation of organic electronic circuits is a
real drawback of printed technology. In the section dealing with inverter constituted of printed
OTFT and discrete resistance, the frequency limitation has been determined coming from the
load resistance and led to an extracted rise time of the output voltage tr = 171.7 ms.
In the previous section, inverters have been fabricated using printed OTFT as a load
transistor and a driver transistor. By using OTFT for both devices of the inverter, rise time has
been improved until tr = 130.3 ms for VDD = 25 V. By analysing the way to characterize the
inverter, we found that this high rise time could come from the capacitance of the electrical
measurement system.
The measurement system was made with a function generator with the peak to peak voltage
of 5 V following by an operational amplifier with a variable gain allowing the control of voltage
from 5 V (gain = 1) to 25 V (gain = 5). The input voltage was linked to a characterization box
with 16 electrodes. The contact between electrodes and glass (organic electronic circuit) was
ensured by a resilient device to avoid any damage on the silver pads. Output voltages of organic
electronic circuits were acquired with an oscilloscope though followers made of an operational
amplifier with very high input impedance (Ze > 1015 ).

Figure 21. Image of the new platform system installed in the glove box.

A new homemade platform has been developed. A specific electronic card has been designed
to generate 8 inputs signal from 5 to 25 volts and to measure 8 outputs on a touchscreen display.
The card is directly integrated into the gloves box and connected to our substrate using 16-
spring electrodes. This homemade platform can also be connected to an external oscilloscope.
163
Comparing to the old measurement system, the new platform can efficiently reduce the wiring
length. In other words, the new platform system expects to benefit from lower load
capacitance (CL). Image of the new measurement system, called platform, is depicted in
Figure 21.

2. Load capacitance (CL) effect on inverter characteristics

In order to confirm the effect of the developed new platform system, the electrical
characteristic of one inverter was measured by the old and the new platform and then compared
in Figure 22. Inverter dynamic measurement is carried out at a fixed VDD = 25 V with 0.1 Hz
switching frequency.
Load TFT (W/L 1500/100 m)
Driving TFT (W/L 5000/100 m) Vin
at VDD = 25 V Old measurement system
New platform
25 25

20 20

Output voltage (V)

Input voltage (V)

15 15

10 10

5 5

0 0
0 10 20 30 40

Time (s)

Figure 22. Square wave input pulse and the inverter dynamic switching behaviour of the old
measurement system and the developed new platform measurement system. Inverter dynamic
measurement is carried out at VDD = 25V with 0.1 Hz switching frequency.

This investigation is related to the load capacitance (CL) effect on the measurement system.
As mentioned in the previous section, an equivalent CL of the measurement system was
combined with OTFT equivalent capacitance. If CL has been improved in the new platform
system, the output voltage level will not change. However, the improved load capacitance will
induce a shorter time to charge and discharge the output CL. In other words, the load
capacitance CL is related to transition frequency, and it can be determined by the RC time
constant (τ = RC) where R is the on-resistance of the OTFT.
From the measured results of the inverter with two different CL (Figure 22), the rise time (tr)
was extracted to 290 ms for the old measurement system and 90 ms for the new platform at
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VDD = 25 V. With a simple calculation, we can estimate the total parasitic capacitance of the
new platform Cp = 34 pF. This value is 5 times lower than the value of the previously calculated
CP in the old measurement system (Cp of in the old measurement system = 171.7 pF). In
conclusion, the load capacitance effect on the electrical characteristic of inverter has been
confirmed and the verification of the new platform has simultaneously been validated.

III.Result and analysis of fully inkjet-printed NMOS

circuits

Fully inkjet-printed Logic gates (Inverter and

NANDs)

1. NMOS Inverter
To demonstrate the feasibility of using the inkjet-printed electronic for the organic circuit,
we have evaluated the logic nMOS inverter. Generally, the evaluation of logic inverter was
carried out in static and dynamic electrical characteristics. Understanding the differences
between the capabilities and limitations of both measurement and simulation are essential to
making that happen. Pre-simulated dynamic and static characteristics of the organic nMOS
inverter were compared with the results of the fabricated inverter to confirm that agreement, as
shown in Figures 23(a) and 23(b), respectively.
(b)
(a) VIN VOUT, Simulated VOUT, Measured 25
VOH = 21.61 V Simulated
25 25
VOH = 21.1 V Measured
20
Output Voltage (V)
Input Voltage (V)

20 20
15
VOUT (V)

15 15
10
10 10

5 5
5 VOL = 2.26 V

VOL = 1.6 V
0 0
0 5 10 15 20 25
10 20 30 40
Time (s) VIN (V)

Figure 23. Dynamic and static characteristics of the inkjet-printed n-MOS logic inverter with an
agreement between simulated and measured result at VDD = 25 V, and frequency = 0.1 Hz.
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 As shown in Figure 23(a), dynamic behaviours of the inverter were evaluated and compared
with the measured and simulated results. A pulse input voltage from 0 to 25 V at a frequency
of 0.1 Hz has been supplied to VIN with an output load capacitance of 34 pF. The output rise
time (tr) and fall time (tf) have been extracted using transient response, as summarized in
Table 7.
Table 7. Comparison of the evaluated parameters between the simulated and measured result for
the inkjet-printed n-MOS logic inverter.

VOH VOL VPP Tr Tf NMH NML

(V) (V) (V) (s) (s) (V) (V)

Simulated 19.1 2.6 16.5 0.15 0.03 10.92 1.19

Inverter
Measured 22.5 2.2 20.3 0.02 0.01 12.91 0.91
(Measured – Simulated) 3.4 -0.4 3.8 -0.13 -0.02 1.99 -0.28

As can be verified in the measured result, the extracted VOH and VOL showed a minimal
difference of 2 + 0.2-0.5V, from supplied VDD. The maximum VOUT (= VOH) is 22.5 V and the
minimum VOUT (= VOL) is 2.2 V, respectively. These voltage differences come from two
transistors (Tload and Tdriver) including in our inverter designs that act as a voltage divider.
Although the selected inverter design is the enhancement mode, where VOL cannot go to 0 V,
the measured result shows very low VOL close to 0 V with a high VPP value. In other words,
the pull-up characteristics of the inverter from the above results have approached sufficient
development for the electrical performance beyond the limitation from the employed design.
To evaluate the noise margin and gain of the fabricated inverter, VTC performance was
measured at VDD = 25 V, as shown in Figure 23(b). High noise margin (NMH) and low noise-
margin (NML) is related to the reliable and robust operation of the logic circuits. And it can be
obtained from different transition levels of output voltage 200,201.
The NMH has been evaluated as 10.92 V in the simulated result and 12.91 V in the measured
result for a supply voltage of 25 V, respectively. Both of the high noise margins values are not
far from the ideal noise margin value of VDD/2 = 12.5 V. Moreover, 2 V higher NMH was
observed in the measured result. The NML has been evaluated as 1.19 V in the simulated result
and 0.91 V in the measured result for a supply voltage of 25 V, respectively. Siegfried et al. 202
mentioned that the minimum required value of the noise margin for circuitry application is 10 %

166
of VDD/2. Therefore, we can verify that the NML also can meet an ideal value as well as the
result of the NMH. In the case of NML, the measured result has 0.28 V lower values than the
simulated result. The VTC of the inverter shows that the input voltage and output voltage were
in inverse proportion. Namely, when the low input voltage applied to the gate of Tdriver, the
output voltage was high, because the Tdriver would be turned off. In the other case, since Tdriver
turns on, the output voltage is low because it is connected to the ground (GND). The gain
(derivative of VTC) was defined by the dVOUT/dVIN at the point of inverting voltage and
evaluated of 4.7 at a supply voltage of 7 V.
The above the compared results have shown three notable features as follow: 1) the obtained
results show correct input-output characteristics that follow the typical operation of the inverter,
2) the value of peak to peak voltage (VP.P) in the measured result was higher than the simulated
result, 3) moreover, the results have been showed the differences in rise time (tr) and fall-
time (tf). The inverter could operate in rail-to-rail at 25 V with only 5 V of voltage drop. The
simulation result is then validated against the measured result in good agreement, each other.
Although the VOUT and transition time (i.e., tr and tf) of the measured results showed better
performances than simulated results, the results show the reliability of the approach using pre-
simulation. SPICE simulations have successfully implemented simple printed circuits based on
n-type organic materials. This approach can efficiently reduce the failures by adjusting process
parameters before fabrication. Besides, most of the inverters were carried out only using the n-
type OSCs, C60. Furthermore, the practical issues can be easily resolved in a CMOS circuit by
applying a p-type OSC to be more certain diode roles. In the sense that our fabricated circuits
only performed by the n-type OSCs, and these electronics having a correct electrical behaviour
with good agreement between experimental and simulated results, the investigated logic
inverter gates were successfully verified.

2. NMOS NAND
The next step towards more complex design circuitry beyond inverter, logic NAND was
constructed using three OTFTs for one load and two drivers. Logic NANDs are more frequently
used than other types of logic gates.
Most of the literature has been reported on printed logic gates, and they are focusing on logic
inverter due to the simplicity and less failure. Only a few reports were showing the complex
designed circuits using printed electronics based on organic material. Therefore, the
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implementation of more complex designed circuitries has been playing a role as an essential
step to demonstrate the feasibility and possibility of these technologies.

(a) 25
Vin1
25
20
(b) 25
VOH = 23.39 V
20
15 15 Simulated
10
10
5 5 VOH = 21.04 V Measured
0 0 20
Vin2
Input Voltage (V)

Output Voltage (V)

25 25
20 20
15 15
15

VOUT (V)
10 10
5 5
0 0
(Simulated) 25
25
20 20 10
15 15
10 10
5 5
0 0 VOL = 3.6 V
5
(Measured)
25 25
20 20
15 15 VOL = 3.16 V
10 10
5 5 0
0 0 0 5 10 15 20 25
10 20 30 40
Time (s) VIN (V)

Figure 24. Dynamic and static characteristics of the inkjet-printed n-MOS logic NAND with an
agreement between simulated and measured result at VDD = 25 V, and frequency = 0.1 Hz.

As shown in Figure 24, the results of the 2-bit logic nMOS NAND are investigated in the
dynamic and static characteristics as with the inverter. A pulse input voltage from 0 to 25 V at
a frequency of 0.1 Hz has been supplied to VIN with an output load capacitance of 34 pF. The
static and dynamic characteristics of the logic gates depend on the data input patterns.
Therefore, the gain and noise margin analysis of the fabricated logic NAND is more
complicated than the inverter. The pre-simulated results were compared with the measured
results of the fabricated NAND to confirm that agreement. In all n-type logic NAND, the
architecture is consists of T1,load to perform the pull-down, T2,driver and T3,driver for two inputs to
perform the pulls-up. The same dimensions were used in the inverter design, as described in
the inset of Figure 24(b), respectively.
As can be shown in the dynamic characteristics (Figure 24(a)), similar to the inverter, the
logic NAND responds as well with the correct behaviour.
Table 8. Comparison of the evaluated parameters between the simulated and measured result for
the inkjet-printed n-MOS logic NAND.

VOH VOL VPP

Tr (s) Tf (s) NMH (V) NML (V)
(V) (V) (V)
Simulated 19.3 4.5 14.9 1.3 0.03 11.48 3.18
Inverter Measured 23.4 6.9 16.6 0.5 0.2 12.91 0.06
(Measured – Simulated) 4.1 2.4 1.7 -0.8 0.17 1.43 3.12
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 The comparison between the measured results and the simulated results was used not only
for the inverter but also for verifying the dynamic and static characteristics of the logical
NAND, as shown in Table 8. The VOH and VOL are evaluated as 23.4 V and 6.9 V, respectively.
Also, the tr and tf have been extracted as 0.5 s and 0.2 s, respectively. In detailed verification,
VOH has less voltage drop (= 1.6 V) than the evaluated result of the inverter. Moreover, the
optimized logic NAND showed good transition time less than 0.5 s without any signal
degradation. However, a higher VOL than the inverter was obtained from the measurement
results of the logic NAND. The measured results in dynamic characteristics were verified as a
good agreement with simulated results through the evaluated parameters and correct operating
behaviours, which was predicted with Aim-Spice simulation.
The NMH has been evaluated as 11.48 V in the simulated result and 12.91 V in the measured
result for a supply voltage of 25 V, respectively. Both of the NMH values are not far from the
deal noise margin value of VDD/2 = 12.5 V, and 1.43 V higher value was observed in the
measured result. The NML has been evaluated as 3.18 V in the simulated result and 0.06 V in
the measured result for a supply voltage of 25 V, respectively. The nMOS logic NAND shows
a gain of ~ 3 at a supply voltage of 11 V.
Several notable features can be discussed as follows: 1) the reason for the high VOL can be
assumed to be due to the n-type OTFTs that constituting the fabricated nMOS logic gates. The
n-type OTFTs have inherently high resistance. Furthermore, the increase in the number of
additional OTFTs connected in series for the implementation of the logic has affected the
switching speed. 2) Although the number of OTFTs has influenced the electrical performance
of the logic gate, the extracted electrical parameters showed sufficient characteristics to realize
many kinds of low-end applications for sensing and operation. 3) The systematic approach is
well validated for good agreement with each other. Therefore, using this approach can propose
a more useful and efficient methodology to implement more complicated circuits using printing
technology, with fewer failures in experiments.
As a result, successful implementation of a NAND gate is a key result, given that by
combining inverters and NAND gates, a wide variety of logic circuits can be constructed
through inkjet printing technology

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 Fully inkjet-printed Digital circuit application

1. 2 to 1 Multiplexer based on n-MOS logic gates

Figure 25 shows the block diagram, truth table, and circuit diagram of 2 to 1 multiplexer,
which is employed as a combinational circuit in this thesis. Besides, the used design of
multiplexer and its configurations of each signal are depicted, as shown in Figure 25(d).

Figure 25. 2 to 1 Multiplexer for the combinational circuit using an inverter and 3 NANDs of (a) block
diagram, (b) truth table, (c) circuit diagram, and (d) circuit design for inkjet printing.

The Multiplexer, shortened to “MUX,” is a circuit that designed to switch one of several
input lines through to a single common output line by the application of a control signal. In
other words, this circuit can select each input line, and is also called “data selectors.” Therefore,
they need a select signal, which is indicated as “S” in Figure 25(a). For instance, the function
of the in-house manufactured manual switch of the multiplexer is used to select individual data
or signal lines simply by turning its input lines of ON/OFF. So, the select signal can make a
decision for the on/off switching in this digital circuit, automatically. If the multiplexer requires

170
N input signals, log2N bit of select signals are need. As a result, one selects signal was required
for two inputs in our designed multiplexer, and then, the circuit can obtain one output.
From the truth table above, as shown in Figure 25(b), when the select signal “S” is “0
(= LOW),” input D1 passes its data to the output, while input D0 is blocked. On the contrary,
when the select signal “S” is “1 (= HIGH),” input D0 passes data to the output F, while input D1
is blocked. Correct behaviours, or certain behaviours, mean that the circuit operating state in
which the output characteristics of all the results appropriately satisfy the truth table according
to the selection signal. The confirmation of the correct behaviour can confirm by following
Boolean expression:

𝐹 (𝑂𝑢𝑡𝑝𝑢𝑡) = 𝑆`𝐷0 `𝐷1 + 𝑆`𝐷0 𝐷1 + 𝑆𝐷0 𝐷1 ` + 𝑆𝐷0 𝐷1 …................. Eq. 4.5

And it can be simplified as:

F (Output) = 𝑆`𝐷1 + 𝑆𝐷0 ….................. Eq. 4.6

Understanding and implementation of multiplexer using printing technology, as a goal of

this thesis, is mostly interesting application, and it can be emphasized for the low-cost,
environmentally friendly digital application based on the combinational circuit, such as a
communication electronics, local area network (LAN) and Ethernet applications.
A printed 2 to 1 multiplexer as a combinational circuit consisting of 11 all n-type OTFTs is
implemented to demonstrate a higher level of transistor integration using inkjet printing
technology. In typical designing for multiplexer, the implementation of the Boolean expression
above using individual logic gates would require the use of one inverter, two AND, and one
OR logic gates. However, our proposed design for the multiplexer composed of one inverter
and three NAND types. The uses of these logic gates are for process simplification, and high
yield for more complex circuits based on the results confirmed above.

171
 20
Vselect 10
0

Output Voltage (V)

20
Vin 1 10
0

20
Vin 2 10
0

20
Vout
10
(Simulated) 0

20
Vout
10
(Measured) 0
0 10 20 30 40 50

Time (10s/diV)
Figure 26. Dynamic behaviour of 2 to 1 multiplexer as a combinational circuit. The simulated and
measured result of 2 to 1 multiplexer is implemented by 11 all n-type OTFTs (one inverter and 3 NANDs)
using fully inkjet printing technology except OSC deposition. A pulse input voltage from 0 to 25 V at a
frequency of 0.1 Hz has been supplied to input D0 and D1 and select signal Vselect from 0 to 25 V has
been supplied with an output load capacitance of 34 pF.

As shown in Figure 26, the simulated result and measured result in the dynamic behaviour
of the proposed 2 to 1 multiplexer are successfully operated. The output signal, according to
the select signal (Vselect), has been showed data selection behaviour for input D0 (VIN1) and D1
(VIN2). Besides, the operating behaviours are corresponding to its truth table as following
Boolean expression. The numbers of OTFTs and continuous connections have been used for
the circuit configuration Despite the burden of the requirements, the differences between the
maximum output voltages of the simulation and the measured result were confirmed to be
within 1-3 V. This means that the proposed SPICE simulation can indirectly indicate its
reliability regardless of the complexity of any circuits. In other words, the good agreements
between the simulated and measured results can be used for a systematic development for
advanced organic-based applications using inkjet printing technology. However, it was also
confirmed that the transition response, as tr and tr, of the output signal were delayed according
to the complexity of the circuit (tr and tf ≈ 0.7 s). It is assumed that the decreasing transition
response comes from the high resistance transition caused by continuous connections with the
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capacitance of the device elements (i.e., OTFTs). The Tload of logic gates consisting of the
fabricated electronic circuit is not a diode, and they are connected to OTFTs with a channel
dimension (W/L = 1550 μm/110 μm). Therefore, high resistivity and capacity of OTFTs can
affect to the performance. These results can cause noise to be generated depending on the state
of the input signals.
Moreover, low mobility of n-type OTFTs not enough to make entirely pull up/pull down
with the high speed of transition response. However, in the sense that our fabricated circuits
only performed by n-type OSCs C60, the practical issues can be quickly resolved in a CMOS
circuit. Most of the studies in advance, it is an interesting result that the implemented circuit
showed a VPP equal to 11 V without signal degradation in output characteristics, even in a
circuit consisting of only one n-type OSC using inkjet printing technology fully. In the next
section, we will implement a sequential circuit composed of more OTFTs to verify this result,
more precisely.

2. D-latch based on n-MOS logic gates

The Data latch, shortened to “D-latch,” is included in a sequential circuit as a memorial
device to store data in 2-bit. D-latch has been created to resolve the big issue of the SR latch,
which is a primary latch among all the flip-flops. When both of the two inputs come in SR latch
as “1 (= HIGH),” abnormal output can occur for outputs Q and Q that need maintaining a
"complementary relationship." That is, the SR latch does not apply to real electronics.
Otherwise, the difference between the SR latch and D latch is that an inverter is used in the
circuit configuration. By connecting the inputs of both logic gates of the clock (CLK) signal
using an inverter, the actual input terminal is composed of one. The inverter always applies the
opposite values to the two inputs of the circuit to prevent abnormal output from being input.
D-latches are typically used as primary 1-bit memory devices and I/O ports of an integrated
circuit and are available as discrete devices. Besides, sometimes used in synchronous two-
phase systems to reduce the transistor count. The D-latch has advantages such as less power
consumption, small die-size based design, and high-speed circuit. However, the significant
advantage of the latches is “Time-Borrowing.” In which if an operation is not completed within
time, the required time for executing the operation is borrowed from the other operational time.
On the other hand, the drawback of D-latch is that it is difficult to predict and analyse circuit
performance because it is a level-sensitive device. Despite these drawbacks of D-latches, it is
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an interesting implementation subject even considering the importance of memorial behaviour
and its usefulness for advanced applications.
The CLK signal entirely governs the operating behaviour of D-latch. First of all, when the
“CLK” signal equal to “1 (= HIGH)” and input signal “D” equal to “1,” and bottom NAND
receives a “0 (= LOW)” signal. That is called “set state.” On the contrary, when the “CLK”
signal equal to “0” and input signal “D” equal to “0,” but bottom NAND receives a “1 (= LOW)”
signal. That is a state called “reset state.” In other words, when the input D = 0 while the CLK
= 1, the output Q also keeps the state 0 at that moment. In the case of when D = 1, Q also keeps
the stat 1. It means that the output of the D-latch is always having the same set state when CLK
is high. However, when CLK = 0, the state of D-latch does not change regardless of the input
signal. Relationship between input and output signal can be presented by Characteristic
Equation 4.7 as follows:

Q(n + 1) = 𝐸𝑛` ∙ 𝑄 + 𝐸𝑛 ∙ 𝐷 ….................. Eq. 4.7

Where Q (n+1) is the next state of an output signal, En is meaning that enabling and it is
CLK signal, and D is an input signal.

Figure 27. D-latch for the sequential circuit using an inverter and 4 NANDs of (a) block diagram, (b)
truth table, (c) circuit diagram, (d) circuit design for inkjet printing, and (e) optical microscopic view of
the fabricated D-latch using fully printing technology except for OSCs.

174
 Figure 27 shows the block diagram, truth table, and circuit diagram of D-latch, which is
employed as a sequential circuit in this thesis. Besides, the used design of D-latch and its
configurations of each signal are depicted, as shown in Figure 27(d).
To further demonstrate the process capability, we have fabricated a practical D-latch. As an
optical microscopic view, the D-latch is fabricated on a 1 inch of a glass substrate using inkjet
printing technology fully. Fourteen (14) OTFTs were used for logic gates, as an inverter and 4
NANDs, in the circuit configuration. Figure 27(e) shows the optical microscopic view of the
fabricated D-latch.
20 20 D (VIN)
10 10
0 0

20 20 CLK (VCLK)
10 10
0 0

Output voltage (V)

Input voltage (V)

20 20 Q (simulated)
10 10
0 0

20 20 Q (measured)
10 10
0 0

Q` (simulated)
20 20
10 10
0 0

20 20 Q` (measured)
10 10
0 0

Time (10s/diV)

Figure 28. Comparison of the D-latch performances between the simulated and measured in
dynamic response. A pulse input voltage from 0 to 25 V at a frequency of 0.1 Hz (Data, D) and CLK
frequency of 0.05 Hz has been supplied with an output load capacitance of 34 pF.

The timing chart in dynamic response shows that the fabricated circuit operates appropriately,
as shown in Figure 28. As demonstrated by the further demonstrations, as for the logic gates
and 2: 1 multiplexer, the dynamic responses of a fabricated D-latch were confirmed at a
frequency of 0.1 Hz and a supply voltage of 25 V. Output of the D-latch read the state of the
input when the state of the CLK is high and keep the output state at the pulling down moment
of the CLK. After the CLK is pulling down, the output state is starting to memorize output
signal. And then, the output state of Q is held until the CLK is pulling up. The operating
behaviours exactly have been matched the operating behaviours of the general D-latch
described above.

175
 Furthermore, this result was confirmed not only from the simulation but also from the
measurement result. Despite increasing the number of OTFTs, the D-latch operates with VPP
of ≈ 14 V as well as 2 to 1 multiplexer, where the further demonstration with 11 OTFTs.
However, significant differences were observed between simulated and measured results in the
transition responses. The tr for the output signals Q and Q` in simulated results are evaluated
as 0.17 s and 0.11 s, respectively. However, the evaluated tr of Q and Q` in measured results
are 0.57 s and 0.62 s, respectively. The simulated result shows an ideal characteristic of
transition time. However, the measurement results can confirm that the factors it has, which
affect the pull-up / down of the transition response of the circuit performance. Moreover, the
noise was confirmed from the output signal in the section where the CLK state was changed.
From the above demonstrations, several factors relating to the transition response and noise
can be estimated:
At first, the factor that causes a noise can come from the circuit itself, such as an imperfect
design or layout, faulty logic gates, or loose connections. In particular, parasitic capacitances
that come from OTFTs consisting of the fabricated integrated circuit will increase the turn-off
delay of one section. The increase of turn off delay affects the DC characteristics (i.e., output
voltage ripple) 203,204. For the second, switching loss of the D-latch can be caused by a charging
of total capacitance (Ctotal), which is come from the increasing number of OTFTs or number of
connections. The increase of these factors can make high dI/dt and dV/dt of MOSFETs and it
causes a considerable amount of overshoot in device voltage.

Figure 29. (a) Switching status, (b) voltage V0 across switching status, and (c) output voltage ripple
with extra ripple due to the charging of capacitance coming from the circuit itself. Adopted from ref. 203.

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 Moreover, current during switching in the presence of logic gates, parasitic load
capacitance (Cl) also cause uncontrollable switching loss and noise, as the result of D-latch 205.
As shown in Figure 29, when the switch is opened at time t3 (Figure 29(a)), the time taken by
203
the voltage in (t4 - t3) to increase to voltage V0 (Figure 29(b))is determined by the Ctotal .
Moreover, high VOL in dynamic characteristics of the D-latch can be related to high ON
resistance coming from the logic gates, as depicted in Figure 29(c).
In addition to understanding the transition response and noise of the D-latch, the output Q is
not clearly defined as memorial behaviours. The CLK signal entirely governs the memorial
behaviour of D-latch. For that reason, using an increase of the CLK frequency with a duty cycle
of 50 % to the same device and investigate a variation in output characteristics, as shown in
Figure 30(a). Besides, when changed the CLK frequency, the operating speed of the circuits
can be evaluated simultaneously.
The D-latch verified at a higher CLK frequency of 200 mHz (4 times higher than above and
the input frequency is the same as above) showed a voltage loss of 2 V in both of the output
characteristics (e.g., Q and Q`). However, they still keep the correct operating behaviour of D-
latch. The advantage of this approach is that the memorial behaviour of the D-latch can be more
clearly investigated than the above results, as shown as grey circles in Figure 30(b).

Figure 30. Dynamic response and memorial behaviours of the D-latch. (a) dynamic response of the
D-latch with a pulse input voltage from 0 to 25 V at a frequency of 0.1 Hz and CLK frequency of 0.2 Hz
has been supplied with an output load capacitance of 34 pF, (b) dynamic behaviours (gray circles inset
of the figure).

177
 However, when the state of CLK was changed to the state of 0, a voltage drop (∆VP) of ≈
2 V simultaneously occurred in output Q, but after output Q was maintained a stable voltage
with the memorial behaviours, as adopted in the literature 206. The phenomenon is reflected in
an effect called “kickback effect.” The effect of kickback is presumed to be due to capacitive
206
coupling caused by the parasitic capacitance . And this parasitic capacitance can generate
between the gate and drain. The relatively large parasitic capacitance obtained can be attributed
to the low resolution of inkjet printing technology and the wide channel length (115 μm) and
channel overlap size (30 μm) of the printed OTFT. However, the kickback has been only
generated in the output Q (not output Q`). The result indirectly reflects that one or more OTFTs
compositing a NAND relating to the node of output Q has a higher parasitic capacitance than
the others. In the case of our process for the D-latch, the results are also attributed to the
increased number of OTFTs and connections, and an occurrence of defects during the process.

IV. Conclusion
In this chapter, we focused on the investigation of circuit implementation using fully inkjet
printed n-type OTFTs. All presented circuit applications from the logic inverter to the complex
design of digital circuits are fabricated using only n-type OSC based transistors for the
composition.
At first, we were focused on the development of the inverter. The suitable discrete load
resistance of 500 MΩ was verified with the inkjet printed OTFT optimized in chapter 3.
Secondly, since the load resistance of the inverter has been defined, the entire inverter
configuration (i.e., load transistor and driver transistor) can be fabricated with inkjet printed
OTFTs. The first task in implementing a full inkjet printing inverter was to build a model. The
model was used to understand in systematic analysis to estimate electrical performance before
fabrication. Based on the well-fitted model and simulation, fully inkjet printed inverter was
fabricated, and supply voltage VDD dependence, frequency dependence has been evaluated.
The frequency limitation of the first inverter was observed. A new measurement platform has
been made, taking into account the effect of device capacitance. The differences in the
mechanism of the platform system were also briefly discussed since it was self-production in
our lab. The load capacitance tended to make a difference to evaluate the actual electrical
characteristic of circuit application.

178
 The electrical characteristics of the fully inkjet printed inverter have been improved. Based
on the developed inverter, the NAND logic gate was also simultaneously implemented. More
complex digital circuits were implemented using validated fully inkjet-printed logic gates (i.e.,
inverter and NAND). Both combinational and sequential digital circuits such as 2 to 1 MUX
and D-Latch were successfully developed based on developed inverter and NAND. Although
more OTFTs were used to compose the configuration of the digital circuit, the fabricated digital
circuit applications have a correct behaviour with small voltage loss and rise time up to 0.8 s
at VDD = 25 V with 0.1 Hz frequency.

179
180
 General Conclusion
In recent decades, considerable research efforts have been implemented in order to respond
to new societal challenges (i.e., sustainable energy, efficient use of raw materials, health,
mobility, etc.) as well as to new consumption patterns (i.e., connected objects, large or even
flexible screens, etc.). Thus, we should see the light of day shortly: Ⅰ) screens and flexible
photovoltaic panels, transparent and covering large areas, Ⅱ) flexible connected sensors
recording physiological constants as close as possible to patients. Electronic researchers (i.e.,
multinationals and research laboratories) strive to offer new technologies to meet these new
needs. One of them, developed over a decade and commonly known as "printed electronics,"
is a serious candidate who can respond to the current issues mentioned above.
Printed electronics implement materials in solution (inks: polymeric, semiconductor, based
on nano-objects, etc.) using equipment already proven in graphic art. However, the know-how
acquired in the field of printing must be transferred to "the field of electronics." This problem,
constituting a major issue, led to this study. In fact, the design methodology for printed
electronic devices is different from that used in “conventional electronics.” Concretely, a
printed electronic device is produced additively (each constituent layer is deposited one after
the other and requires no etching step) unlike a device produced by photolithography (a process
commonly used in microelectronics). In addition, printed electronics can address other
challenges such as: producing electronics at low temperatures on non-conventional substrates
compatible with large surfaces (plastic, paper, biodegradable, etc.). The first fully printed
transistors have been produced in the laboratory, but to date, no product has been marketed
using this technology. Indeed, many obstacles remain to be lifted, such as the reliability and
the reproducibility of the devices.
In previous work carried out at IETR, printed transistors could thus be produced showing
the feasibility of using inkjet printing for the manufacture of integrated electronic devices. The
objectives of this thesis were to:

- Better understand the structure of a printed organic transistor to optimize the

manufacturing process.
- Improve the electrical performances of printed organic transistors to integrate them into
electronic circuits

181
 - Study the electrical stability of these transistors to improve the reliability of the circuits
- Study the electrical characteristics of inverter using this new inkjet printed OFETs with
a well-fitted model.
- Build a digital circuit to demonstrate an applicability and perspective of the inkjet
printing technology.

The first part of this thesis work consisted in improving the organic transistor structure by
the inkjet printing process. Until now, only the gate, drain and source electrodes have been
manufactured by inkjet printing. In microelectronics, gate insulators are inorganic type
materials and do not meet specifications allowing their printing. A polymer type insulator was
therefore studied. SU-8 is a photosensitive resin which, due to these physical properties, is
compatible with an inkjet printing process. This organic insulator was, first of all, studied from
an electrical point of view by depositing it in solution by spin-coating, a technique mastered in
the field of microelectronics. These electrical properties have proved to be very advantageous
for its use as an insulator, such as a very low leakage current (I ≤ 10-9 A/cm2), a high breakdown
electric field (4.5 MV/cm) and a dielectric constant  = 2.75.
The next step of this work was to study the printing process of this polymer. Indeed, the
printing of a material in solution requires precise control of the rheological parameters of the
inks as well as the study of the behaviour of these inks on the surface on which they are
deposited. The creation of uniform films, the control of the thickness of the insulating layer
and the study of the morphology of the films constituted an important technological work
during this thesis.
The printing process for a transistor structure requires precise control of the printed layer as
a function of the previous layer. The printing process for the drain and source electrodes with
accurate patterning such as desired dimensions requires surface modifications of the printed
SU-8 to obtain a continuous film. After various attempts to print these electrodes by modifying
the printing parameters as in the case of the previous study, the study of the impact of UV
Ozone exposure of the SU-8 film was performed. Then, it was possible to modify the
hydrophobicity of the SU-8 layer and to produce continuous films based on silver ink for
patterning the drain/source electrodes.
The last step in the fabrication of a printed organic transistor focused on the study of the
organic semiconductor (fullerene C60) deposited by thermal evaporation during the last step of
the fabrication process. The impact of the access resistances between the silver electrodes
182
(drain/source) and the semiconductor on the injection and the charges transport through the
fullerene required a work of optimization of this layer in terms of crystallinity and thickness.
This study on the optimization of the electrical performance of the printed organic transistor
led to obtain results at state of the art. These transistors were then manufactured in larger series
for studies of reproducibility, uniformity of performances and electrical stability. Indeed, these
elements constitute the basis for the design of electronic circuits from printed organic
transistors.
This thesis work then focused on the production of organic digital circuits in inkjet printing
technology. An electrical model was developed from the electrical characteristics using the
Aim-Extract software. Inverter, NAND logic gates, multiplexer and D flip-flop digital circuits
were simulated with this model using Aim-Spice software. Finally, from a dimensioning phase
of these circuits, they were manufactured with inkjet printing technology optimized during this
study.
During an intensive investigation of inverters, a transition response (i.e., rise time) issue was
confirmed due to the capacitance effect of the ‘previous measurement system.’ To overcome
this issue, a new platform system was carried out in our laboratory. Finally, the verification of
the new platform has simultaneously been validated by tuning the capacitance issue.
By extensive study for improving electrical characteristics of the inverter using OFETs,
dynamic inverter switching corresponds to expected behaviour with VDD ranges from 5V to
25 V. Interestingly, comparing the input and output waveforms, measurements showed
transient characteristics even in the lowest VDD = 5 V. A NAND logic gate, multiplexer and D
flip-flop digital circuits were fabricated using fully additive process technology and electrical
performances of these circuits have been validated with correct behaviour.
In conclusion, the work carried out during this thesis has made it possible to demonstrate the
feasibility of an organic digital circuit using inkjet printing technology. The results obtained
also demonstrate the skills acquired by the IETR on technological research and development,
starting from the material and leading to the design of a complete electronic circuit.
In this work, we described the development of organic electronic with fully additive
technological process. The major perspective of this work will be to transfer this process onto
a fully inkjet printing process. For now, OSC is still evaporated in the last process step. Our
goal will be to print an OSC in solution. In addition, CMOS circuits will be implemented using

183
a combination of p-type and n-type OSC leading to a competitive electrical performance of
organic electronic circuits.

184
185
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 Titre : Développement d’un procédé de fabrication par impression jet d’encre pour la fabrication
de circuit électronique à base de matériaux organiques
Mots clés : Impression jet d’encre, Transistors couches minces organiques, Circuits numériques
organiques
Résumé : L’objectif de cette thèse était de
démontrer les potentialités du procédé
technologique d’impression jet d’encre pour la
fabrication de circuits numériques à base de
matériaux organi\ques. Une première étape sur le
développement d’une structure de transistor
couches minces organiques (OTFTs) fabriquée
par impression jet d’encre a permis
d’appréhender les mécanismes d’intéraction
entre les différents matériaux déposés en
solution. A partir de cette étude, la structure a pu
être optimisée afin d’obtenir des performances
électriques uniformes et reproductibles. Les
transistors en couches minces organiques ont
ensuite été modélisés électriquement à l’aide
d’un modèle simple (Aim-Extract, Aim-Spice).
La comparaison entre caractérisations et
simulations électriques ont démontré la
possibilité de prédire le comportement électrique
de la structure OTFT imprimée.
Title : Development of Inkjet Printing Technology for Fully Solution Process Dedicated to Organic
Electronic Circuits
Keywords : Inkjet printing technology, Organic Thin Film Transistors, Organic digital electronic
circuits
Abstract: The main objective of this study
was to demonstrate the capability of inkjet
printing technology to fabricate organic based
digital circuits. At first, development of an
Organic Thin Film Transistor structure (OTFTs)
fabricated with inkjet printing technology has
highlighted interaction mechanisms between
materials deposited with a fully solution process.
From this study, the structure has been optimized
to obtain uniform and reproducible electrical
performance. The organic Thin Film Transistors
were then electrically modeled using a simple
model (Aim-Extract, Aim-Spice). The
comparison between electrical characterizations
and simulations has demonstrated the possibility
to predict electrical behaviour of printed OTFT.
A partir de ce modèle, des portes logiques
élémentaires ont été simulées puis fabriquées par
la technologie d’impression jet d’encre. Les
limitations en termes de temps de réponse des
circuits et de tensions d’alimentation ont ainsi pu
être déterminés. Finalement, des circuits
électroniques combinatoires et séquentiels plus
complexes, tel que des multiplexeurs et des
bascules de type D, ont été fabriqués et
caractérisés. La démarche employée au cours de
cette étude, à savoir, l’optimisation de la
structure OTFT, la modélisation électrique et la
fabrication d’un circuit électronique complet a
démontré les potentialités de l’impression jet
d’encre pour la réalisation d’électronique bas-
coût, grande surface, entièrement additive et
potentiellement flexible.
From this model, elementary logic gates were
simulated and then fabricated by inkjet printing
technology. Time response and supply voltage
of such circuit has been determined. Finally,
more complex combinational and sequential
electronic circuits, such as multiplexers and D-
latch, were fabricated and characterized. The
Experimental protocol used in this study dealing
with: i) OTFT electrical optimization, ii)
electrical modeling and iii) electronic circuit
fabrication has demonstrated the ability of inkjet
printing to reach low-cost, large area, fully
additive and potentially flexible electronics.