CD-610 Service Manual

SERVICE
MANUAL
CD- 610
m o c . m - r e t n i . w w w
A E R O K N I E D A M
1 C D
PLAYER
ELECTRICAL ADJUSTMENT PROCEDURE (FRONT PART)
1
MB95F108AHW
8-bit Proprietary Microcontrollers
Electrical Adjustment Procedure
Specifications
Electrical Parts List
Top and Bottom View of P.C.Board
Wiring Diagram
Block Diagram
Schematic Diagram
Exploded View of Cabinet & Chassis / Mechanical Parts list
1~42
43
44~45
46~49
50~51
52~53
54~59
60~61

CONTENTS
GGDESCRIPTION
GGFEATURE
The MB95100AH series is general-purpose, single-chip microcontrollers.
In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
64-pin plastic LQFP (FPT-64P-M03)
FMC-8FX CPU core
Instruction set optimized for controllers
GGGGGG Multiplication and division instructions
GGGGGG 16-bit arithmetic operations
GGGGGG Bit test branch instruction
GGGGGG Bit manipulation instructions etc.
Clock
GGGGGG Main clock
GGGGGG Main PLL clock
GGGGGG Subclock (for dual clock product)
GGGGGG Sub PLL clock (for dual clock product)
Timer
GGGGGG 8/16-bit compound timer 2 channels
GGGGGG 16-bit reload timer
GGGGGG 8/16-bit PPG x2 channels
GGGGGG 16-bit PPG x2 channels
GGGGGG Timebase timer
GGGGGG Watch prescaler (for dual clock product)
LIN-UART
GGGGGG Full duplex double buffer
GGGGGG Clock asynchronous or clock synchronous serial transfer capable
UART/SIO
GGGGGG Clock asynchronous or clock synchronous serial transfer capable
IC*
GGGGGG Built-in wake-up function
External interrupt
GGGGGG Interrupt by edge detection (rising, falling, or both edges can be selected)
GGGGGG Can be used to recover from low-power consumption (standby) modes.
8/10-bit A/D converter
GGGGGG 8-bit or 10-bit resolution can be selected
Low-power consumption (standby) mode
GGGGGG Stop mode
GGGGGG Sleep mode
GGGGGG Watch mode (for dual clock product)
GGGGGG Timebase timer mode
I/O port: Max 54
GGGGGG General-purpose I/O ports (Nch open drain) : 6 ports
GGGGGG General-purpose I/O ports (CMOS) : 48 ports
TEST
2 3
GGPIN ASSIGNMENT GPIN DESCRIPTION
(Continued)
Pin no.
Pin name
Circuit
type
Description
FPT-64P-M03
FPT-64P-M09
1 AVcc - A/D power supply pin
2 AVR - A/D reference input pin
3 PE3/INT13
P
General-purpose I/O port.
The pins are shared with the external interrupt input.
4 PE2/INT12
5 PE1/INT11
6 PE0/INT10
7 P83
O General-purpose I/O port
8 P82
9 P81
10 P80
11 P71/TI0
H
The pin is shared with 16-bit reload timer ch0 output.
12 P70/TO0
The pin is shared with 16-bit reload timer ch0 input.
13 MOD B An operating mode designation pin
14 X0
A Subclock oscillation pin
15 X1
16 Vss - Power supply pin (GND)
17 Vcc - Power supply pin
18 C H Capacitor connection pin
19 PG2/X1A
H/A
Single clock product is general-purpose port.
Dual clock product is main clock oscillation pin (32 kHz).
20 PG1/X0A
21 RST B Reset pin
22 P00/INT00
C
The pins are shared with external interrupt input. Large current port.
23 P01/INT01
24 P02/INT02
25 P03/INT03
26 P04/INT04
27 P05/INT05
28 P06/INT06
29 P07/INT07
30 P10/UI0 G
The pin is shared with UART/SIO ch0 data input.
(FPT-64P-M03, FPT-64P-M09)
s
s
V
A
0
N
A
/
0
3
P
0
0
N
A
/
1
3
P
1
0
N
A
/
2
3
P
2
0
N
A
/
3
3
P
3
0
N
A
/
4
3
P
4
0
N
A
/
5
3
P
5
0
N
A
/
6
3
P
6
0
N
A
/
7
3
P
7
0
N
A
/
0
4
P
8
0
N
A
/
1
4
P
9
1
N
A
/
2
4
P
0
1
N
A
/
3
4
P
1
N
I
S
/
7
6
P
T
O
S
/
6
6
P
K
C
S
/
5
6
P
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc 1
48 P64/EC1
AVR 2
47 P63/TO11
P E3/INT13 3
46 P62/TO10
P E2/INT12 4
45 P61/PPG11
P E1/INT11 5
44 P60/PPG10
P E0/INT10 6
43 P53/TRG1
P83 7
42 P52/PPG1
P82 8
41 P51/SDA0
P81 9
40 P50/SCL0
P80 10
39 P24/EC0
P71/TI0 11
38 P23/TO01
P70/TO0 12
37 P22/TO00
MOD 13
36 P21/PPG01
X0 14
35 P20/PPG00
X1 15
34 P14/PPG0
Vss 16
33 P13/TRG0/ADT G
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
c
c
V
C
*
A
1
X
/
2
G
P
*
A
0
X
/
1
G
P
T
S
R
P
0
0
T
N
I
/
0
0
P
1
0
T
N
I
/
1
0
P
2
0
T
N
I
/
2
0
P
3
0
T
N
I
/
3
0
P
4
0
T
N
I
/
4
0
P
5
0
T
N
I
/
5
0
P
6
0
T
N
I
/
6
0
P
7
0
T
N
I
/
7
0
0
I
U
/
0
1
P
0
O
U
/
1
1
P
P
0
K
C
U
/
2
1
64
TOP VIEW
* Single clock product is general-purpose port, and dual clock product is subclock oscillation pin.
TEST
4 5
Pin no.
Pin name
Circuit
type
Description
FPT-64P-M03
FPT-64P-M09
31 P11/UO0
H
The pin is shared with UART/SIO ch0 data output.
32 P12/UCK0
The pin is shared with UART/SIO ch0 clock I/O.
33
P13/TRG0/
ADTG
The pin is shared with 16-bit PP G ch0 trigger input (TRG0) and A/D
trigger input (ADTG).
34 P14/PPG0
The pin is shared with 16-bit PPG ch0 output.
35 P20/PPG00
H
The pins are shared with 8/16-bit PPG ch0 output.
36 P21/PPG01
37 P22/TO00
The pins are shared with 8/16-bit compound timer ch0 output.
38 P23/TO01
39 P24/EC0
The pin is shared with 8/16-bit compound timer ch0 clock input.
40 P50/SCL0
I
The pin is shared with I
2
C ch0 clock I/O.
41 P51/SDA0
2
C ch0 data I/O.
42 P52/PPG1
H
43 P53/TRG1
The pin is shared with 16-bit PPG ch1 trigger input.
44 P60/PPG10
K
45 P61/PPG11
46 P62/TO10
47 P63/TO11
48 P64/EC1
49 P65/SCK
The pin is shared with LIN-UART clock I/O.
50 P66/SOT
The pin is shared with LIN-UART data output.
51 P67/SIN L
The pin is shared with LIN-UART data input.
52 P43/AN11
J
The pins are shared with A/D analog input.
53 P42/AN10
54 P41/AN09
55 P40/AN08
Pin no.
Pin name
Circuit
type
Description
FPT-64P-M03
FPT-64P-M09
56 P37/AN07
J
57 P36/AN06
58 P35/AN05
59 P34/AN04
60 P33/AN03
61 P32/AN02
62 P31/AN01
63 P30/AN00
64 AVss - A/D power supply pin (GND)
TEST
6 7
SP232ACT
Enhanced RS-232 Line Drivers/Receivers
GGDESCRIPTION
GGFEATURE
The Sipex SP231A, SP232A and SP233A are enhanced versions of the Sipex SP231, SP232 and
SP233 RS-232 line drivers/receivers.
They are pin-for-pin replacements for these earlier versions and will operate in their sockets.
Performance enhancements include 10V/us slew rate,
120k bits per second guaranteed transmission rate,
and increased drive current for longer and more flexible cable configurations.
Ease of use enhancements include smaller, 0.1uF charge pump capacitors, enhanced ESD protection,
low power dissipation and overall ruggedized construction for commercial environments.
The series is available in plastic and ceramic DIP and SOIC packages operating over the commercial,
industrial and military temperature ranges.
The Sipex SP231A, SP232A and SP233A are enhanced versions of the Sipex SP231, SP232 and
SP233 RS-232 line drivers/receivers. They are pin for-pin replacements for these earlier versions,
will operate in their sockets with capacitors ranging from 0.1 to 100F,either polarized ornonpolarized,
and feature several improvements in both performance and ease of use. Performance enhancements include
10V/s slew rate, 120k bits per second guaranteed transmission rate, and increased drive current for
longer and more flexible cable configurations. Ease of use enhancements include smaller,
0.1Fchargepump capacitors, enhanced ESD protection, low power dissipation and overall ruggedized
construction for commercial environments.
The SP232A, SP233A, SP310A and SP312A include charge pump voltage converters which allow them to
operate from a single +5V supply. These converters convert the +5V input power to the 10V needed to
generate the RS-232 output levels. Both meet all EIA RS-232D and CCITT V.28 specifications.
The SP231A has provisions for external V+ supplies. With this power supplied externally,
the current drain due to charge pump operation is considerably reduced, typically to 400A.
The SP310A provides identical features as the SP232A. The SP310A has a single control line which
simultaneously shuts down the internal DC/DC converter and puts all transmitter and receiver
outputs into a high impedance state. The SP312A is identical to the SP310A with separate tri-state
and shutdown control lines.
The SP231A is available in 14-pin plastic DIP, CERDIPand 16-pin SOICpackages for
operation over commercial, industrial and military temperature ranges.
The SP232A is available in 16-pin plastic DIP,SOIC and CERDIP packages, operating over the commercial,
industrial and military temperature ranges. The SP233A is available in a 20-pin plastic DIP and
20pin SOIC package for operation over the commercial and industrial temperature ranges.
The SP310A and SP312A are available in 18-pin plastic, CERDIP and SOIC packages for operation
over the commercial and industrial temperature ranges. Please consult the factory for DIP and
surface-mount packaged parts supplied on tape-on-reel, as well as parts screened to MIL-M-38510.
GPIN ASSIGNMENT
V G
N
D
T

O
U
T
R

I
N
R

O
U
T
T

I
N
T

I
N
R

O
U
T
C
C
1
2
C

+
V
+
C

-
C

+
C

-
V
-
T

O
U
T
R

I
N
1
1
1
A 2 3 2 P S
1 2 3 4 5 6 7 8
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
1 2 2 2 2
1 2
TEST
8
ELECTRICAL ADJUSTMENT PROCEDURE (REAR PART)
9
PCM1738E
24-Bit, 192kHz Sampling,
Advanced Segment, Audio-Stereo
DIGITAL-TO-ANALOG CONVERTER
GGDESCRIPTION GGFEATURE
The PCM1738 is a CMOS, monolithic, Integrated
Circuit (IC) that includes stereo Digital-to-Analog
Converters (DACs) and support circuitry in a small
SSOP-28 package. The data converters utilize a
newly developed advanced segment DAC architecture
to achieve excellent dynamic performance and
improved tolerance to clock jitter. The PCM1738
provides balanced current outputs, allowing the user to
optimize analog performance externally, and accepts
industry standard audio data formats with 16- to
24-bit data, providing easy interfacing to audio DSP
and decoder chips. Sampling rates up to 200kHz are
supported.
The PCM1738 also has two optional modes of
operation: an external digitalfilter mode
(for use with the DF1704, DF1706, and PMD200),
and a DSD decoder interface for SACD playback
applications. A full set of user-programmable
functions are accessible through a 4-wire serial control
port that supports register write and read functions.
G24-BIT RESOLUTION
ANALOG PERFORMANCE (VCC = +5V):
Dynamic Range: 117dB typ
SNR: 117dB typ
THD+N: 0.0004% typ
Full-Scale Output: 2.2Vrms (at post amp)
DIFFERENTIAL CURRENT OUTPUT: 2.48mA
SAMPLING FREQUENCY: 10kHz to 200kHz
SYSTEM CLOCK: 128, 192, 256, 384, 512,
or 768fS with Auto Detect
ACCEPTS 16-, 20-, AND 24-BIT AUDIO DATA
DATA FORMATS: Standard, I2S, and Left-
Justified
8x OVERSAMPLING DIGITAL FILTER:
Stopband Attenuation: 82dB
Passband Ripple: 0.002dB
OPTIONAL INTERFACE TO EXTERNAL
DIGITAL FILTER AVAILABLE
OPTIONAL INTERFACE TO DSD DECODER
FOR SACD PLAYBACK
USER-PROGRAMMABLE MODE CONTROLS:
Digital Attenuation: 0dB to 120dB, 0.5dB/Step
Digital De-Emphasis
Digital Filter Roll-Off: Sharp or Slow Soft Mute
Zero Detect Mute
Zero Flags for Each Output
DUAL-SUPPLY OPERATION:
+5V Analog, +3.3V Digital
5V TOLERANT DIGITAL INPUTS
SMALL SSOP-28 PACKAGE
8
3
7
1
M
C
P
24LC02B
2K IC Serial EEPROM
GGDESCRIPTION GGPACKAGE TYPE (SOIC)
GGFEATURE
GGPIN DESCRIPTION
Single supply with operation down to 1.8V
Low-power CMOS technology
- 1 mA active current typical
- 1A standby current typical (I-temp)
Organized as 1 block of 256 bytes (1 x 256 x 8)
2-wire serial interface bus, IC compatible
Schmitt Trigger inputs for noise suppression
Output slope control to eliminate ground bounce
100 kHz (24AA02) and 400 kHz (24LC02B)
compatibility
Self-timed write cycle (including auto-erase)
Page write buffer for up to 8 bytes
2 ms typical write cycle time for page write
Hardware write-protect for entire memory
Can be operated as a serial ROM
Factory programming (QTP) available
ESD protection > 4,000V
1,000,000 erase/write cycles
Data retention > 200 years
8-lead PDIP, SOIC, TSSOP and MSOP packages
5-lead SOT-23 package
Pb-free finish available
Available for extended temperature ranges:
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C
The Microchip Technology Inc. 24AA02/24LC02B
(24XX02*) is a 2 Kbit Electrically Erasable PROM. The
operation down to 1.8V, with standby and active currents
has a page write capability for up to 8 bytes of data. The
available in the 5-lead SOT-23 package.
mount SOIC, TSSOP and MSOP packages and is also
with a 2-wire serial interface. Low-voltage design permits
24XX02 is available in the standard 8-pin PDIP, surface
of only 1A and 1 mA, respectively. The 24XX02 also
device is organized as one block of 256x8-bit memory
2
0
X
X
4
2
A0
A1
A2
Vss
1
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
PDIP/SOIC/TSSOP/MSOP
GGBLOCK DIAGRAM
HV
EEPROM
Array
Page
YDEC
XDEC
Sense Amp.
Memory
Control
Logic
I/O
Control
Logic
I/O
WP
SDA
SCL
VCC
VSS
R/W Control
Latches
Generator
Name
A0
A1
A2
Vss
SDA
SCL
WP
PDIP SOIC TSSOP MSOP SOT23 Description
Vcc
1 1 1 1
2 2 2 2
3 3 3 3
-
-
-
4 4 4 4 2
5 5 5 5
6 6 6 6
7 7 7 7
8 8 8 8
3
1
5
4
Not Connected
Not Connected
Not Connected
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
1.8V to 5.5V Power Supply
TEST
10 11
GGBLOCK DIAGRAM GPIN CONFIGURATION
GPIN ASSIGNMENT
RST
ZEROL
ZEROR
LRCK
DATA
BCK
SCKI
DGND
V
DD
SCKO
MDO
MDI
MC
CS
V
CC
3
AGND2
I
OUT
L
I
OUT
L+
V
CC
2
V
CC
1
V
COM
3
I
REF
V
COM
2
V
COM
1
AGND1
I
OUT
R+
I
OUT
R
MUTE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PCM1738
PIN NAME TYPE FUNCTION
1 RST IN Reset
(1)
2 ZEROL OUT Zero Flag for L-Channel.
3 ZEROR OUT Zero Flag for R-Channel.
4 LRCK IN Left/Right clock (f
S
) input for normal operation.
(1)
WDCK clock input in external DF mode. Connected to GND in DSD mode.
5 DATA IN Serial Audio data input for normal operation.
(1)
L-channel audio data input for external DF and DSD modes.
6 BCK IN Bit Clock. Input. Connected to GND for DSD mode.
(1)
7 SCKI IN System Clock Input for normal operation.
(1)
BCK (64f
S
) clock input for DSD mode.
8 DGND Digital Ground
9 V
DD
Digital Supply, +3.3V
10 SCKO OUT System Clock Output
11 MDO OUT Serial data output for function control register.
(2)
12 MDI IN Serial data input for function control register.
(1)
13 MC IN Shift Clock for function control register.
(1)
14 CS IN Mode Control chip select and latch signal.
(1)
15 MUTE IN Analog output mute control for normal operation.
(1)
R-channel audio data input for external DF and DSD modes.
16 I
OUT
R OUT R-Channel Analog Current Output
17 I
OUT
R+ OUT R-Channel Analog Current Output +
18 AGND1 Analog Ground
19 V
COM
1 Internal Bias Decoupling Pin
20 V
COM
2 Common Voltage for I/V
21 I
REF
Output current reference bias pin. Connect 16k resistor to GND.
22 V
COM
3 Internal Bias Decoupling Pin
23 V
CC
1 Analog Supply, +5.0V
24 V
CC
2 Analog Supply, +5.0V
25 I
OUT
L+ OUT L-Channel Analog Current Output +
26 I
OUT
L OUT L-Channel Analog Current Output
27 AGND2 Analog Ground
28 V
CC
3 Analog Power Supply, +5.0V
NOTES: (1) Schmitt-trigger input, 5V tolerant. (2) Tristate output.
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TEST
12 13
AK4117
Low Power 192kHz Digital Audio Receiver
DESCRIPTION
FEATURE
The AK4117 is a S/PDIF AES/EBU receiver supporting sample rates up to 192kHz and resolution up to 24-bit.
The integrated channel status decoder supports both consumer and professional modes.
The AK4117 can automatically detect a Non-PCM bit stream.
Combining the AK4117 with a multi-channel codec such as AKMs AK4527B or AK4529 can create a complete
AC-3 system. Mode settings can be controlled via microprocessor serial interface. A low power mode is available
for normal speed modes and the small 24pin VSOP package saves board space.
AES3. EC60958. S}PDF. EAJ CP!20! Compalble
Low ller Analoq PLL
PLL Lock Panqe 32kHz lo !92kHz
Clock Source PLL or X'lal
2channel Pecever npuls Seleclor
Auxlary dqlal npul
Deleclon Funclons
NonPCM Bl Slream Deleclon
DTSCD Bl Slream Deleclon
Samplnq Frequency Deleclon
32kHz. 44.!kHz. 48kHz. 88.2kHz. 96kHz. !76.4kHz. !92kHz)
Unlock & Parly Error Deleclon
Valdly Flaq Deleclon
Up lo 24bl Audo Dala Formal
Audo }F Lell uslled. Pqhl uslled !6bl. !8bl. 20bl. 24bl). 2S
40bl Channel Slalus Buller
Bursl Preamble bl Pc and Pd Buller lor NonPCM bl slream
Qsubcode Buller lor CD bl slream
4wre Seral P }F
Masler Clock Culpul !28ls}256ls}5!2ls
Cperalnq Vollaqe 2.7 lo 3.6V
Small Packaqe 24pn VSCP
Ta 40 lo 85`C
BLOCK DIAGRAM
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&

D
e
t
e
c
t

S
T
A
T
U
S
I
N
T
1
Q
-
s
u
b
c
o
d
e
b
u
f
f
e
r

2

t
o

1

U
O
U
T
TEST
14
ELECTRICAL ADJUSTMENT PROCEDURE (CD MAIN PART)
15
GGPIN LAYOUT
GGPIN FUNCTION
PIN NAME I/O FUNCTION
External Resistor Pin
12k-5% ~ 13k+5% resistor to AVSS externally.
Analog Power Supply Pin
Receiver Channel 1 (Internal Biased Pin)
No Connect
No internal bonding.
Receiver Channel 0 (Internal Biased Pin)
Digital Power Supply Pin
Digital Ground Pin
X'tal Input Pin
X'tal Output Pin
Output Channel Clock Pin
Audio Serial Data Clock Pin
Audio Serial Data Output Pin
Auxiliary Audio Data Input Pin
Master Clock Output Pin
No Connect
No internal bonding.
U-bit Output Pin
When UOUTE bit = 0, UOUT pin = L.
Control Data Output Pin
Control Data Input Pin
Control Data Clock Pin
Chip Select Pin
Interrupt 1 Pin
Interrupt 0 Pin
Power-Down & Reset Pin
When L, the AK4117 is powered-down and reset, and all output pins go to
L and the control registers are reset to default state.
Analog Ground Pin
-
-
I
-
I
-
-
I
O
O
O
O
I
O
-
O
O
I
I
I
O
O
I
-
R
AVDD
RXI
NC
RX0
DVDD
DVSS
XTI
XTO
LRCK
BICK
SDTO
DAUX
MCKO
NC
UOUT
CDTO
CDTI
CCLK
CSN
INT1
INT0
PDN
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Note 1: All input pins except internal biased pins should not be left floating.
6
5
4
3
2
1 R
AVDD
NC
RX1
RX0
DVDD
DVSS 7
XTI 8
AVSS
PDN
INT0
INT1
CSN
CCLK
CDTI
CDTO
Top
View
10
9 XTO
LRCK
BICK 11
SDTO 12
UOUT
NC
MCKO
DAUX
19
20
21
22
23
24
18
17
15
16
14
13
MB95F108AW
8-bit Proprietary Microcontrollers
GGDESCRIPTION
GGFEATURE
The MB95100A series is general-purpose, single-chip microcontrollers.
In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions.
64-pin plastic LQFP (FPT-64P-M03)
FMC-8FX CPU core
Instruction set optimized for controllers
GGGGGG Multiplication and division instructions
GGGGGG 16-bit arithmetic operations
GGGGGG Bit test branch instruction
GGGGGG Bit manipulation instructions etc.
Clock
GGGGGG Main clock
GGGGGG Main PLL clock
GGGGGG Subclock (for dual clock product)
GGGGGG Sub PLL clock (for dual clock product)
Timer
GGGGGG 8/16-bit compound timer x 2 channels
GGGGGG 16-bit reload timer
GGGGGG 8/16-bit PPG x 2 channels
GGGGGG 16-bit PPG x 2 channels
GGGGGG Timebase timer
GGGGGG Watch prescaler (for dual clock product)
LIN-UART
GGGGGG Full duplex double buffer
GGGGGG Clock asynchronous or synchronous serial transfer capable
UART/SIO
GGGGGG Clock asynchronous or synchronous serial transfer capable
IC*
GGGGGG Built-in wake-up function
External interrupt
GGGGGG Interrupt by edge detection (rising, falling, or both edges can be selected)
GGGGGG Can be used to recover from low-power consumption modes.
10-bit A/D converter
GGGGGG 10-bit resolution
Low-power consumption (standby mode)
GGGGGG Stop mode
GGGGGG Sleep mode
GGGGGG Watch mode (for dual clock product)
GGGGGG Timebase timer mode
I/O port: Max 55
GGGGGG General-purpose I/O ports (Nch open drain) : 6 ports
GGGGGG General-purpose I/O ports (CMOS) : 49 ports
TEST
16 17
GPIN ASSIGNMENT
s
s
V
A
0
N
A
/
0
3
P
0
0
N
A
/
1
3
P
1
0
N
A
/
2
3
P
2
0
N
A
/
3
3
P
3
0
N
A
/
4
3
P
4
0
N
A
/
5
3
P
5
0
N
A
/
6
3
P
6
0
N
A
/
7
3
P
7
0
N
A
/
0
4
P
8
0
N
A
/
1
4
P
9
1
N
A
/
2
4
P
0
1
N
A
/
3
4
P
1
N
I
S
/
7
6
P
T
O
S
/
6
6
P
K
C
S
/
5
6
P
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVcc 1 48 P64/EC1
AVR 2 47 P63/TO11
P E3/INT13 3 46 P62/TO10
P E2/INT12 4 45 P61/PPG11
P E1/INT11 5 44 P60/PPG10
P E0/INT10 6 43 P53/TRG1
P83 7 42 P52/PPG1
P82 8 41 P51/SDA0
P81 9 40 P50/SCL0
P80 10 39 P24/EC0
P71/TI0 11 38 P23/TO01
P70/TO0 12 37 P22/TO00
MOD 13 36 P21/PPG01
X0 14 35 P20/PPG00
X1 15 34 P14/PPG0
Vss 16 33 P13/TRG0/ADT G
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
c
c
V
0
G
P
A
1
X
/
2
G
P
A
0
X
/
1
G
P
T
S
R
P
0
0
T
N
I
/
0
0
P
1
0
T
N
I
/
1
0
P
2
0
T
N
I
/
2
0
P
3
0
T
N
I
/
3
0
P
4
0
T
N
I
/
4
0
P
5
0
T
N
I
/
5
0
P
6
0
T
N
I
/
6
0
P
7
0
T
N
I
/
7
0
0
I
U
/
0
1
P
0
O
U
/
1
1
P
0
K
C
U
2
1
P
64
TOP VIEW
GPIN DESCRIPTION
(Continued)
Pin no. Pin name
Circuit
type
Description
1 AVcc A/D power supply pin
2 AVR A/D reference input pin
3 PE3/INT13
P
General-purpose I/O port
The pins are shared with the external interrupt input.
4 PE2/INT12
5 PE1/INT11
6 PE0/INT10
7 P83
O General-purpose I/O port
8 P82
9 P81
10 P80
11 P71/TI0
H
The pin is shared with 16 - bit reload timer ch0 output.
12 P70/TO0
The pin is shared with 16 - bit reload timer ch0 input.
13 MOD B An operating mode designation pin
14 X0
A Crystal oscillation pin
15 X1
16 Vss Power supply pin (GND)
17 Vcc Power supply pin
18 PG0 H General-purpose I/O port.
19 PG2/X1A
H/A
Single-system product is general-purpose port.
Dual-system product is Crystal oscillation pin (32 kHz).
20 PG1/X0A
21 RST B Reset pin
22 P00/INT00
C
The pins are shared with external interrupt input. Large current port.
23 P01/INT01
24 P02/INT02
25 P03/INT03
26 P04/INT04
27 P05/INT05
28 P06/INT06
29 P07/INT07
30 P10/UI0 G
The pin is shared with UART/SIO ch0 data input.
TEST
18 19
Pin no. Pin name
Circuit
type
Description
31 P11/UO0
H
The pin is shared with UART/SIO ch0 data output.
32 P12/UCK0
The pin is shared with UART/SIO ch0 clock I/O.
33
P13/TRG0/
ADTG
The pin is shared with 16-bit PPG ch0 trigger input (TRG0) and A/D
trigger input (ADTG).
34 P14/PPG0
35 P20/PPG00
H
36 P21/PPG01
37 P22/TO00
38 P23/TO01
39 P24/EC0
40 P50/SCL0
I
2
C ch0 clock I/O.
41 P51/SDA0
2
C ch0 data I/O.
42 P52/PPG1
H
43 P53/TRG1
The pin is shared with 16-bit PPG ch1 trigger input.
44 P60/PPG10
K
45 P61/PPG11
46 P62/TO10
47 P63/TO11
48 P64/EC1
49 P65/SCK
The pin is shared with LIN-UART clock I/O.
50 P66/SOT
The pin is shared with LIN-UART data output.
51 P67/SIN L
The pin is shared with LIN-UART data input.
52 P43/AN11
J
53 P42/AN10
54 P41/AN09
55 P40/AN08
Pin no. Pin name
Circuit
type
Description
56 P37/AN07
J
57 P36/AN06
58 P35/AN05
59 P34/AN04
60 P33/AN03
61 P32/AN02
62 P31/AN01
63 P30/AN00
64 AVss A/D power supply pin (GND)
TEST
20 21
GGBLOCK DIAGRAM
1
P80 ~ P83
P14/PPG0
P53/TRG1
P65/SCK
P67/SIN
PE0/INT10 ~ PE3/INT1 3
AV CC
AV SS
AVR
P52/PPG1
P50/SCL0
P51/SDA0
P40/AN08 ~ P43/AN11
P30/AN00 ~ P37/AN07
P21/PPG01
P22/TO00
P23/TO01
P24/EC0
P12/UCK0
P62/TO10
P61/PPG11
P60/PPG10
P63/TO11
P 00/INT00 ~ P07/INT07
P10/UI0
P64/EC1
P71/TI0
P66/SOT
P70/TO0
RST
X0,X1
PG2/X1A*
PG1/X0A*
PG0
MOD, VCC, VSS
P13/TRG0/ADTG
P20/PPG00
P11/UO0
I
2
C
F
2
MC-8FX CPU
UART/SIO
16 bit-PPG ch0
8/16-bit PPG ch0
10-bit A/D
converter
C
16-bit PPG ch1
LIN-UART
8/16-bit PPG ch1
ROM
RAM
Port Port
External interrupt ch8 to ch11
8/16-bit compound
timer ch0
16-bit reload timer
8/16-bit compound
timer ch1
Interrupt control
Wild register
Reset control
Clock control
Watch prescaler
Watch counter
External interrupt ch0 to ch7
s
u
b

l
a
n
r
e
t
n
I
* : Single-system product is general-purpose port, and dual-system product is subclock oscillation.
Other pins
S5L9290X02
DIGITAL SIGNAL PROCESSOR FOR INTERNET AUDIO
GGDESCRIPTION
GGFEATURE
S5L9290X02 is a signal processing LSI for the Internet Audio (CD-MP3 etc) interface only.
Digital processing function (EFM demodulation, error correction), spindle motor servo processing,
wide capture range DPLL and 1-bit DAC for the Internet Audio CD player are installed in S5L9290X02.
Signal processing part
EFM data demodulation
Frame sync detection, protection, insertion
Sub code data processing (Q data CRC check, Q data register installed)
Error correction (C1: 2 error correction, C2: 4 erasure correction)
Installed 16K SRAM for De-interleave
Interpolation
Digital audio interface
CLV servo control (X1, X2)
Wide capture range digital PLL ( 50%)
Digital filter, DAC part
4 times over sampling digital filter
Digital de-emphasis (can be process the 32kHz, 44.1kHz, 48kHz)
Sigma-delta stereo DAC installed
Audio L.P.F installed
48-LQFP-0707
#1
TEST
22 23
GGBLOCK DIAGRAM GGPIN CONFIGURATION
D
P
L
L
C
L
V
S
e
r
v
o
L
O
C
K
S
M
E
F
S
M
D
P
S
M
D
S
W
D
C
K
E
F
M
I
V
C
O
1
L
F
T
i
m
i
n
g
G
e
n
e
r
a
t
o
r
M
i
c
o
m
I
n
t
e
r
f
a
c
e
W
F
C
K
R
F
C
K
C
4
M
X
I
N
I
S
T
A
T
M
L
T
M
D
A
T
M
C
K
M
U
T
E
S
u
b
c
o
d
e
O
u
t
E
F
M
D
e
m
o
d
u
l
a
t
o
r
E
C
C
1
6
K
S
R
A
M
A
d
d
r
e
s
s
G
e
n
e
r
a
t
o
r
S
Q
C
K
S
B
C
K
S
O
S
1
S
Q
D
T
S
B
D
T
I
n
t
e
r
p
o
l
a
t
o
r
I
/
O
I
n
t
e
r
f
a
c
e
J
I
T
B
L
P
F
P
W
M
S
A
D
T
O
L
R
C
K
O
B
C
K
O
L
C
H
O
U
T
R
C
H
O
U
T
V
H
A
L
F
V
R
E
F
1
-
b
i
t
D
A
C
D
i
g
i
t
a
l
O
u
t
D
i
g
i
t
a
l
F
i
l
t
e
r
C
2
P
O
D
A
T
X
S
A
D
T
I
L
R
C
K
I
B
C
K
I
S5L9290X02
DSP+DAC
48-LQFP-0707
VSSA_PLL
VCO1LF
VSSD_PLL
VDDD_PLL
XI N
XOUT
EFMI
LOCK
SMEF
C2PO
JI TB
DATX
VDDD3- 5V
VDDD2- 3V
SBCK
SQDT SMON
V
T
S
E
T
S
D
M
S
K
C
D
W
MUTE
I
K
C
B
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
VDDD1_5V
VSSD1_5V
S
F
K
L
S
F
K
L
B
T
E
S
E
R
T
L
M
T
A
D
M
K
C
M
T
A
T
S
I
1
S
0
S
K
C
Q
S
VSSD2- 3V
SADTO
L RCKO
BCKO
I
K
C
R
L
I
T
D
A
S
C
A
D
_
D
S
S
V
C
A
D
_
D
D
D
V
T
U
O
H
C
R
C
A
D
_
A
S
S
V
F
E
R
V
F
L
A
H
V
C
A
D
_
A
D
D
V
T
U
O
H
R
L
L
L
P
_
A
D
D
V
TEST
24 25
GGPIN DESCRIPTION
NO. NAME I/O Pin Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
VSSA_PLL
VCO1LF
VSSD_PLL
VDDD_PLL
VDDD1-5V
XIN
XOUT
VSSD1
EFMI
LOCK
SMEF
SMDP
SMDS
WDCK
TESTV
LKFS
C4M
RESETB
MLT
MDAT
MCK
ISTAT
SOS1
SQCK
SQDT
MUTE
VDDD2-3V
VSSD2
VDDD3-5V
SBCK
JITB
C2PO
DATX
SADTO
-
O
-
-
-
I
O
-
I
O
O
O
O
O
I
O
O
I
I
I
I
O
O
I
O
I
-
-
-
I
O
O
O
O
Analog Ground for DPLL
Pump out for VCO1
Digital Ground Separated Bulk Bias for DPLL
Digital Power Separated Bulk Bias for DPLL (3V Power)
Digital power (5V Power, I/O PAD)
Xtal oscillator input (16.9344MHz)
Xtal oscillator output
Digital Ground (I/O PAD)
EFM signal input
CLV Servo locking status ouput
LPF time constant control of the spindle servo error signal
Phase control output for Spindle Motor drive
Speed control output for Spindle Motor drive
Word clock output (Narmal Speed : 88.2kHz, Double Speed : 176kHz)
Various Data/Clock Input
The Lock status output of frame sync
4.2336MHz clock output
System Reset at L
Latch data input from Micom
Serial data input from Micom
Serial data receiving clock input from Micom
The internal status output to Micom
Subcode sync signal (S0+S1) output
Subcode-Q data transfering bit clock input
Subcode-Q data serial output
System mute at H
Digital Power (3V Power, Internal Logic)
Digital Ground (Internal Logic)
Digital Power (5V Power, I/O PAD)
Subcode data transfering bit clock
Internal SRAM jitter margin status output
C2 pointer output
Digital audio data output
Serial audio data output (48 slot, MSB first)
NO. NAME I/O Function Description
35
36
37
38
39
40
41
42
43
44
45
46
47
48
LRCKO
BCKO
BCKI
LRCKI
SADTI
VSSD_DAC
VDDD_DAC
RCHOUT
VSSA_DAC
VREF
VHALF
VDDA_DAC
LCHOUT
VDDA_PLL
O
O
I
I
I
-
-
O
-
O
O
-
O
-
Channel clock output
Bit clock output
Bit clock input
Channel clock input
Serial audio data input (48 slot, MSB first)
Digital Ground for DAC
Digital Power for DAC (3V Power)
Right-Chnanel audio output through DAC
Analog Ground for DAC
Referance Voltage output for bypass
Referance Voltage output for bypass
Analog Power for DAC (3V Power)
Left-Channel audio outpu through DAC
Analog Power for PLL (3V Power)
TEST
26 27
K4S641632H
SDRAM 64Mb H-die
GGDESCRIPTION
GGFEATURE
The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM
organized as 4 x 4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits,
fabricated with SAMSUNG?s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high performance memory system applications.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock
Burst read single-bit write operation
DQM (x4,x8) & L(U)DQM (x16) for masking
Auto & self refresh
64ms refresh period (4K cycle)
Pb-free Package
RoHS compliant
GBLOCK DIAGRAM
B
a
n
k

S
e
l
e
c
t
D
a
t
a

I
n
p
u
t

R
e
g
i
s
t
e
r
4
M

x

4

/

2
M

x

8

/

1
M

x

1
6
4
M

x

4

/

2
M

x

8

/

1
M

x

1
6
P M A e s n e S
r e f f u B t u p t u O l o r t n o C O / I
C
o
l
u
m
n

D
e
c
o
d
e
r
L
a
t
e
n
c
y

&

B
u
r
s
t

L
e
n
g
t
h
P
r
o
g
r
a
m
m
i
n
g

R
e
g
i
s
t
e
r
r e t s i g e R s s e r d d A
r e f f u B w o R
r e t n u o C h s e r f e R
r e f f u B . l o C r e d o c e D w o R
S A R L
R B C L
L
C
K
E
L
R
A
S
L
C
B
R
L
W
E
L
D
Q
M
C
L
K
C
K
E
C
S
R
A
S
C
A
S
W
E
L
(
U
)
D
Q
M
L
W
E
L
D
Q
M
D
Q
i
C
L
K
A
D
D
L
C
A
S
L
W
C
B
R
4
M

x

4

/

2
M

x

8

/

1
M

x

1
6
4
M

x

4

/

2
M

x

8

/

1
M

x

1
6
T
i
m
i
n
g

R
e
g
i
s
t
e
r
* Samsung Electronics reserves the right to change products or specification without notice.
TEST
28 29
GGPIN CONFIGURATION
GGPIN klzjypw{pvu
S1L9226X
RF AMP & SERVO SIGNAL PROCESSOR
GGDESCRIPTION
GGFEATURE
As a pre-signal & servo signal processor for the DISC-MAN, S1L9226X is a low voltage,
low consumption current IC that can read CD-RW, and CD-R discs and can be applied to various products,
such as the CDP/VCD/CDMP3 for the DISC-MAN. It is a hard-wired free-adjustment servo,
which automatically controlled the control point of the pre-signal portion.
RF amplifier (CD, CD-R, CD-RW applicable)
Gain setting & monitoring for the CD-R, CD-RW DISC
RFAMP offset adjustment
Focus error amp & Febias adjustment
Tracking error amp & balance, gain adjustment
FOK, defect, mirror detect
Center voltage amplifier
APC (Automatic Power Control)
RF AGC & EQ control (AGC Level Control Compatible)
Enhanced EFM slice (Double Asymmetry Method)
Focus servo loop & offset adjustment
Tracking servo loop & offset adjustment
Sled servo loop
Spindle servo loop
Auto-sequence
Fast search mode (1 - 36000 track jump)
Interruption countermeasure
Focus & Tracking servo muting controlled by EFM duty check
RF peaking prevention system by EFM duty check
Focus, tracking, spindle loop pole move option
Operating voltage 2.7V ??3.3V
Power saving mode
<Notice> LPC Control used by side beam signal, it related to pick-up assurance.
When used pick-up, the specification is present extra.
48-LQFP-0707
#1
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select
Disables or enables device opemasking or enabling all inputs except ration by
CLK, CKE and DQM
CKE Clock enable
Masks system clock to freeze operat ion from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A11 Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0~ RA11,
Column address : (x4 : CA0 ~ CA9 ,x8 : CA0 ~ CA8 ,x16 : CA0 ~ CA7)
BA0 ~ BA1 Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQ0 ~ X15 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
N.C/RFU
No connection
/reserved for future use
This pin is recommended to be left No Connection on the device.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
(Top view)
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
x16 x8 x4 x16 x8 x4
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
N.C/RFU
UDQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
N.C
VDDQ
N.C
DQ0
VSSQ
N.C
N.C
VDDQ
N.C
DQ1
VSSQ
N.C
VDD
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
N.C
VSSQ
N.C
DQ3
VDDQ
N.C
N.C
VSSQ
N.C
DQ2
VDDQ
N.C
VSS
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
N.C
DQ1
VSSQ
N.C
DQ2
VDDQ
N.C
DQ3
VSSQ
N.C
VDD
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
N.C
DQ6
VDDQ
N.C
DQ5
VSSQ
N.C
DQ4
VDDQ
N.C
VSS
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
VSS
TEST
30 31
GGBLOCK DIAGRAM
4
12
RF AGC & EQ
Control
Focus OK Detect
Defect Detect Mirror
Gen
Center
Voltage
APC. Laser
Control &
LPC
Tracking Servo Loop
- Gain & Phase
Compensation
- Track Jump
- Offset Adjust
- TZC Gen.
Tracking Error
(RW)
I/V AMP
RF & Focus
Error (CD-RW)
I/V AMP
Hardware Logic
- Auto-Sequencer
- Fast Search
- Febias, Focus Servo,
Tracking Offset ADJ.
- Tracking Balance & Gain
Adjust
- Interruption Detect
- EFM Muting System
Sled Servo &
Kick Gen
Spindle
Servo LPF
EFM
Comparator
Micom Data Interface Logic Decoder
Focus Servo Loop
- Gain & Phase
Compensation
- Focus Search
- Offset Adjust
- FZC Gen.
EQO
PD
LD
LPFT
TEIO
TZC&
SSTOP
ATSC
TEO
TEM
SLP
SLO
SLM
FEO
FEM
SPDLO
SPDLM
I
Q
E
O
F
R
M
F
R
C
Q
E
F
E
R
V
E
D
P
F
D
P
D
B
D
P
C
A
D
P
T
A
T
S
I
K
C
M
A
T
A
D
M
T
L
M
T
E
S
E
R
K
C
D
W
I
V
L
C
K
C
O
L
Y
S
A
M
F
E
5
45
46
44
43
6
7
8
9
10
11
14 13 15 16 17 19 18 20 22 21
24
23
30
29
25
26
27
28
29
36
33
34
35
37
38
39
41 40 42 47 48 1 2 3
EFMI
DCCI
DCC0
MCP
DCB
VCC/
VDD
FRSH
FSET
FLB
FGD
FSI
TGU
GPIN CONFIGURATION
GPIN DESCRIPTION
S1L9226X
O
E
T
M
E
T
P
L
S
O
L
S
M
L
S
ISTAT
MCK
MDATA
MLT
RESET
WDCK
CLVI
LOCK
ASY
EFM
SPM
I
M
F
E
C
C
V
H
S
R
F
T
E
S
F
B
L
F
D
G
F
I
S
F
U
G
T
O
Q
E
I
Q
E
O
F
R
M
F
R
PD
LD 37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
SPO
M
E
F
O
E
F
D
N
G
P
O
T
S
S
/
C
Z
T
O
I
E
T
T
F
P
L
C
S
T
A
PDAC
PDF
PDBD
PDE
DCB
MCP
DCCI
DCCO
VREF
EQC
Pin No. Symbol I/O Description
1 RFM I RF summing amp. inverting input
2 RFO O RF summing amp. output
3 EQI I RFO DC eliminating input(use by MIRROR, FOK ,AGC & EQ terminal)
4 EQO O RF equalizer output
5 EFMI I EFM slice input. (input impedance 47K)
6 VCC P Main power supply
7 FRSH I Capcitor connection to focus search
8 FSET I Filter bias for focus,tracking,spindle
9 FLB I Capacitor connection to make focus loop rising band
10 FGD I Terminal to change the hign frequency gain of focus loop
11 FSI I Focus servo input
12 TGU I Connect the component to change the high frequency of tracking Loop
13 ISTAT O Internal status output
14 MCK I Micom clock
15 MDATA I Data input
16 MLT I Data latch input
17 RESET I Reset input
(Continued)
TEST
32 33
MLC3300
MPEG Audio Layer2/3 and WMA with CDROM Decoder
GGDESCRIPTION
The MLC3300 is a single chip of ultra low power multi format
digital audio decoder with additional CDROM decoder. It also
offers more variety of flexibility and very high performance to
users application. This product employs new cutting-edge and high
performance RISC-DSP CPU core, very efficient and flexible firmware
and multiplex peripherals. The embedded RISC-DSP core and
advanced architecture provide most efficient performance for
decoding multi format digital audio files and controllability for
Compact disc player system.
The MLC3300 is fabricated with advanced CMOS technology and
designed for consuming innovative ultra low power. The MLC3300
decodes MPEG layer2 and layer3 formats and WMA (Windows
media audio) format including ASF (Advanced Systems Format) files.
The MLC3300 is also designed to be able to employ many kinds of
Non-Volatile memory as external program memory and SDRAM as
external data memory. The external Non-Volatile memory can be
used as not only upgradeable program memory area but also
users data storage. Also the external SDRAM can be used as the flexible
memory buffer for MPEG / WMA bit stream, compressed audio data and
temporary data of the host controller. The MLC3300 supports two ways
for handshaking with host system controller in both parallel
and serial communication. The programmable-DAC-controller-
configuration and auto-sampling-rate-conversion functionalities
can be communicated with any general DAC and dedicated
Red Book audio DAC.
GGFEATURE
1. Physical
- Supply voltage: 2.5V 10%, I/O supply power: 3.3V 10%
- Ultra low power consumption: 65mW 10%
- Flexible crystal frequencies of 16.9344Mhz and 33.8688Mhz
- 100 TQFP
2. Firmware
- Single-chip MPEG 1/2 layer 2 and 3 decoder with
CDROM decoder
- Windows Media Audio (WMA) decoding regardless bit rate
- Audio decoding of Window Media Video (WMV)
- Supports ASF (Advanced Systems Format) decoding
- Support ID3 tag V1 and V2 extraction.
- Extension to MPEG 2 / layer 2 and 3 for low bit rates
(MPEG 2.5 - LSF)
- Bit stream with variable bit rates (bit rate switching) are supported.
- Full MPEG bit rates including free format
- Full bit rates WMA file Decoding
- Supports Software MUTE / Pause / Resume
- Supports ISO9660 CDROM Mode1/Mode2 format (CDROM-XA)
- Supports Joliet decoding both single-session and multi-session disc
- Supports Joliet Level 3 decoding as call UDF Bridge
- Supports UDF (Universal Disk Format) decoding in Packet writing
format CD-RW disc and in Non-packet writing CD-R disc.
- Support the sorting directories and files in name order.
- Support the playing list file as like xxx.pls and xxx.m3u
- High quality voice recoding
- CD-TEXT format decoding in Lead-in area.
- Digital volume control
- 7-band sound Equalizer for MP3, WMA and Red book audio CD
- 7 band graphic Equalizer for MP3, WMA and Red book audio CD
- MEBB (MCS Logic Enhanced Bass band) sound algorithm
- Optional sampling rate conversion to 44.1Khz for off-chip
general audio DAC
- Channel mixing or separating for two different audio sources
- Improved high quality sound at high compression rate of ESP
- Supports time display (Normal / FF / FB)
- Dynamic classification of memory area cluster
3. Interface
- Serial Host Controller interface / Parallel Host Controller Interface
- Audio PCM output delivered via I2S bus
- Connection to external memory
SDRAM from 16M bits to 256M bits with 16 bits data bus
Programmable access time control
- Connection to external program memory
Flash (NOR type), EPROM and Mask ROM up to 16M bits
with 8 bits data bus
2-wire I2C serial EEPROM
Host controller direct access to NOR-Flash, EPROM, Mask ROM
- Compatible with various format of CDROM
(Mode 1, Mode 2/Form 1 and Mode 2/Form 2)
- Supports Fast CDROM decoding up to 4X
- Real-Time One Error Correction and Detection for CDROM
- Additional functionality achievable by downloading supplied firmware
- Video CD mode (Play MPEG audio data from VCD)
- Audio CD mode
1) Audio bypass mode.
2) Anti-shock proof on audio CD mode:
18 CLVI I Input the spindle control output from DSP
19 WDCK I 88.2KHz input terminal from DSP
20 LOCK I Sled run away inhibit pin (L: sled off & tracking gain up)
21 EFM O EFM output for RFO slice(to DSP)
22 ASY I Auto asymmetry control input
23 SPM I Spindle amp. inverting input
24 SPO O Spindle amp. output
25 SLM I Sled servo inverting input
26 SLO O Sled servo output
27 SLP I Sled servo noninverting input
28 TEM I Tracking servo amp.inverting input
29 TEO O Tracking servo amp. output
30 FEM I Focus servo amp. inverting input
31 FEO O Focus servo amp. output pin
Pin No. Symbol I/O Description
32 GND P Main ground
33 TZC/
SSTOP
I
Tracking zero crossing input & Check the position of pick-up wherther inside or not
34 TEIO B Tracking error output & Tracking servo input
35 LPFT I Tracking error integration input (to automatic control)
36 ATSC I Anti-shock input
37 LD O APC amp. output
38 PD I APC amp. input
39 PDAC I Photo diode A & C RF I/V amp. inverting input
40 PDBD I Photo diode B & D RF I/V amp. inverting input
41 PDF I Photo diode F & tracking(F) I/V amp. inverting input
42 PDE I Photo diode E & tracking(E) I/V amp. inverting input
43 DCB I Capacitor connection to limit the defect detection
44 MCP I Capacitor connection to mirror hold
45 DCCI O Output pin to connect the component for defect detect
46 DCCO I Input pin to connect the component for defect detect
47 VREF O (VCC+GND)/2 Voltage reference output
48 EQC I AGC_equalize level control terminal & capacitor terminal to input in to VCA
TEST
34 35
GGBLOCK DIAGRAM GGPIN CONFIGURATION
MLC3300 / MLC3310
5
7
6
1
D
A
E
4
7
A
T
A
D
D
3
7
2
7
1
7
0
7
K
C
M
D
9
6
8
6
7
6
D
D
V
6
6
5
6
S
S
V
4
6
3
6
2
6
1
6
0
6
9
5
7
5
8
5
6
5
45
44
43
42
41
40
39
38
37
BA1
BA0
UDQM
AD12
SDCSN
SDCLK
AD11
RASN
CASN
CKE
WEN
VDD
VSS 36
35
34
33
32
31
30
29
28
27
26
VDD
BCLK
DATA
LRCK
SCOR
VSS
PLLAVDD
PLLAVSS
XI
XO
IOVDD
IOVSS
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
S
S
V
D
D
V
1 2 3 4 5 6 7 8 9
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
1
0
2
TOP VIEW
100 TQFP
AD10
AD8
SCLK
SDAT
SLAT
SENSEB
HAD0
HAD1
SYNC
C
N
n
T
E
S
E
R
NC must be connected to ground
D
D
V
O
I
S
S
V
O
I
AD5
AD6
AD4
AD3
0
D
A
7
D
6
D
5
D
4
D
2
D
3
D
1
D
0
D
R
E
T
L
I
F
AD9
S
S
V
HAD2
K
C
R
L
D
K
C
B
D
IOVSS
IOVDD
AD7
D
D
V
LDQM
5
1
D
1
2
2
2
3
2
4
2
5
2
50
49
48
47
46
5
5
4
5
2
5
3
5
1
5
76
77
78
79
80
HAD3
HAD4
HAD5
HAD6
7
D
A
H
0
1
D
9
D
8
D
3
1
D
2
1
D
1
1
D
4
1
D
]
1
[
5
P
]
2
[
5
P
AD2
S
S
V
O
I
D
D
V
O
I
XISEL
]
3
[
5
P
]
4
[
5
P
E
D
O
M
S
P
1
D
A
7
1
D
A
E
8
1
D
A
E
9
1
D
A
E
0
2
D
A
E
N
E
W
E
N
E
O
E
N
S
C
E
]
0
[
5
P
AD[12:0]
D[15:0]
SDCSN
RASN
CASN
WEN
Reset
&
Clock
External
DAC
Interface
PLL
RISC-DSP
CORE
Memory
Interface
M
Q
D
]
L
/
U
[
]
0
:
1
[
A
B
XI
XO
RESETn
FILTER
DDATA
DLRCK
DBCK
DMCK
E
K
C
K
L
C
D
S
EPIO
P5[4:0]
Cache
XISEL
Host
Interface
SCLK
SDAT
SLAT
SENSEB
PSMODE
DATA
LRCK
BCK
SCOR
CDROM
Decoder
SYNC
MP3/WMA
Firmware
ROM
EAD[20:16]
N
E
W
E
N
E
O
E
N
S
C
E
[Fig 1] Host Controller Serial Interface
Note: The PSMODE pin has to be stuck to IOVDD for this serial interface mode.
TEST
36 37
GGPIN DESCRIPTION
Pin# Pin Name I/O Description
Default
I/O
Mode
Pull-up
Pull-down
1 FILTER O 820pF capacitor is connected to PLLAVSS for PLL O
2 VDD Digital Power supply
3 VSS Digital Ground
External SDRAM data bus [0]
Also used as data[0] for external program memory
14 D8 I/O External SDRAM data bus [8] I Pull-up
15 IOVDD IO Power supply
16 IOVSS IO Ground
External SDRAM address bus [0]
Also used as address[0] for external EPROM,
Mask-ROM or FLASH-NOR
D0
D1
D2
D3
D4
D5
D6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D7 I/O
AD0 O
AD1 O
AD2 O
AD3 O
AD4 O
AD5 O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
4
5
6
7
8
9
10
13
24
25
26
27
28
29
Default
I/O
Mode
Pull-up
Pull-down
34 AD10 O External SDRAM address bus [10] O
Also used as address [10] for external EPROM,
39 CSN O SDRAM Chip selector O
40 CKE O SDRAM clock enable O
41 RASN O SDRAM RAS O
42 SDCLK O SDRAM clock O
43 IOVSS IO Ground
45 CASN O SDRAM CAS O
46 WEN O SDRAM WE O
SDRAM Bank selector 0
SDRAM Bank selector 1
SDRAM Lower data byte DQM
SDRAM Upper data byte DQM
Address[16] for external EPROM, Mask-ROM or
FLASH-NOR
FLASH-NOR
FLASH-NOR
FLASH-NOR
AD6 O O 30
31 AD7 O O
33 AD9 O O
32 AD8 O O
37 AD11 O
38 AD12 O
47 BA0 O
48 BA1 O
49 LDQM O
50 UDQM O
51 EAD16 O
52 EAD17 O
53 EAD18 O
54 EAD19 O
O
O
O
O
O
O
O
O
O
O
TEST
38 39
Default
I/O
Mode
Pull-up
Pull-down
FLASH-NOR
56 EWEN O External FLASH-NOR WEN O
57 EOEN O External EPROM, Mask-ROM or FLASH-NOR OEN O
58 ECSN O External EPROM, Mask-ROM or FLASH-NOR CSN O
59 P5[0] I/O General Purpose I/O I Notes (1) I Notes(1)
60 VDD Digital Power Supply
62 DBCK O IS Serial Output Clock O
63 DLRCK O IS Serial Output Frame Identification O
64 DDATA O IS Serial Output Data O O
65 DMCK O Master clock Output for the DAC O
66 IOVSS IO Ground
68 NC I Not Connection (This pin has to connected to IOVSS) I Pull-down
69 RESETn I Chip Reset signal active L I Pull-up
70 P5[1] I/O General Purpose I/O I Notes(1)
74 PSMODE I Communication mode with host controller I I
75 HAD7 I/O Data bus [7] for parallel interface with host controller I Pull-up
83 SENSEB O Communication handshaking output with host controller O
Communication control signal input with host controller
Refer to Chapter 5.1 and 7.4
87 SYNC O CDROM Sync interrupt O
90 LRCK I LRCK input from CDDSP I
91 DATA I Serial bit DATA input from CDDSP I
92 BCLK I BCLK input from CDDSP I
93 SCOR I Sub-code block Sync from CDDSP I
94 XISEL I XI clock selector (Refer to Chapter 5.3) I
96 IOVSS IO Ground
97 XISEL I Clock In (16.9344Mhz / 33.8688Mhz) I
98 XO O Clock Out O
99 PLLAVSS PLL Ground
100 PLLAVDD PLL Power supply
84 SLAT I
O 55 EAD20 O
85 SDAT I
86 SCLK I
I
I
I
SST39VF020
Multi-Purpose Flash
GGDESCRIPTION GGFEATURE
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 are 64K x8, 128K x8, 256K x8 and 5124K x8
CMOS Multi-Purpose Flash (MPF) manufactured with
SSTs proprietary, high performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches. The SST39LF512/
010/020/040 devices write (Program or Erase) with a 3.0-
3.6V power supply. The SST39VF512/010/020/040
devices write with a 2.7-3.6V power supply. The devices
conform to JEDEC standard pinouts for x8 memories.
Featuring high performance Byte-Program, the SST39LF512/
010/020/040 and SST39VF512/010/020/040 devices
provide a maximum Byte-Program time of 20sec. These
devices use Toggle Bit or Data# Polling to indicate the
completion of Program operation. To protect against
inadvertent write, they have on-chip hardware and Software
Data Protection schemes. Designed, manufactured, and
tested for a wide spectrum of applications, they are offered
with a guaranteed typical endurance of 10,000cycles.
Data retention is rated at greater than 100 years.
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices are suited for applications that require
convenient and economical updating of program, configuration,
or data memory. For all system applications, they
significantly improves performance and reliability, while lowering
power consumption. They inherently use less energy
during Erase and Program than alternative flash technologies.
The total energy consumed is a function of the applied
voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time, the
total energy consumed during any Erase or Program operation
is less than alternative flash technologies. These devices
also improve flexibility while lowering the cost for program,
data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program cycles
that have occurred. Therefore the system software or hardware
does not have to be modified or de-rated as is necessary
with alternative flash technologies, whose Erase and Program
times increase with accumulated Erase/Program cycles.
To meet surface mount requirements, the SST39LF512/010/
020/040 and SST39VF512/010/020/040 devices are offered
in 32-lead PLCC and 32-lead TSOP packages. The SST39LF/
VF010 and SST39LF/VF020 are also offered in a 48-ball
TFBGA package. See Figures 1, 2, 3, and 4 for pin assignments.
Organized as 64K x8/ 128K x8/ 256K x8/ 512K x8
Single Voltage Read and Write Operations
3.0-3.6V for SST39LF512/010/020/040
2.7-3.6V for SST39VF512/010/020/040
Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
Low Power Consumption
(typical values at 14 MHz)
Active Current: 5 mA (typical)
Standby Current: 1 A (typical)
Sector-Erase Capability
Uniform 4 KByte sectors
Fast Read Access Time:
45 ns for SST39LF512/010/020/040
55 ns for SST39LF020/040
70 and 90 ns for SST39VF512/010/020/040
Latched Address and Data
Fast Erase and Byte-Program:
Sector-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Byte-Program Time: 14 s (typical)
Chip Rewrite Time:
1 second (typical) for SST39LF/VF512
2 seconds (typical) for SST39LF/VF010
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bit
Data# Polling
CMOS I/O Compatibility
JEDEC Standard
Flash EEPROM Pinouts and command sets
Packages Available
32-lead PLCC
32-lead TSOP (8mm x 14mm)
48-ball TFBGA (6mm x 8mm)
34-ball WFBGA (4mm x 6mm) for 1M and 2M
All non-Pb (lead-free) devices are RoHS compliant
TEST
40 41
GGBLOCK DIAGRAM
GGPIN ASSIGNMENTS
GGPIN DESCRIPTION
Y-Decoder
I/O Buffers and Data Latches
Address Buffers & Latches
X-Decoder
DQ
7
- DQ
0
Memory Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
NC
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
A17
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
A17
WE#
VDD
A18
A16
A15
A12
A7
A6
A5
A4
SST39LF/VF512
SST39LF/VF010
SST39LF/VF020
SST39LF/VF040
SST39LF/VF512
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS VSS VSS VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Standard Pinout
Top View
Die Up
SST39LF/VF020
SST39LF/VF020 SST39LF/VF040
Symbol Pin Name Functions
AMS-A0
DQ7-DQ0
CE#
OE#
WE#
VDD
VSS
NC
To provide memory addresses. During Sector-Erase AMS-A12 address lines will
select the sector. During Block-Erase AMS-A16 address lines will select the block.
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage :
Unconnected pins
Address Inputs
Data Input/output
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
3.0-3.6V for SST39LF512/010/020/040
2.7-3.6V for SST39VF512/010/020/040
KA9259HD
5-Channel Motor Drive IC
GGDESCRIPTION
GGFEATURE
GGPIN ASSIGNMENTS
The KA9259D is a monolithic integrated circuit, and suitable for 5-CH motor driver which drives focus actuator,
tracking actuator, sled motor, spindle motor and loading motor of compact disk player system.
. 4-CH Balanced Transformerless(BTL) Driver
. 1-CH (Forward/Reverse) DC Motor Driver With Speed Control Circuit
. Built-in TSD (Thermal Shutdown) Circuit
. Built-in 5V Regulator (With an External PNP Transistor)
. Built-in Mute Circuit
. Wide Operating Supply Voltage Range: 6V~13.2V
28-SSOPH-375
KA9259D
1 2 3 4 5 6 7 8 9 10 11 13 14
28 27 26 25 24 23 22
FIN
21 20 19 18 17 16 15
FIN
12
1
.
1
O
D
2
.
1
O
D
1
.
2
O
D
2
.
2
O
D
2
.
4
O
D
1
.
4
O
D
2
.
3
O
D
1
.
3
O
D
2
.
4
I
D
1
.
4
I
D
L
T
C
D
L
3
I
D
2
.
5
O
D
1
.
5
O
D
2
.
5
I
D
1
.
1
I
D
2
.
1
I
D
B
E
R
O
G
E
R
E
T
U
M
1
.
5
I
D
2
I
D
1
D
N
G
2
D
N
G
3
D
N
G
2
C
C
V
1
C
C
V
F
E
R
V
TEST
42
SPECIFICATIONS
43
GGPIN DESCRIPTION
Pin Number Pin Name I/O Pin Function Description
Channel 1 output 1
Channel 1 output 2
Channel 1 input 1
Channel 1 input 2 (Adjustable)
External transistor base drive output
Regulator output
Mute signal input
Ground 1
Channel 5 input 1 (Loading Motor)
Channel 2 input
Channel 2 output 1
Channel 2 output 2
Ground 2
Channel 5 input 2 (Loading Motor)
Channel 5 output 1 (Loading Motor)
Channel 5 output 2 (Loading Motor)
Channel 3 output 1
Channel 3 output 2
Channel 3 input
Channel 5 (Loading Motor) speed control input
Power supply voltage 1
Power supply voltage 2
Bias voltage input
Channel 4 input 1 (Adjustable)
Channel 4 input 2
Channel 3 output 1
Channel 3 output 2
Ground 3
DO1.1
DO1.2
DI1.1
DI1.2
REB
REO
MUTE
GND1
DI5.1
DI2
DO2.1
DO2.2
GND2
DI5.2
DO5.1
DO5.2
DO3.1
DO3.2
DI3
LD CTL
VCC1
VCC2
VREF
DI4.1
DI4.2
DO4.1
DO4.2
GND3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
O
O
I
I
O
O
I
-
I
I
O
O
-
I
O
O
O
O
I
I
-
-
I
I
I
O
O
-
Audio Channel
Frequency Response
T.H.D. (with A filter)
S/N(with A Filter)
Analog Output Level
Headphone Output Level
Quantization
Analog Output Terminal
Digital Output (TOS LINK/RCA)
Player Responds
Operation Temperature
Power Source
Power Consumption
Weight 6.2kg/13.7lb
Dimensions
* Specifications and design subject to change without notice for improvements.
18W(Standby: Less than 1W)
482(W)x88(H)x380(D)mm/19(W)x3.5(H)x14.9(D)in
SPDIF(IEC958)
CD-DA/MP3/WMA
-10C ~ +40C
100120VAC or 220240VAC; 50/60Hz
(Supplied AC mains transformer depends on country requirements)
6dB2dB
(load impedance 32 Ohm) 3.5dB2dB
24-bit
RCA-2CH/XLR-2CH/XLR MIX-1CH
2 Channels
20Hz~20kHz1dB
0.002% (Less than 0.02%)
100dB (Better than 90dB)
CD-610
TEST
ELECTRICAL PARTLIST
44 45
Ref. Part No. Description Value Ref. Part No. Description Value
C754 S35608212430 CE820P50/1608,820P 820P
C704 C714-715 S35611032530 CE0.01U50K/1608,0.01U 0.01U
X701 3938000880 10MHZ/CSTLS,10MHz 10MHz C728 C738
CN706 4428594508 08P/53014/2,53014-08P 53014-08P C740-741 C783
Q701 S20110499001 PNP/KTA1504S-Y/SOT23,KTA1504S-Y KTA1504S-Y C785
Q702-703 S20260403001 N/FDV303N/SOT23,FDV303N FDV303N C739 S35611532530 CE0.015U50K/1608,0.015U 0.015U
IC707 S21161034001 BA33FP/TO252-3,BA33FP BA33FP C711 C724 S35612222530 CE2200P50K/1608,2200P 2200P
IC709 S21161054001 BA33C25FP/TO252-5,BA33C25FP BA33C25FP C748-749 C751
IC706 S21211642901 MB95F108AW/LQFP64P,MB95F108AW MB95F108AW C778
IC703 S21213001501 MLC3300/TQFP100P,MLC3300 MLC3300 C755-758 S35612232530 CE0.022U50K/1608,0.022U 0.022U
IC702 S21213480701 S5L9290X/LQFP48P,S5L9290X S5L9290X C760-761
IC705 S21235328102 SST39VF020/TSOP,SST39VF020 SST39VF020 C763-765 C767
IC704 S21243540702 K4S641632H-TL75/TSOP54P K4S641632H-TL75 C770 C772 C803
IC701 S21271480701 S1L9226X/LQFP48P,S1L9226X S1L9226X C721 S35613332530 CE0.033U50K/1608,0.033U 0.033U
IC710 S21288280701 KA9259D/SSOPH28P,KA9259D KA9259D C712 C731 S35614722530 CE4700P50K/1608,4700P 4700P
D702-705 S22100500001 D/1N4148/SOT23,1N4148 1N4148 C716 S35616832530 CE0.068U50K/1608,0.068U 0.068U
FB701 S26001212029 BEAD/HB1M121JT/2012,HB-1M2012-121JT HB-1M2012-121JT X702 S39102999900 16.934MHZ/HC-49U/SMD,16.934MHz 16.934MHz
R731-734 R790 S30100007121 R0J/1608,0 0 CN705 S44443412603 03P/12505WR/1.25,12505WR-03P 12505WR-03P
R738-739 R751 S30100107121 R1J/1608,1 1 CN704 S44443412604 04P/12505WR/1.25,12505WR-04P 12505WR-04P
R757 R792 CN703 S44445520602 02P/20022WR/2,20022WR-02P 20022WR-02P
R701 S30101007121 R10J/1608,10 10 CN702 S44510410615 15P/FFCFPC553-1/1.0,FFCFPC553-15P FFCFPC553-15P
R796 S30101007231 R10J/2012,10 10 CN701 S44510410616 16P/FFCFPC553-1/1.0,FFCFPC553-16P FFCFPC553-16P
R713 R721 R781 S30101037121 R10KJ/1608,10K 10K SW701 S46680020001 PU/MPU12371MLB1,MPU12371MBL1 MPU12371MBL1
R775-776 R779
R794-795
R715 R799 S30101057121 R1MJ/1608,1M 1M
R735 S30101337121 R13KJ/1608,13K 13K
R711 S30101537121 R15KJ/1608,15K 15K D201-204 2058100996 D/1N4006,1N4006(4007) 1N4006(4007)
R704 R706 R708 S30101547121 R150KJ/1608,150K 150K JK202 2128008400 OPTO/TOTX177L,TOTX177L TOTX177L
R797 FB201-209 2648609900 H5B/BEAD,VALUE VALUE
R730 S30101837121 R18KJ/1608,18K 18K R301 3009103973 R10KJ/A,10K 10K
R716 S30102037121 R20KJ/1608,20K 20K X201 3938000840 11.3MHZ/CSA,11.2896MHz 11.2896MHz
R752-754 S30102217121 R220J/1608,220 220 AN102 4353978210 11P/LW-5267/2.5,ASS'Y-11P ASS'Y-11P
R760-761 R772 S30102227121 R2.2KJ/1608,2.2K 2.2K JK203-205 4408194210 XLR/F/5031-030/V,XLR/F XLR/F
R710 S30102237121 R22KJ/1608,22K 22K CN206 4428536316 16P/FMN-BTRK/2,FMN-BTRK-16P FMN-BTRK-16P
R707 R709 R712 S30102247121 R220KJ/1608,220K 220K CN905 4428589420 20P/ZIF8370,ZIF8370-20P ZIF8370-20P
R793 CN205 4428594509 09P/53014/2,53014-09P 53014-09P
R729 S30102437121 R24KJ/1608,24K 24K JK206 4438095310 RCA/JK44N/02H/4438095310,RCA02P RCA02P
R756 S30102717121 R270J/1608,270 270 JK201 4438095510 RCA/JC27HN/01H/4438095510,RCA01P RCA01P
R723-724 S30102747121 R270KJ/1608,270K 270K JK207 4438189610 DS09P/M/4438189610,D-SUB09P D-SUB09P
R758-759 S30102797231 R2.7J/2012,2.7 2.7 RLY201-204 5528006900 12V/DPDT1A/S2L1/2,VALUE VALUE
R705 S30103037121 R30KJ/1608,30K 30K Q201 2008606111-T PNP/KRA107M,KRA107M KRA107M
R717 S30103327121 R3.3KJ/1608,3.3K 3.3K C209 C211 3409210071-T EC10U50/SGT,10/50 10/50
R719 S30103927121 R3.9KJ/1608,3.9K 3.9K C213-215 C238
R740-743 S30104707121 R47J/1608,47 47 C247 C258
R745-750 C291-293
R755 R764-771 C305-306
R773-774 C201 3409210141-T EC100U25/SGT,100/25 100/25
R782-788 R791 C285 C287-290 3409210971-T EC1U50/SGT,1/50 1/50
R720 R778 R780 S30104727121 R4.7KJ/1608,4.7K 4.7K C242 C244 3409222071-T EC22U50/SGT,22/50 22/50
R789 C256-257 C260
R702 R714 S30104737121 R47KJ/1608,47K 47K C265 C299-300
R703 R725-726 S30106837121 R68KJ/1608,68K 68K C202 C204 C223 3409247041-T EC47U25/SGT,47/25 47/25
R727 S30108207121 R82J/1608,82 82 C226 C234 C237
R718 S30108227121 R8.2KJ/1608,8.2K 8.2K C249-250 C261
C717 C787 C798 S34121000422 EC10U16/RC,10/16 10/16 C263 C275 C282
C727 C784 C786 S34121010242 EC100U6.3/RC,100/6.3 100/6.3 C297-298
C800 C208 C312-313 3509104530-T CE0.1U50Z/Y5V/T,0.1U 0.1U
C742 C780 S34122210442 EC220U16/RC,220/16 220/16 C229-231 C233 3609182120-T MA0.0018U100T,0.0018/100(M) 0.0018/100(M)
C703 C734 C736 S34124700232 EC47U6.3/RC,47/6.3 47/6.3 C216 C221-222 3609562120-T MA0.0056U100T,0.0056/100(M) 0.0056/100(M)
C744 C753 C227
C759 C762 C766 C228 C232 3609822120-T MA0.0082U100T,0.0082/100(M) 0.0082/100(M)
C768-769 C771 C280 3639104111-T MA0.1U50/ECQVT,0.1/50(M) 0.1/50(M)
C729 S34124790422 EC4.7U16/RC,4.7/16 4.7/16 Q202-207 S20160405003 NPN/KRC107S/SOT23,KRC107S KRC107S
C730 C773 C796 S35101024321 CE1000P50/1608,1000P 1000P Q208 S2040000100 PNP/KRA107M,KRA107S KRA107S
C701 C705-707 S35101045321 CE0.1U50Z/1608,0.1U 0.1U Q209-210 S20560405003 NPN/KTD1304/SOT23,KTD1304 KTD1304
C709 C713 IC205-210 IC212 S21101083204 NJM5532M/DMP08P/2,NJM5532M NJM5532M
C722-723 IC201 S21161034001 BA33FP/TO252-3,BA33FP BA33FP
C725-726 C735 IC202 S21221242701 AK4117/VSOP24P,AK4117 AK4117
C737 C743 IC211 S21252145405 74HC04/SOP14P/2,74HC04 74HC04
C745-747 C750 IC204 S21275160001 MAX232/SOP16P,MAX232CWE MAX232CWE
C752 C777 C779 IC203 S21282287601 PCM1738/SSOP28P,PCM1738 PCM1738
C781-782 C792 D205-208 S22300502001 D/BAT54S/SOT23,BAT54S BAT54S
C797 C799 L201-202 S26104R73062 4.7UH/3225/ELJFA,4.7 uH 4.7 uH
C801-802 R202 R209 S30100007231 R0J/2012,0 0
C774-775 S35102004321 CE20P50/1608,20P 20P R213-215 R249
C719-720 S35104744331 CE0.47U50Z/2012,0.47U 0.47U R316-317 S30101017231 R100J/2012,100 100
C702 C793-794 S35601012430 CE100P50/1608,100P 100P R201 R207-208 S30101027231 R1KJ/2012,1K 1K
C732 S35602092430 CE2P50/1608,2P 2P R238 R241 R243
C795 S35602202430 CE22P50/1608,22P 22P R267-268
C790-791 S35603312430 CE330P50/1608,330P 330P R288-289
C708 S35603912430 CE390P50/1608,390P 390P R242 R244 S30101037231 R10KJ/2012,10K 10K
CD-610 CD B'D
CD-610 MAIN B'D
CD-610 REAR B'D
Ref. Part No. Description Value Ref. Part No. Description Value
R269-270 R960-961
R275-278 R287 R970-981
R290-293 R304 R933 R958 S30104717231 R470J/2012,470 470
R286 S30101047231 R100KJ/2012,100K 100K R921 R930 R935 S30104727231 R4.7KJ/2012,4.7K 4.7K
R247-248 S30101137231 R11KJ/2012,11K 11K R955
R203 R240 R245 S30101237231 R12KJ/2012,12K 12K R922 R936 S30108227231 R8.2KJ/2012,8.2K 8.2K
R217 S30101337231 R13KJ/1608,13K 13K C903 S34211070350 TT100U10/C,100/10 100/10
R205-206 S30102227231 R2.2KJ/2012,2.2K 2.2K C910 S34211090633 TT1U25/A,1/25 01 25
R204 R246 S30102237231 R22KJ/2012,22K 22K C909 S35101024331 CE1000P50/2012,1000P 1000P
R263-264 C904-905 S35101045331 CE0.1U50Z/2012,0.1U 0.1U
R261-262 S30102727231 R2.7KJ/2012,2.7K 2.7K C907-908
R250 S30103307231 R33J/2012,33 33 C913-914 C920
R210-212 S30103317231 R330J/2012,330 330 C906 S35611032540 CE0.01U50K/2012,0.01U 0.01U
R216 R235-237 S30104707231 R47J/2012,47 47
R283-285
R294-300 D501 2058100996 D/1N4006,1N4006(4007) 1N4006(4007)
R234 R239 S30104717231 R470J/2012,470 470 D502-503 2058304100 D/1N4148,1N4148 1N4148
R257-260 IC501 2118010932 NJM4556AD/2,4556AD 4556AD
R271-272 R279 VR501 3228065700 503B/09/RK097122T,50KB*2 50KB*2
R281 R305 R315 AN205 4353978710 09P/53014/2,ASS'Y-9P ASS'Y-9P
R282 S30105607231 R56J/2012,56 56 JK501 4438097310 PHN04P/4438097310,PHONE04P PHONE04P
R218-233 S30106217330 R620J1/8W/2012,620 1/8W 620 1/8W RLY501 5528006900 12V/DPDT1A/S2L1/2,VALUE VALUE
R937 S30106807231 R68J/2012,68 68 C501 C504 3409247041-T EC47U25/SGT,47/25 47/25
R273-274 S30124305230 R43KF/2012,43K 1% 43K 1% Q501 S20160405003 NPN/KRC107S/SOT23,KRC107S KRC107S
C283 C316-317 S35101024331 CE0.001U50J/2012,0.001U 0.001U L501-502 S26102R23025 2.2UH/FIB222KJT/2012,2.2 uH 2.2 uH
C203 C205 C210 S35101045331 CE0.1U50Z/2012,0.1U 0.1U R510 R512 S30101027231 R1KJ/2012,1K 1K
C212 C218-220 R503 R505 S30102227231 R2.2KJ/2012,2.2K 2.2K
C224-225 R511 R513 S30102247231 R220KJ/2012,220K 220K
C235-236 C241 R504 R506 S30103307231 R33J/2012,33 33
C243 C246 R501-502 S30106227231 R6.2KJ1/8W/2012,6.2K 1/8W 6.2K 1/8W
C253-254 C262 C503 C506 S35101045331 CE0.1U50Z/2012,0.1U 0.1U
C264 C281 C284 C502 C505 S35608212440 CE820P50/2012,820P 820P
C286 C295-296 C507-510
C310
C267-273 C294 S35601012440 CE100P50/2012,100P 100P
C301-302 C304 CN906 4428594505 05P/53014/2,53014-05P 53014-05P
C206-207 S35601502440 CE15P50/2012,15P 15P SW902-909 4628985710 TC/THVV501BAA,THVV501BAA THVV501BAA
C252 C255 C279 S35601802440 CE18P50/2012,18P 18P SW914-915
C274 S35612232540 CE0.022U50K/2012,0.022U 0.022U R901 R909 S30101027231 R1KJ/2012,1K 1K
R907 R915 S30101537231 R15KJ/2012,15K 15K
R903 R911 S30102227231 R2.2KJ/2012,2.2K 2.2K
D901 2058304100 D/1N4148,1N4148 1N4148 R908 S30102737231 R27KJ/2012,27K 27K
ZD901 2058502024 ZD/UZ2.4BM,2.4BM 2.4BM R904 R912 S30103327231 R3.3KJ/2012,3.3K 3.3K
VFD901 2328130992 LC/9-ST-37GINK,9-ST-37GINK 9-ST-37GINK R905 R913 S30104727231 R4.7KJ/2012,4.7K 4.7K
R916 3009229973 R2.2J/A,2.2 2.2 R906 R914 S30108227231 R8.2KJ/2012,8.2K 8.2K
X901 3938000880 10MHZ/CSTLS,10MHz 10MHz
LUG901 4350001200 01P/CNT,ASS'Y-01P ASS'Y-01P
AN906 4353978410 05P/AN/2,ASS'Y-05P ASS'Y-05P RMC901 2438200950 37.9KHZ/RPM7138,RPM7138-H4 RPM7138-H4
AN101 4353978610 10P/AN/2,ASS'Y-10P ASS'Y-10P CN902 4428594504 04P/53014/2,53014-04P 53014-04P
AN902 4353978810 04P/AN/2,ASS'Y-04P ASS'Y-04P SW901 4628985710 TC/THVV501BAA,THVV501BAA THVV501BAA
CN901 4428589420 20P/ZIF8370/1.25,ZIF8370-20P ZIF8370-20P C902 3409210071-T EC10U50M/SG/T,10/50 10/50
CN903 4428594508 08P/53014/2,53014-08P 53014-08P R928 S30101017231 R100J/2012,100 100
SW913 4628985710 TC/THVV501BAA,THVV501BAA THVV501BAA C901 S35101024331 CE1000P50/2012,1000P 1000P
SW917-932
BZ901 5540000050 BUZZER/PKM22EPP-40,CAP-1205SL(9.5) CAP-1205SL(9.5)
C915 3409222033-T EC22U16/SET,22/16 22/16
C911 C921 3409247033-T EC47U16M/SE/T,47/16 47/16
Q903 S20110499001 PNP/KTA1504S-Y/SOT23,KTA1504S-Y KTA1504S-Y
Q902 S20160405003 NPN/KRC107S/SOT23,KRC107S KRC107S
Q901 S20160499001 NPN/KTC3875S-Y/SOT23,KTC3875S-Y KTC3875S-Y
IC903 S21103030502 KIA7045AF/SOT89,KIA7039AF KIA7039AF
IC901 S21211642902 MB95F108AW/LQFP64P,MB95F108AHW MB95F108AHW
IC902 S21233089902 24LC02B/SOP08P,24LC02B 24LC02B
D902 S22300502001 D/BAT54S/SOT23,BAT54S BAT54S
FB901 S26001212029 2200PF/FIB222JT/2012,HB-1M2012-121JT HB-1M2012-121JT
R917-918 R954 S30101027231 R1KJ/2012,1K 1K
R910 R925-927 S30101037231 R10KJ/2012,10K 10K
R939 R948-950
R957 R966-967
R991
R923 R944 S30101537231 R15KJ/2012,15K 15K
R983-990 S30102217231 R220J/2012,220 220
R919 R929 R932 S30102227231 R2.2KJ/2012,2.2K 2.2K
R968 R998-999
R956 S30102297230 R2.2J/2012,2.2 2.2
R924 R945 S30102737231 R27KJ/2012,27K 27K
R920 R934 S30103327231 R3.3KJ/2012,3.3K 3.3K
R992-993
R969 S30103337231 R33KJ/2012,33K 33K
R902 R931 S30104707231 R47J/2012,47 47
R941-943
R951-953
CD-610 REMOTE SENSE B'D
CD-610 FRONT B'D
CD-610 HEADPHONE B'D
CD-610 FUNCTION KEY B'D
TOP AND BOTTOM VIEW OF P.C.BOARD
46 47
48 49
BOTTOM
CD MAIN BD 4002900300
WIRING DIAGRAM
50 51
REAR BD
HEAD
PHONE
BD
SMPS
FUNCTION BD
CD MECH
FRONT BD
Remote
Sense
BD
CN905
CN206 CN205
AN205
CP702
CN906
AN102
CN1
CN102
CN902
AN906
AN902
CN901
AN101
CN101
INPUT
BLOCK DIAGRAM
52 53
SCHEMATIC DIAGRAM
54 55
CD PART
56 57
FRONT PART
58 59
REAR PART
EXPLODED VIEW OF CABINET & CHASSIS / MECANICAL PARTLIST
60 61

CD-610 Service Manual

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CD-610 Service Manual

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SERVICE

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