Chapitre III

Circuits arithmétiques

11-18 octobre - 01 novembre 2023

Pr. Younes JABRANE 2ème année CP 2023/2024 1 / 31

Addition et soustraction
En arithmétique binaire, il faut non seulement
additionner le chiffre de signification équivalente des deux
nombres à additionner
mais également le bit de retenue (si présent) du chiffre significatif
inférieur
Cette opération peut être réalisée en deux étapes :
additionnez d’abord les deux bits correspondant au chiffre 2k
puis ajoutez le résultat au report du bit 2k−1
Lorsque vous soustrayez plusieurs colonnes de chiffres binaires
vous devez tenir compte de l’emprunt et devez également garder
une trace des différences et des emprunts
La forme générale dePl’addition binaire dans la colonne LSB peut
s’écrire : A0 + B0 = 0 +Cout
P
La sortie de la somme est donnée par le symbole , et le report
est donné par Cout
Pr. Younes JABRANE 2ème année CP 2023/2024 2 / 31
 Addition et soustraction
INTRODUCTION
INTRODUCTION truth
truthtable
tableininTable
Table10.1
10.1shows thefour
showsthe fourpossible
possiblecondi-
condi-
AArange La table de vérité quitions
rangeofofdevices
devicesisisavailable
availablefor
when
tions whenadding
suit addingtwo
montre
forperforming
performingbinarytwobinary
binary
binary
digits.
les
digits.4 conditions possibles lors de
arithmetic
arithmeticfunctions.
functions.Their Their usefulness
usefulness and
Table 10.1 Truth
Table10.1 and cost-
TruthTable
Tablefor
cost-forAddition
Additionofoftwo
twoBinary
Binary
effectiveness
he
thelow
lowcost
costand
l’addition de deux chiffres binaires
effectivenessisisthrown
throwninto
andavailability
intosome
somedoubt
doubtthese
thesedays
themicroprocessor.
availabilityofofthe
daysdue
Digits
microprocessor.They
duetoto
Digits in the LeastSignificant
in the Least
They
SignificantColumn
Column
will A0A B0B S0S Cout
willalways
alwayshave
havea aplace
placewhere
wherethe thearithmetic
arithmeticrequire-
require- 0 0 0 C out
ment verysimple
mentisisvery simpleororbasic,
basic,ororwhere
wherea asimple
simplearithmetic
arithmetic 00 00 00 00
procedure
procedureisisa asmall
smallpart
partofofa amuch
muchmoremorecomplex
complexfunc- func- 00 11 11 00
ion
tionbest
bestperformed
performedbybydiscrete
discretehardware.
hardware.Complicated
Complicated 11 00 11 00
arithmetic 11 11 00 11
arithmeticcalls
callsforforcomplicated
complicatedcircuits,
circuits,and
andititisisininthese
these
circumstances
circumstancesthat thatthethedesigner
designershould
shouldreally
reallyconsider
consider
whether IfIfa acarry
carryout
outisisproduced,
produced,ititmust
mustbebeadded
addedtotothe
whethera amicroprocessor
microprocessormight mightbebea abetter
bettersolution.
solution. the
ADDITION
ADDITIONAND
Si un report est produit,
ANDSUBTRACTION
SUBTRACTION Figure
il doit
next-more-significant
next-more-significant
Figure10.1
10.1shows
showsthis
être
columnajout
column
thisoperation
operationand
andtruth
étable.
asasa a carry-in
carry-inàIn(CIn(Cla
truthtable.
).).
the
the
colonne in
in

truth table, the C term comes from the value of

nInbinary
binaryarithmetic
equivalent
la plus significative suivante
arithmeticwe wemust
equivalent significanceofofthe
significance
mustnot notonly
onlyadd
CC from
thetwo
addthe
fromthe
twonumbers
en
thedigit
the previous
tant
digitofof
previousaddition.
numberstotobebe
que
truth table, the C term comes from the value of
addition.Now,
out
out Now,with
C inthree
with
in
three
in

possible inputs
inputsthere
thereare
areeight
eightcombinations
combinationsofofoutputs
summed
summedbut butalso thecarry
alsothe carrybitbit(in(incase
caseititisispresent)
La table de vérité de(2possible present)ofof est : outputs
(2cette op ération 3
he ==8). 3
thenext
nextlower
lowersignificant
significantdigit.
digit.This
Thisoperation
operationmay
8). maybebe
carried
carriedoutoutinintwotwo steps: first add the two bits corre-
k steps: first add the two bits corre-
sponding to the
sponding to the 2 k–12 kdigit, and then add the resultant to
digit, and then add the resultant to
he
thecarry
carryfromfromthe the2 2k–1bit.
bit.When
Whenyou yousubtract
subtractseveral
several
columns A1 B1 Cin S1 Cout
columnsofofbinarybinarydigits,
digits,youyoumustmusttake
takeintointoaccount
account CC
in
in
CCin
in
A1 B1 Cin S1 Cout
he
theborrowing
borrowingand andshould
shouldalsoalsokeep
keeptrack
trackofofthe thediffer-
differ- AA AA 0 0 0 0 0
1 0 0 0 0 0 0
ences
encesandandborrows.
borrows. ++ BB1
1
BB0
0 0
0
0
0
1
0
1
0
1
1
1
1
0
0
0
10.1 1 0 0 1 0 1 0
10.1 Explain the general form of binary additioninin
Explain the general form of binary addition
SS
2 SS1 SS0
0
0
1
1
1
1
0
0
1
1
the
theleast
leastsignificant
significantand andmoremoresignificant
significant 2 1 0 1 0 0 1 0
++ ++ 1 0 0 1 0
columns.
columns. 1
1
0
0
1
1
0
0
1
1
CCout CCout 1 1 0 0 1
Solution: out out 1 1 0 0 1
Solution: 1
1
1
1
1
1
1
1
1
1
Thegeneral
The generalform formofofbinary
binaryaddition
additionininthetheleast
leastsignifi-
signifi-
cant
cantcolumn
columncan canbebewritten
writtenas: as:
AA0 + +BB0 = =SS0 + +CC out 10.1
10.1
0 0 0 out
The
Thesum
called
sumoutput
sigma, Le terme C provient
outputisisgiven
and the
givenbybythe
carry-out
Fig.de
Fig. 10.1 la
10.1
thesummation
is given
called sigma, and the carry-out is given by Cout. The
valeur
Addition
in
Requires
by
ininthe
summationsymbol
Addition deSignificant
theMore
symbol(S)
More
IncludingCC with
RequiresIncluding
C out . The
(S) CoutColumns
Significant
withAA ++BB
de l’addition précédente
Columns
in 1 1
in 1 1

Donc avec 3 entrées possibles, il y a 8 combinaisons de sorties

Pr. Younes JABRANE 2ème année CP 2023/2024 3 / 31
 Arithmetic Circuits 213
in the least significant and more significant col- 10.5 What is the most widely used method of repre-
Inumns.
order to perform binary addition, we represent all Tosenting
subtractbinary
0100 numbers
– 0001, Aand performing arith-
0 must borrow from A1;
Solution:
binary numbers in groups of 8 or 16, because that is metic in computer systems?
but A is zero. Therefore, A must first borrow from A
Addition et soustraction The
the general
standardform
nificant
puters today.
usedoffor
binary subtraction
arithmetic
column can be written as:
in the
in most least com-
digital sig-
1
Solution:
1
making A2 a 0. Now A1 is a 2. A0 borrows from A1
The
makingmostA1widely
a 1 andusedA0 amethod
2. Nowofwerepresenting
can subtractbinary
2

to get
A0 – B0 the
10.2 Explain = R0general
+ Bout form of binary subtraction 10.2 0011 (3 10and
numbers ). performing arithmetic in computer sys-
The difference, or significant
in the least remainder,and from the significant
more subtractioncol-
is tems is by using the two’s-complement
10.5 What is the most widely used method of repre- method. With
R0, andumns.
if a borrow is required, Bout is 1. The truth table this method
senting both positive
binary and negative
numbers numbers can
and performing be
arith-
La forme générale de la soustraction binaire dans la colonne LSB
inSolution:
Table 10.2 shows the four possible conditions when
subtracting
represented
meticusing the samesystems?
in computer
tion is greatly simplified.
format, and binary subtrac-
The generaltwo binary
form digits.subtraction in the least sig-
of binary Solution:
peut s’écrire : A0 − B0Table
=10.2
nificant R0Truth+
column can beB
A –B =R +B
written as:
out
Table for Subtraction of Two Binary
10.2
TheMost
numbers.
computer
most
numbers Inand
widely systems
used method
an performing
are based on 8-bit or 16-bit
of representing
the total number
8-bit system,arithmetic
binary
of differ-
in computer sys-
0 0 0
Digits in the Least Significant Column out
ent combinations is 256 (28); in a 16-bit
is by usingofthebitstwo’s-complement system
La différence, ou le reste, de
The difference,
A0
or la soustraction
remainder,
B0
from the subtraction is est R , et si un
R0
R , and if a borrow is required, B is 1. The truth table
0
Bout 0out
tems
the number is 65,536 (2 16
).
this method both positive and negative numbers can be
method. With
To be ableusing
represented to represent
the same bothformat,positive and negative
and binary subtrac-
in Table 10.2 shows the four possible conditions when
emprunt est nécessaire, Bout
subtracting
0
0 estdigits.1
two binary
0
1
0
1
0
1
Borrow required
because A0 < B0
numbers,
mostMost
the simplified.
tion is greatly
significant
two’s complement format uses the
(MSB) ofare
bit systems thebased
8-or 16-bit number to
1 0 1 0 computer on 8-bit or 16-bit
La table de vérité de cette
Table 10.2op 1
If a borrow is
ération
Truth
Digits
1
in the ALeast
required, must
estof Two
Table for Subtraction 0
Significant
: Binary
Column
borrow from A in
0 signify
numbers.
The MSB
whether
is
the number
In an 8-bit
therefore
system, the
called
is positive
the
or negative.
total number
sign
ent combinations of bits is 256 (2 ); in a 16-bit system
of differ-
8 bit and is defined
0 1 asthe0 number
for positive numbers
the next
A0 more-significant
B0 R0 column.
Bout When A0 borrows is 65,536 (216and
). 1 for negative numbers.
SignedTo betwo’s
able tocomplement
represent both numbers areand
positive shown in
negative
from its left, A0 increases by 2 (just as in decimal sub-
0 0 0 0 Borrow required Fig. 10.3. the two’s complement format uses the
numbers,
traction
0
where1 the number
1
increases
1
by 10).
because A < B 0 0
10.3 1Elaborate
0 on binary
1 subtraction
0 in the second most significant bit (MSB) of the 8-or 16-bit number to
D7 D6 D5 D4 D3 D2 D1 D0
1and more
1 significant
0 columns.
0 signify whether the number is positive or negative.
The MSB is therefore called the sign bit and is defined
Solution:
If a borrow is required, A0 must borrow from A1 in Sign bit
as 0 for positive numbers and 1 for negative numbers.
The
the second column and allcolumn.
next more-significant more significant
When A0 columns
borrows (a)
Si un emprunt est nécessaire, A0 doit emprunter de A1 dans la
first
fromhave
subtracting
to determine
its left,
traction where
if Aby
A0 increases
theTherefore,
A – B.
was borrowed-from
2 (just as in decimal
they havebythree
number increases
before
sub-
10). input con-
Signed two’s complement numbers are shown in
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Fig. 10.3.

prochaine colonne la plus significative

ditions,
tions, as
for a totalonofbinary
10.3 Elaborate
andillustrated
eight different
subtraction
in Fig. 10.2.
more significant columns.
possible combina-
in the second D7 DSign bit
6 D5 D4 D3 D2 D1 D0
(b)

Solution: A1 B1 Bin R1 Bout Sign bit

Fig. 10.3 Two’s Complement Numbers: (a) 8-bit Num-
The second column and all more significant columns (a)
Bin Bin 0 0 0 0 0 Borrow (Bout) ber; (b) 16-bit Number.
first have
A1
toA determine0 if A 0
was
1
borrowed-from
1 1
before D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 required
subtracting
– B1 A
B0 – B. Therefore,
0 1 they
0 have
1 1three input con- The range of positive numbers in an 8-bit system is
R1 for Ra0 total of eight
ditions, 0 1 different
1 0 possible
1 combina- 0000 0000 to 0111 Sign 1111bit (0 to 127). The range of
tions, +as illustrated
+ in 1Fig.010.2.
0 1 0 negative numbers in an 8-bit (b) system is 1111 1111 to
Bout 1
Bout 0 1 0 0
1 1 0 0 0
1000 0000 (–1 to –128). In general, the maximum
A B B R B
1 1 1 1 1 in 1 1 1 out Fig. 10.3
positive Two’s
number is equal to (2N–1 Numbers:
Complement (a) maximum
– 1), and the 8-bit Num-
N–1
Bin Bin 0 0 0 0 0 Borrow (Bout) negative number ber; (b) 16-bit
is –(2 ) Number.
where N is the number of
A1 A0 0 0 1 1 1 required bits in the number including the sign bit.
B1 Subtraction
Fig.– 10.2 B0 in
0 the
1 More
0 Significant
1 1 Columns.
because Bin The range of positive numbers in an 8-bit system is
Lorsque A0 emprunte à sa gauche, A0 augmente de 2
R1
10.4 Subtract
+
R0
+
0
4 – 1 (0100
1 1
1 2 0– 0001
0
0 21). 0
1 needs to
borrow from
10.6
0000Convert
Solution:
0000 to350111
10 to 1111
two’s (0complement.
to 127). The range of
negative numbers in an 8-bit system is 1111 1111 to
Bout Bout
Solution: 1 0 1 0 0 A1, which is If1000
the decimal
0000 (–1 number is positive,
to –128). the two’s
In general, comple-
the maximum
comme en soustraction4 décimale
A A A A
où0 le nombre augmente de 10
1 0 0
1
1
1
1
0
1
0
1
0
1
1
0 2 Æ2
zero.
ment number
positive is the
number to (2N–1equivalent
true binary
is equal of maximum
– 1), and the the deci-
10 3 2 1 0 mal number.
negative number is –(2N–1) where N is the number of
Pr. Younes JABRANE –110 –B3 B2 B1 B0 0 0 0 1 2èmebits ann
in theée CP
number 2023/2024
Trueincluding
binary = the
0010 bit. 4 / 31
0011
sign
Additionneur et soustracteur

Un demi-additionneur est un circuit additionneur de base

il ne peut pas effectuer d’addition de nombres de plus de 1 bit
Il n’a pas d’entrée pour les reports des bits précédents
Les additionneurs complets pour les nombres binaires doivent
recevoir des retenues
ainsi que 2 valeurs binaires (addend et augend) comme entrées
Une entrée de report C1 est la sortie de report C0 de l’addition
précédente
Lors d’une soustraction il faut d’abord (chapitre 1)
prendre le complément à 2 de la valeur à soustraire
Ensuite, nous ajoutons le résultat pour obtenir la réponse
Avec un inverseur contrôlé, on peut produire le complément à 2

Pr. Younes JABRANE 2ème année CP 2023/2024 5 / 31

 1001 shows the addition of two 2-bit numbers. This could
10010 (invalid because of carry) easily be expanded to cover 4-8-or 16-bit addition.
Additionneur et soustracteur
carry
Notice that addition in the least significant bit column
requires analysing only two inputs (Ao plus Bo) to
0110 determine the sum (So) and carry (Cout). But any more
11000 = 0001 1000BCD 216 (2 12000
significant columns column andProblems
Solved above) require theElectronics
in Digital
=
Toutes
1810
les opérations arithmétiques peuvent être mises en oeuvre
inclusion of a third input, which is the carry (Cin) from
the columnOR to its right.
an For
ANDexample, the carry-out out)
circuit is(Ccalled
à l’aide
t the following decimald’additionneurs
numbers to formés des portes logiques de base
of the 20 column
and gate. That
becomesinthe carry-in
A
the 21
a half-adder 1

nd add them. Convert the result back

and is shown Fig. 10.5. (C B ) toexclusive-OR
If inthe function 1

mal to checkla table de vérité détermine les conditions d’entrée produisant

column. Figure 10.4(c) shows the inclusion of a third
your answer. in Fig. 10.5 is implemented using an AND-NOR-NOR
A
input for the truth table of the more significant column 1
+ 63 chaque combinaison de bits
(b) 78 + 69 additions. configuration, we can tap off the AND gate for the carry,
de sortie de la somme et la retenue C in
as shown in Fig. 10.6. The AND-NOR-NOR configuration
is an Ex-OR. A combinational logic circuit used to add B1
0101 0010
two binary digits is known2 outputs
as a half adder. Cin
0110 0011 Cin Cin 2 inputs
64 8 64
4744 4744
8
1011 0101 A1 A0
216 2000 Solved Problems in Digital Electronics A0 A 0 B0 S0 Cout Fig. 10.8
+ B1 B0 S0 = A 0B0 + A0 B 0
0110 invalid BCD number S1 S0
B0 0 0 0 0
1 0001 0101 and an
=OR0001 gate.BCD
AND 0101
0001 That circuit is +called
+ a half-adder0 1 A1 1 0
and is shown in Fig. 10.5. If the exclusive-OR
Cout Cout function1 0 B1 1 0
=in Fig. 110.5
1 510
is implemented using an AND-NOR-NOR1 1 A 0 1 Cout = A0B0
1
0111 1000 configuration,
Both groupswe of can
4 BCDtap off the AND gate for the carry, Cin
A1
Cout = 1 for any Two
0110 1001 as bits
shownareininvalid
Fig. 10.6. The AND-NOR-NOR configuration Inputs HIGH B1
Fig.
(a) 10.5 Half-adder Circuit, using Ex- OR and AND
P B(b)
1110 0001 is an Ex-OR. A combinational logic circuit used to add
= A B + A B et C =A B 1

0 binary0digits
two 0 is known out
0 as0 a half adder. 0 Gates
3 inputs
0 for Addition
Cin
2 outputs
in the LSB Column.
carry 644 4A07444 8 644 74 48 Cin
0110 A0 A1 B1 Cin Fig.
S 1 10.8 Cout Carry-out
Cout =(CAout) Function of the Full-adder.
0B 0
S0 = A 0B0 + A0 B 0
1110 0111 B0
0 0 0 0 0
0110 0 0 1 1 0 S 0 = A 0B0 + A0AB10B1 Fig. 10.9
0 1 0 1 0
10100 0111 = 0001 0100 0111BCD Cout = A0B0
0 B10 1 0 1 combinat
Cout
1 0 0 11 0 A
= 1 4 710 B01 digits is k
Fig. 10.5 Half-adder Circuit, using Ex-1 OR and
0 AND1 1
Fig. 10.6 Alternative
Un circuit logique combinatoire utilisé pour additionner 2 chiffresHalf-adder Circuit Built from
Cin an
( A 1B1 + A1 B 1)
1 1 0 0
Gates for Addition in the LSB Column. AND-NOR-NOR 1 10.20 Ap
UBTRACTORS 1 1 1 1 1 Configuration.
Fi
binaires
s a basic adder circuit.ABy
0
estitappel
itself cannot é
demi-additionneur
(c) C S in 1
C
Pr. of
Younes Cout = A10.19
0B 0 With the help of a suitable
2ème sketch describe the 6 / 31 i
on of numbers more JABRANE
than 1 bit. It lacks année CP 2023/2024
 Additionneur Cet Csoustracteur
2 inputs 2 outputs
in in 64 8 64
4744 4744
8
A1 A0 A0 B0 S0 Cout
+ B1 B0
nvalid BCD number S1 S0
0 0 0 0
001 0001 0101BCD + + 0 1 1 0
Cout Cout 1 0 1 0
Décrivez le fonctionnement
1 1 510 d’un
1 additionneur
1 0 1 complet à partir de
oth groups of 4 BCD
sa table de vérité
its are invalid
(a) (b)

3 inputs 2 outputs
644 8 64
47444 4744
8
A1 B1 Cin S1 Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0001 0100 0111BCD
0 1 1 0 1
1 0 0 1 0
1 4 710 1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
uit. By itself it cannot (c)
ore than 1 bit. It lacks
ing bits. Full-adders Fig. 10.4 (a) Addition of Two 2-bit Binary numbers
carries as well as the (b) Truth Table for the LSB Addition; (c) Truth
arry input, CI, is the Table for the More Significant Column.
addition. A full-adder 10.18 With the help of a suitable sketch,2ème
describe
Pr. Younes JABRANE année CP 2023/2024 7 / 31
tion B1
NORAdditionneur
A1 et soustracteur
rry, Cin Cout = 1 for any Two
tion P Inputs HIGH
B1
add 1 = A1 ⊕ B1 ⊕ Cin
Cout = C
Ain1 B1 + Cin (A1 ⊕ B1 )
Schéma logique d’un additionneur complet
Fig. 10.8 Carry-out (Cout) Function of the Full-adder.

A1B1

Cout
A1
B1
AND Cin ( A 1B1 + A1 B 1)

Cin S1

B0 Fig. 10.9 Logic Diagram of a Full-adder.

Pr. Younes JABRANE 2ème année CP 2023/2024 8 / 31
 Cin = 1 Solution: S1 = 0
an use an even- of HIGH inputs
We can simplify the representation of half-adder and
bit, as shown in
Additionneur et soustracteur
(S1) Function of the Fig. full-adder
10.10 is Full-adder
Full-adder circuits for
Operation by Problem
drawing 10.20.
only a box with the input
and output lines, as shown in Fig. 10.11. When drawing
d from an Even-parity Generator.
10.21 Draw andmultibit explain adders, a block
the block diagram of a 4 isbitused to represent
diagram
ions produceNous pouvons
a HIGH ?simplifier
at Coutbinary
The adder.thela représentation
addition des circuits de :
in each column.
s1 HIGH number demi-additionneur
for odd whenever any two of the :
Solution:
erefore,
GH inputswe can take care of Cout
We can simplify the representation of half-adder and
an OR, as shown in Fig. 10.8. circuits by drawing only A B A B Ci
the Full-adder is full-adder HA
a box with theFA input
he full-adder circuit shown in Figs
and output lines, as shown in Fig. 10.11. When drawing
earity Generator.
combined to form the complete
multibit
C0 S
adders, a block diagram is used to represent
C0 S
wn in Fig. 10.9.
IGH at Cout? The In the figure the
the addition in each column.
ed using (a) (b)
r any twothe
ofsame logic as thatcomplet
additionneur
the in
R feeding an
take care of Cout Ex-OR). The C out Fig. 10.11 Block Diagram of (a) Half-adder; (b) Full-
in Cin ( A 1B1 + A1 B 1). A A B
B1 or10.8.
A1Fig. A B Ci
adder.
uit shown in Figs HA FA
rm the complete C0 S C0 S
In the figure the
e logic as that in (a) (b)
Exemple
x-OR). The Cout : Additionneur 4 bits
Fig. 10.11 Block Diagram of (a) Half-adder; (b) Full-
B 1). A
1B1 + A1Dans le cas d’un additionneur
adder. 4 bits la colonne 20 n’a besoin
que d’un demi-additionneur car il n’y aura pas de report
Chacune des colonnes les plus significatives nécessite un
additionneur complet
Pr. Younes JABRANE 2ème année CP 2023/2024 9 / 31
 Arithmetic Circuits 2
0
For example, in case of a 4-bit adder, the 2 column Note that the LSB half-adder has no carry-in
Additionneur etbecause
needs only a half-adder, soustracteur
there will be no carry- carry-out (Cout) of the LSB becomes the carry-in
in. Each of the more significant columns requires a to the next full-adder to its left. The carry out (C
full-adder as shown in Fig. 10.12. the MSB full-adder is actually the highest-order
output (S4).

(MSB) (LSB)
A3 B3 A 2 B2 A1 B1 A0 B0

4-Bit Addition: A B Ci A B Ci A B Ci A B
bit representations
A 3 A2 A1 A 0 FA FA FA HA
+ B 3 B2 B1 B 0
S4 S 3 S 2 S1 S 0 C0 S C0 S C0 S C0 S

S4 S3 S2 S1 S0

Fig. 10.12 Block Diagram of a 4-bit Binary Adder.

10.22 Explain the

Le report 7483,du
Cout 4-bit
LSBfull adder. Give ale
devient brief
report Cin du prochain
description of available MSI adder ICs. Fast-look-ahead
additionneur complet à sa gauche
Solution:
Carry

Medium-Scale-Integration (MSI) ICs are available with

Cout
four du MSB
full-adders de package.
in a single l’additionneur
PTable 10.3 listscomplet
the est la sortie
Most Significant
Binary Inputs
A4 de somme FA4
3 B4
d’ordre le plus élevé 4
most popular adder ICs. Each adder in the table contains 2 Ci
four full-adders, and all are functionally equivalent;
however their pin layouts differ (refer to data manual A3 Co
FA3
for pin layouts). Each of them will add two 4-bit binary B3 Ci
words plus one incoming carry. The binary sum appears
on
Pr. the
Younes outputs (S1 to S4) and the outgoing carry.
sumJABRANE 2èmeAann
2
ée CP 2023/2024 Co/ 31
10
 output (S4).

(LSB)
B2 Additionneur et soustracteur
A1 B1 A0 B0

B Ci A B Ci A B
Additionneur 4 bits : 7483
FA FA HA

S
le sch
C
éma
S
fonctionnel
0 C S
logique du 7483
0

les entrées LSB (20 ) sont sur les bornes A1 B1

S2 S1 S0
les MSB (23 ) sont sur les bornes A4 B4
rief
Fast-look-ahead
Cout
Carry

with Most Significant

A4
the Binary Inputs FA4 S4
B4
ains 23 Ci
ent;
nual A3 Co
FA3 S3
ary B3 Ci
ears
y. A2 Co
FA2 S2
B2 Ci

Least
Significant A1 Co
B1 FA1 S1
Binary Inputs Ci
arry 20
arry Cin 7483
arry

the YounesThe
Fig.Pr.10.13 7483, 4-Bit Full-adder.
JABRANE 2ème année CP 2023/2024 11 / 31
 Device Family Description
7483
Additionneur TTL
et soustracteur 4-Bit binary full-adder, fast carry
74HC283 CMOS 4-Bit binary full-adder, fast carry
4008 CMOS 4-Bit binary full-adder, fast carry
Le ”fast-look ahead carry” garantit que Cout de l’addition d’ordre <
Figure 10.13 shows the functional diagram and the
est fourni
logic dans le report
diagram for d’entr
the ée Cin de
7483. In l’addition d’ordre
the figure the> least
danssignificant
un laps de temps trèsinputs
binary court (2°) come into the A B
1 1
terminals, and the most significant (23) come into the
Additionneur
A4B44 terminals.
bits : 7483
En se basant sur l’architecture du 7483 4 bits
10.23 Show the external connections to two 4-bit
formez un additionneur
adder ICs 8tobits capable
form d’effectuer
an 8-bit adder l’addition
capable of
performing the following addition:
A8 A7 A6 A5 A4 A3 A2 A1
+ B8 B7 B6 B5 B4 B3 B2 B1
S9 S8 S7 S6 S5 S4 S3 S2 S1
Solution:
We can choose any of the IC adders listed in Table
10.3
Pr. Younes for our design. Let’s choose 74HC283,
JABRANE 2ème année CP which is12 / 31
2023/2024
 Figure 10.13 shows the functional diagram and the Fig
logic diagram for the 7483. In the figure the least
Additionneursignificant et soustracteur
binary inputs (2°) come into the A1 B 1 num
terminals, and the most significant (23) come into the eac
AdditionneurA4 B 4 4bits : 7483
terminals. the
En se 10.23
basantShow sur l’architecture
the external du 7483 4 bits to two 4-bit
connections
adder ICs to
formez un additionneur 8 bits capable d’effectuer form an 8-bit adderl’addition
capable of gro
performing the following addition: hal
A8 A7 A6 A5 A4 A3 A2 A1 not
+ B8 B7 B6 B5 B4 B3 B2 B1
S9 S8 S7 S6 S5 S4 S3 S2 S1 mu
218 2000 Solved Problems in Digital Electronics add
Solution:
We can choose any of the IC adders listed in Table
8 bit Inputs ens
10.3 for our design. Let’s choose 74HC283, which is ord
the Ahigh-speed
B 4 A B
4 3 A B CMOS
3 2 A B
2 1
version
1 A B ofA the
B
4 A4-bit
B
4 A adder
3B 3
(it has
2 2 1 1
hig
theC same7483logic symbol
out C in asC the 7483).
7483
out TheC two 8-bit in
so
S4 S3 S2 S1 S4 S3 S2 S1

S9
(High-Order) (Low-Order)

Sum Output

Pr.10.14
Fig. Younes8-Bit
JABRANE
Binary Adder using two 74HC283 ICs. 2ème année CP 2023/2024 13 / 31
Additionneur et soustracteur

Additionneur à base de portes NAND

Donnez le schéma logique d’un demi-additionneur ayant 2
entrèes A et B à base de portes NAND
Conclure le schéma logique d’un additionneur complet à base de
portes NAND

Pr. Younes JABRANE 2ème année CP 2023/2024 14 / 31

through all four of the low-order additions first. added are in two’s complement. Using one’s complement
10.24 Compare and contrast parallel and serial we not only have to test sign bit carries but also have to
Additionneur et soustracteur
adders. provide an end-around carry.
Solution: 10.25 With the help of a diagram describe a parallel-
Parallel adders require more circuits than serial adders adder using NAND gates.
butAdditionneur
allow all inputs to à
be base
presentedde portes
at once NAND
instead of Solution:
sequentially. The advantage of adding serially is that Parallel addition of two numbers can be carried out by
Donnez
just one adder le sch
is needed. émaadder
A parallel logique
consists d’un
of demi-additionneur
having ayant
a full-adder for each pair 2 that must be
of bits
full-adders connected in cascade, with the output carry added, except for the least significant bits, which require
entrèes A et B à base de portesonly
from one full-adder connected to the input carry of the
NANDa half adder. To add two 8-bit numbers in parallel
would require seven full adders plus a half adder.
next full-adder. The inputs to the serial adder are two
Conclure le schéma logique d’un additionneur In adder circuit usingcomplet
NAND gates, à Fig.
base deit is
10.15,
series of signals for the addend and the augend. The apparent that the construction of a parallel 8-bit adder
portes
output S is a series NAND
of signals for the sum. The carry would be quite complicated. N-bit adders are available
output C0 is delayed one clock pulse by a flip-flop as integrated circuits, but once constructed, a parallel
and fed back as a carry input C1. Basically, a serial adder is limited to the size of numbers it can handle.
adder adds magnitudes. We need a circuit to test the An 8-bit adder cannot handle 9-bit numbers.

HA
B
2 6
A B + AB S1
1 4 5 8 Sum
C D Sum
A 3 7
A ◊B A◊B A
A E C0
B C2
Ci
9 C0
B
C1
(a) (b)

Fig. 10.15
Demi-additionneur Additionneur complet
Adder Circuit using NAND Gates: (a) Half Adder (b) Full Adder.

10.26 Describe serial addition.

Pr. Younes JABRANE The two first bits are ann
2ème taken from the
ée CP serial outputs
2023/2024 15 / of
31
Additionneur et soustracteur

Le schéma logique décrit l’addition parallèle (//) de 2 nombres

Pour additionner 2 nombres de 8 bits en //
il faudrait 1 demi-additionneur plus 7 additionneurs complets

Problème
Dans un circuit additionneur utilisant des portes NAND
la construction d’un additionneur // 8 bits serait assez compliquée
Les additionneurs N bits sont sous forme de circuits intégrés
mais une fois construits un additionneur // est limité
à la taille des nombres qu’il peut gérer
Un additionneur 8 bits ne peut pas gérer les nombres de 9 bits

Pr. Younes JABRANE 2ème année CP 2023/2024 16 / 31

 in the first shift register. If required, a further number
may be loaded into the second shift register and added Karnaugh Map
to the sum.
Additionneur 10.27
et soustracteur
Implement a full-adder using Karnaugh maps.
From either method of sim
C o = AB + ACi + B
Solution: and S = ABCi + ABCi
Figure 10.17 shows an arrangement for adding two 4- These functions can be
bit binary numbers A3 A2 A1 A0 and B3 B2 B1 B0 to give shown in Fig. 10.20.
a 5-bit result X4 X3 X2 X1 X0, where A3, B3, and X4
TÀF represent the most significant bits, and A0, B0, and X0
represent the least significant bits. It is common practice
Implémenteztoun additionneur
number the bits of binarycomplet
numbers from à the
l’aide des
right and tables de
to start from 0. Thus an n-bit number has digits from 0
Karnaugh (figure)
to n-1. A
A
X4 X3 X2 X1 X0

Co S Co S Co S Co S B
B
Full Full Full Half
Adder Adder Adder Adder
Ci
Ci
(MSB) Ci Ci Ci (LSB)
A3 A2 A1 A0
(MSB) B3 B2 B1 B0 (LSB)

Fig. 10.17 An Arrangement to Add Two 4-bit Numbers.

It can be seen that each full-adder has three inputs

(A, B, and the carry input Ci) and two outputs (the sum Fig. 10.20 Implementation
S, and the carry output Co). The function of the full-
Pr. Younes JABRANE adder is described by the truth table of Fig. 10.18.
10.28 2023/2024
2ème année CP
n-bit
Describe a 17 / 31
bi
Additionneur et soustracteur

Additionneur BCD
Formez un additionneur BCD en utilisant les additionneurs
binaires 4 bits du circuit intégré 7483

Pr. Younes JABRANE 2ème année CP 2023/2024 18 / 31

 the sum of any group-of-four BCD exceeds 9, or when 0111
there is a carry-out, the number is invalid and must be + 0110
Additionneur et soustracteur
corrected by adding 6 to the invalid answer to get the 1101 invalid
correct BCD answer. (The valid range of BCD numbers + 0110 add 6 to correct
is 0000 to 1001). 1 0011
Additionneur BCD
For example, adding 0111BCD + 0110BCD (7 + 6) carry to next BCD digit
gives us an invalid result: The corrected answer is 0001 0011BCD, which equals
13.
BCD Input (A3A2A1A0 + B3B2B1B0)

A3 B3 A2 B2 A 1 B1 A0 B0

0 0 1 1 1 1 1 0
A4 B4 A3 B 3 A 2 B2 A1 B 1

Cout 7483 Cin Carry from Next Lower Digit,

Basic Adder
if any (Equals 0 if LSD)
S4 S3 S2 S1
1 1 0 1
23 22 21 20
0
1 1
Carry to next Higher Digit 1
(or use as MSD) 1
1
0

Error Correction 01 11 1 0 0 1
(add 6) A 4 B4 A3 B3 A2 B2 A 1 B1
Not 7483
Cout Correction Adder Cin
used
S4 S3 S2 S1
0 0 1 1

MSD = 1
Corrected LSD BCD Sum = 3

Fig. YounesBCD
Pr.10.23 Adder Illustrating the Addition 7 + 6 = 13 (0111 + 0110 = 0001
JABRANE 2ème0011
année ).
BCDCP 2023/2024 19 / 31
 01 11 1 0 0 1
(add 6) A 4 B4 A3 B3 A2 B2 A 1 B1
Not 7483
Additionneur et soustracteur
used
Cout

S4
Correction Adder
S3 S2 S1
Cin

0 0 1 1

La soustraction binaire peut être abordé d’une manière similaire à

MSD = 1
celle de l’additionCorrected LSD BCD Sum = 3
CD Adder Illustrating the Addition 7 + 6 = 13 (0111 + 0110 = 0001 0011BCD).
On peut construire un demi-soustracteur comme :
binary subtraction. Bo D

A B Bo D
binary subtraction can be tackled in a 0 0 0 0
o that of addition. We can construct a 0 1 1 1
as shown in Fig. 10.24(a), with a truth 1 0 0 1
Fig. 10.24(b). 1 1 0 0
now concerned with subtraction rather + –
e have difference (D) and borrow (B)
an sum and carry. It is also necessary
between the two inputs A and B to A B
h one is subtracted from which. In the (a) Block Diagram (b) Truth Table
the output isPuisque nous nous intéressons maintenant à la soustraction
equal to (A–B).
h table we can see that Fig. 10.24 A Half-subtractor.
B plutôt qu’à l’addition
10.11
+ AB = A ≈ B 10.32 Explain multiple-bit binary subtraction.
nous avons des sorties de différence D et d’emprunt B plutôt que
10.12
Solution:
n that D is identical to S for a half-
de S
he borrow output etthede
is not Cas the
same In order to perform multiple-bit subtraction we again
need to consider the effect of one stage on the next.
Il est également nécessaire de différencier les deux entrées A et B
pour déterminer laquelle est soustraite de l’autre (A − B dans
l’exemple)
Pr. Younes JABRANE 2ème année CP 2023/2024 20 / 31
 numbers to be used.

Additionneur et soustracteur Bo D3 D2 D1 D0

Bo Bo Bo Bo

Full
Table de vérité: nousSubtractor
avons: BFull0 = AB
Subtractor
Full
et D =
Subtractor
Full
AB + AB = A ⊕ B
Subtractor

D est identique à S pour un B demi-additionneur

B i B i B i i

mais que la sortie B0An’est pas 3 A la même

A 2
queA C 1 Half0
B B B B Subtracto
Afin d’effectuer une soustraction sur plusieurs bits
3 2 1

+
0

Fig. 10.25 A 4-bit Subtractor.

nous devons considérer l’effet d’une étape sur la suivante
Figure 10.26 shows the truth table for a full- A
un soustracteur 4 subtractor.
bits utilise 3 soustracteurs
The outputs can be represented complets
by the et 1 demi
Boolean expressions Fig. 10.27 Constructing
peut être mis en cascade Bo = ABpour
+ ABi +l’utilisation
BBi de grands 10.13 nombresHalf-subtracto
On peut construireandunDsoustracteur
= AB Bi + AB B i + Acomplet
B B i + ABBi comme 10.14 : a LOW INVERT produces
X7 . . . X0 = 0110 1
Bo D A B Bi Bo D But a HIGH INVERT resu
0 0 0 0 0 X7 . . . X0 = 1001 0
0 0 1 1 1 The controlled inverter i
0 1 0 1 1 helpful in subtraction. Du
Full 0 1 1 1 0 need to take the 2’s com
Subtractor 1 0 0 0 1 Then we can add the compl
1 0 1 0 0 the answer. With a control
+ –
1 1 0 0 0 the 1’s complement. There
1 1 1 1 1 complement.
A B Bi Figure 10.28 can b
(a) (b) complementing function. I
each of the data bits is co
Pr. Younes JABRANE 2ème année CP 2023/2024 21 / 31
Fig. 10.26 A Full-subtractor.
 22 / 31
on a besoin d’un élément pour complémenter appelé inverseur

2023/2024
Les circuits soustracteurs décrits fonctionnent comme prévu
ou construites à partir de deux demi-soustracteurs (à faire)
Ces fonctions peuvent être implémentées directement

mais souvent dans des circuits arithmétiques binaires

2ème année CP
ronics
g four full- D
Bo
allow larger
à condition que le résultat ne soit pas négatif

D0
Bo
Half
Full Subtractor
Subtractor
Additionneur et soustracteur

+ –
Bi
A0 Half
B0 Subtractor
+ –
for a full- A Bi
B
nted by the
Fig. 10.27 Constructing a Full-subtractor from Two
Half-subtractors.
10.13
10.14 a LOW INVERT produces

Pr. Younes JABRANE

X7 . . . X0 = 0110 1110
D But a HIGH INVERT results in

contrôlé
0 X7 . . . X0 = 1001 0001
1 The controlled inverter is important because it is very
1 helpful in subtraction. During a subtraction, we first
0 need to take the 2’s complement of the subtrahend.
1 Then we can add the complemented subtrahend to obtain
0 the answer. With a controlled inverter, we can produce
0 the 1’s complement. There is an easy way to get the 2’s
1 complement.
Figure 10.28 can be used to provide the
Additionneur et soustracteur

TÀF
Donnez le schéma logique d’un inverseur 8 bits avec une entrée
de contrôle à base de portes XOR

Pr. Younes JABRANE 2ème année CP 2023/2024 23 / 31

Additionneur et soustracteur
Arithmetic Circuits 223

D0
X0
D1
X1
D2
X2
D3
8-Bit X3 Controlled Output
D4 if C = 1, X0, 7 = D0, 7
Input X4
D5 if C = 0, X0, 7 = D0, 7
X5
D6
X6
D7
X7

Complementing
Control Signal (C)

Fig. 10.28 Controlled Inverter (Complementing) Circuit.

Lorsque All weinvert est à adder/subtractor

need for a combination 0, il transmetcircuit
is an input switch or signal to signify addition or
into 8 bitsThed’entr
the adders. other 8-bitée
binaryànumber
la sortie
comes in
on the B to B lines. If the B number is to be subtracted,
7 0
quand invert est à 1, il transmet le
subtraction so that we will know whether to form a
positive or a negative two’s-complement of the second
the complément à 1 position,
complementing switch will be in the up (1)
causing each bit in the number to be complemented
par exemple,
final result.
avec l’entrée est DC7 ...D
number. Then we will just use a binary adder to get the (one’s
0 a= 01101110
complement).
receives
At the same time, the low-order
1, which has the effect of adding a 1 to
in
Si invert est à 0 alors X7 ...X
To form negative two’s complement, we can use the
controlled inverter circuit of Fig. 10.28 and add
=the01101110
already complemented number B, making it a
1 to its0 negative two’s complement number.
Si invert est à 1 alors X7 ...X0 = 10010001
output.
10.34 Illustrate the subtraction 42 – 23 = 19 using
Now the 4008s perform a regular binary addition. If
the complementing switch is up, the number on the B
L’inverseur contrôlé est très utileinput
the CMOS 4008.
Solution:
enis soustraction
subtracted from the number on the A inputs. If
it is down, the sum is taken. The C of the MSB is out
où il faut
The 4008prendre
are CMOS 4-bitle compl
binary ément
adders. The
7
8-bit
number on the A inputs (A to A ) is brought directly
0
à 2
ignored. duresult
The soustractif
to 1000 0000 (–128).
can range from 0111 1111 (+127)

puis, nous ajoutons ce complément à 2 pour obtenir la réponse Complementing

Switch
A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 A0 B0
1 (Subtract)
Pr. Younes JABRANE0 0 0 0 1 0 0 1 1 0 0 1 1 1 0 1 2ème année CP 2023/2024 24 / 31
Additionneur et soustracteur

Avec un inverseur contrôlé, on produit le complément à 1

pour mettre en oeuvre cette conception
2 circuits intégrés XOR quad 7486 pourraient être utilisés
donnés par la figure précédente

puis on ajoute 1 pour obtenir le complément à 2

Pr. Younes JABRANE 2ème année CP 2023/2024 25 / 31

Additionneur et soustracteur

TÀF
Illustrez la soustraction 42 − 23 = 19 en utilisant 7483

Pr. Younes JABRANE 2ème année CP 2023/2024 26 / 31

al result. Cin receives a 1, which has the effect of adding a 1 to
To form negative two’s complement, we can use the the already complemented number B, making it a
put.
Additionneur et soustracteur
trolled inverter circuit of Fig. 10.28 and add 1 to its
negative two’s complement number.
Now the 4008s perform a regular binary addition. If
34 Illustrate the subtraction 42 – 23 = 19 using the complementing switch is up, the number on the B
the CMOS 4008. input is subtracted from the number on the A inputs. If
TÀF
ution: it is down, the sum is taken. The Cout of the MSB is
e 4008 are Illustrez
CMOS 4-bitlabinary
soustraction 42 − ignored.
adders. The 8-bit 23 = 19 The en
resultutilisant 7483
can range from 0111 1111 (+127)
mber on the A inputs (A7 to A0) is brought directly to 1000 0000 (–128).
Complementing
Switch
A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 A0 B0
1 (Subtract)
0 0 0 0 1 0 0 1 1 0 0 1 1 1 0 1
0 (Add)

1 1 1 0 1 0 0 0

A4 B4 A 3 B3 A2 B 2 A1 B1 A 4 B4 A3 B 3 A2 B 2 A1 B1

Cout 7483 Cin Cout 7483 Cin

S4 S3 S2 S1 S4 S3 S2 S1

27 26 25 24 23 22 21 20

Le CEight-bit
. 10.29 Two’s-Complement Adder/Subtractor, Illustrating the Subtraction 42 – 23 = 19.
out du MSB est ignoré
Pr. Younes JABRANE 2ème année CP 2023/2024 27 / 31
Comparateurs
228 2000 Solved Problems in Digital Electronics

A0 P0
0 1
B0 Q0
0
A1
B1
Out = 1 if P1
1 1
A2 A0 = B0 Q1
B2 A1 = B1 1
A2 = B2
A3 = B3 (
A3
B3 P0
1 0
Q0
Fig. 10.36 Binary Comparator for Comparing two 4- 0
bit Binary Strings.
si A0 et B0 sont égaux le XNOR supérieur produira un 1
10.45 Referring to Fig. 10.36 determine if the
P1
following
Il en va de même pour pairs
les of input
2ème, binary et
3ème numbers
4èmewillportes
Q XNOR
1 1
output a 1. 1
1
A3A12Aindiquant
la porte ET produit(a)un 1A0 = 1 0 1 1 l’égalité entre A et B
B3B2B1B0 = 1 0 1 1 (

sinon inégalité entre

(b) AA3Aet B0 = 0 1 1 0
2A 1A Fig. 10.37
B3B2B1B0 = 0 1 1 1
Solution: if the equality is not met. T
(a) When the A and B numbers are applied to the larger than B, and the A <
Pr. Younes JABRANE 2ème1’s,
inputs, each of the four Ex-NORs will output than 2023/2024
année CP A. 28 / 31
 29 / 31
Le 7485 a la caractéristique supplémentaire de dire quel nombre

2023/2024
2ème année CP
La sortie A  B est à 1 si A est supérieur à B
Arithmet
B3 1 16 VCC Le 7485 est un comparateur 4 bits A3
A2
A Input A1

sinon c’est A ≺ B qui est à 1

IA < B 2 15 A3 A0
IA = B 3 14 B2
B3
IA > B 4 13 A2 B2 A< B
B Input
B1 A= B
A> B 5 12 A1 B0 A> B

est le plus grand

Comparateurs

A= B 6 11 B1
IA < B

Pr. Younes JABRANE

A< B 7 10 A0 Expansion IA = B
Inputs
IA > B
GND 8 9 B0
(a) (b)
Fig. 10.38 The 7485 Four-bit Magnitude Comparator: (a) Pin Configuration, (b) Logic Symbols
A3 A3 A7 A3
A2 A2 A6 A2
A1 A1 A5 A1
A0 A0 A4 A0
Comparateurs
Extension
Le circuit comparateur de base peut être étendu
à n’importe quel nombre de bits
Les entrées d’extension IA < B et IA > B sont utilisées pour
l’extension à un système capable de comparaisons  4 bits
pour comparer deux nombres de 8 bits il faut 2 circuits 7485
donnez le schéma équivalent de cette combinaison
Arithmetic Circuits 229

A3
B3 1 16 VCC A2
A Input A1
IA < B 2 15 A3 A0

IA = B 3 14 B2
B3
IA > B 4 13 A2 B2 A< B
B Input
B1 A= B Ouptuts
A> B 5 12 A1 B0 A> B

A= B 6 11 B1
IA < B
A< B 7 10 A0 Expansion IA = B
Inputs
IA > B
GND 8 9 B0

(a) (b)

Pr. Younes JABRANE

Fig. 10.38 The 7485 Four-bit Magnitude Comparator: (a) Pin Configuration, (b) Logic Symbols.
2ème année CP 2023/2024 30 / 31
 A= B 6 11 B1
IA < B
Comparateurs A< B 7 10 A0 Expansion IA = B
Inputs
IA > B
GND 8 9 B0

(a) (b)

Fig. 10.38 The 7485 Four-bit Magnitude Comparator: (a) Pin Configuration, (b) Logic Symbols.

A3 A3 A7 A3
A2 A2 A6 A2
A1 A1 A5 A1
A0 A0 A4 A0
Low-order High-order
Inputs Inputs
B3 B3 A< B B7 B3 A< B 8-Bit
B2 B2 B6 B2
B1 7485 A= B 7485 A= B Comparison
B1 B5 B1
B0 Outputs
B0 A> B B4 B0 A> B

IA < B IA < B
1 IA = B IA = B
IA > B IA > B

Fig. 10.39 Magnitude Comparison of Two 8-bit Binary Strings (or Binary Words).

10.48 Describe a simple parity generator/checker the parity bit that is added must make the sum of all 5-
system. bits odd. In an even-parity system, the parity bit makes
the sum of all 5 bits even.
Solution:
The parity generator is the circuit that creates the
Parity systems are defined as either odd parity or even
parity bit. On the receiving end, a parity checker
parity. The parity system adds an extra bit to the digital
determines if the 5-bit result is of the right parity. The
information being transmitted. A 4-bit system will type of system (odd or2èmeeven)ann
must be decided before
Pr. Younes
require a fifth JABRANE
bit, an 8-bit system will require a ninth ée CP 2023/2024 31 / 31